Current compensation circuit and chip

Abstract

The utility model discloses a current compensation circuit and a chip, which are used for compensating the output current of a current type digital-to-analog converter, the current compensation circuit comprises a negative resistance unit connected with the output end of the current type digital-to-analog converter, and the negative resistance unit comprises a detection unit and a compensation unit, the detection unit generates a detection current based on an output voltage of the current-mode digital-to-analog converter. The compensation unit generates, based on the detection current, a compensation current opposite to the detection current in flow direction and for the injection node. According to the current compensation circuit and the chip, the detection unit shunts the output current of the current type digital-to-analog converter, the compensation unit generates the compensation current based on the detection current generated by shunting, the magnitude of the compensation current is adjustable, and the direction of the compensation current is opposite to that of the detection current. The output current of the current type digital-to-analog converter is compensated through the compensation current, so that the precision of the output current of the current type digital-to-analog converter under different loading conditions is improved.

Description

Current compensation circuit and chip Technical Field

[0001] This utility model belongs to the field of integrated circuit technology, specifically relating to a current compensation circuit and chip. Background Technology

[0002] Current-mode digital-to-analog converters (IDACs) are used in industrial control systems for computer data acquisition to provide precise and controllable output current. The accuracy of the IDC's output current affects the accuracy of the output load voltage, which in turn affects the accuracy of the voltage values ​​sampled by subsequent circuits. For example, when the output load of the IDC is too large, the leakage current flowing from the IDC's output to subsequent circuits will increase. Some chips also integrate a current-mode IDC and a voltage-mode IDC (VDAC), resulting in interconnected outputs of the two converters. In this case, a portion of the current-mode IDC's output current will flow into the feedback resistor of the VDAC, further affecting the accuracy of the current-mode IDC's output current.

[0003] The information disclosed in this background section is intended only to enhance the understanding of the overall background of this utility model and should not be construed as an admission or in any way implying that the information constitutes prior art known to those skilled in the art. Summary of the Invention

[0004] The purpose of this invention is to provide a current compensation circuit and chip that can compensate the output current of a current-type digital-to-analog converter to improve the accuracy of the output current.

[0005] To achieve the above objectives, a specific embodiment of this utility model provides a current compensation circuit for compensating the output current of a current-mode digital-to-analog converter. The current compensation circuit includes a negative resistance unit connected to the output terminal of the current-mode digital-to-analog converter, the negative resistance unit comprising:

[0006] The detection unit is connected to the output terminal of the current-mode digital-to-analog converter to form a node, so as to shunt the output current of the current-mode digital-to-analog converter to generate a detection current;

[0007] The compensation unit, connected to the detection unit and the node, generates a compensation current that flows in the opposite direction to the detection current and is used to inject into the node.

[0008] In one or more embodiments of this utility model, the detection unit includes a resistor, the first end of which is connected to the output terminal of a current-type digital-to-analog converter to form a node, and the second end of which is connected to a compensation unit.

[0009] In one or more embodiments of this utility model, the compensation unit includes a mirror module and an injection module. The mirror module is connected to the detection unit to generate a compensation current by proportionally mirroring the detection current. The injection module is connected to the mirror module and the node to inject the compensation current into the node.

[0010] In one or more embodiments of this utility model, the mirror module includes a first transistor and a mirror tube unit. The second terminal of the first transistor is connected to the detection unit to receive the detection current. The mirror tube unit is connected to the control terminal of the first transistor to perform proportional mirror detection to generate a compensation current. The injection module is connected to the mirror tube unit to deliver the compensation current to the injection node.

[0011] In one or more embodiments of the present invention, the mirror unit includes a first switch, a second switch, and a mirror transistor. The first end of the first switch is connected to the control end of the mirror transistor, and the second end of the first switch is used to receive the voltage from the control end of the first transistor. The first end of the second switch is connected to the control end of the mirror transistor, and the second end of the second switch is connected to the first end of the mirror transistor.

[0012] In one or more embodiments of this utility model, the mirror ratio between the mirror transistor unit and the first transistor is 2. n-1 : 1, n is greater than or equal to 1.

[0013] In one or more embodiments of this utility model, n represents the number of bits in the mirror unit.

[0014] In one or more embodiments of this utility model, the injection module includes a current mirror unit, which is connected to the mirror module and the node to inject the compensation current into the node after proportional mirroring.

[0015] This utility model also discloses a chip, including a current-type digital-to-analog converter and the aforementioned current compensation circuit. The output terminal of the current-type digital-to-analog converter is connected to an external load via a bus, and the current compensation circuit is connected to the bus to perform current compensation.

[0016] In one or more embodiments of this utility model, the chip further includes a voltage-type digital-to-analog converter and / or an analog-to-digital converter connected to a bus.

[0017] Compared with the prior art, the current compensation circuit and chip of this utility model shun the output current of the current-type digital-to-analog converter through the detection unit, and generate a compensation current based on the detection current generated by the compensation unit. The magnitude of the compensation current is adjustable, and the direction of the compensation current is opposite to that of the detection current. The compensation current compensates the output current of the current-type digital-to-analog converter, thereby improving the accuracy of the output current of the current-type digital-to-analog converter under different load conditions. The current compensation circuit and chip of this utility model have a simple circuit structure, low power consumption, and consume less resources and area. Attached Figure Description

[0018] To more clearly illustrate the technical solutions in the embodiments of this utility model or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in this utility model. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0019] Figure 1 is a circuit diagram of the current compensation circuit in one embodiment of the present invention. Detailed Implementation

[0020] To enable those skilled in the art to better understand the technical solutions of this utility model, the technical solutions of the embodiments of this utility model will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this utility model, and not all embodiments. Based on the embodiments of this utility model, all other embodiments obtained by those skilled in the art without creative effort should fall within the protection scope of this utility model.

[0021] The terms "coupled," "connected," or "linked" in this specification include both direct and indirect connections. An indirect connection is a connection made through an intermediate medium, such as an electrical conduction medium, which may have parasitic inductance or capacitance. Indirect connections may also include connections made through other active or passive devices to achieve the same or similar functional purpose, such as connections through switches, follower circuits, or other circuits or components. Furthermore, in utility models, terms such as "first" and "second" are primarily used to distinguish one technical feature from another, and do not necessarily require or imply any actual relationship, quantity, or order between these technical features.

[0022] In the detailed description of this specification, reference is made to the accompanying drawings, which form a part thereof, wherein like reference numerals always denote like parts, and wherein exemplary embodiments are shown by way of example that may be implemented. It should be understood that other embodiments may be utilized, and structural or logical changes may be made, without departing from the scope of this disclosure. Therefore, the following detailed description should not be considered limiting.

[0023] The various operations in the specification may be described sequentially as multiple discrete actions or operations in a manner most conducive to understanding the claimed subject matter. However, the order of description should not be construed as implying that these operations must be sequentially related. Specifically, these operations may not be performed in the order presented. The described operations may be performed in a different order than in the described embodiments. Various additional operations may be performed in additional embodiments and / or the described operations may be omitted.

[0024] For the purposes of this disclosure, the phrase “A and / or B” means (A), (B), or (A and B). For the purposes of this disclosure, the phrase “A, B and / or C” means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B and C).

[0025] Various components and devices may be referred to or shown in the singular (e.g., “transistor”, “transistor”, “switch”, etc.) in this document, but only for the convenience of discussion, and any element referred to in the singular may include multiple such elements as taught herein.

[0026] The description uses the phrases "in one embodiment," "in other embodiments," or "in some embodiments," each of which may refer to one or more of the same or different embodiments. Furthermore, the terms "comprising," "including," "having," etc., used with respect to embodiments of this disclosure are synonymous.

[0027] As shown in Figure 1, a current compensation circuit in this embodiment of the present invention is used to compensate the output current of a current-mode digital-to-analog converter (IDAC). The current compensation circuit includes a negative resistance unit 100 connected to the output terminal of the current-mode digital-to-analog converter (IDAC). The negative resistance unit 100 includes a detection unit 10 and a compensation unit.

[0028] The detection unit 10 is connected to the output terminal of the current-mode digital-to-analog converter (IDAC) to form node Q, so as to shunt the output current of the current-mode digital-to-analog converter (IDAC) to generate the detection current I1.

[0029] The compensation unit is connected to the detection unit 10 and node Q to generate a compensation current that flows in the opposite direction to the detection current I1 and is used to inject into node Q.

[0030] The detection unit 10 includes a resistor R. The first end of the resistor R is connected to the output of the current-type digital-to-analog converter (IDAC) to form a node Q. The second end of the resistor R is connected to the compensation unit.

[0031] The compensation unit includes a mirror module 21 and an injection module 22. The mirror module 21 is connected to the detection unit 10 to generate a compensation current by proportionally mirroring the detection current I1. The injection module 22 is connected to the mirror module 21 and node Q to inject the compensation current into node Q.

[0032] In one embodiment, the mirror module 21 includes a first transistor M1 and four mirror transistor units 211. The second terminal of the first transistor M1 is connected to the second terminal of the resistor R of the detection unit 10 to receive the detection current I1. All mirror transistor units 211 are connected to the control terminal of the first transistor M1 to perform proportional mirroring of the detection current I1 to generate a compensation current. The injection module 22 is connected to the mirror transistor units 211 to deliver the compensation current I2 to the injection node Q. Here, all the working mirror transistor units 211 will generate compensation current, and the injection module 22 can collect all the compensation currents.

[0033] Each mirror tube unit 211 includes a set of switches and mirror tubes. The first mirror tube unit 211 includes a first switch K11, a second switch K12 and a mirror tube M21. The second mirror tube unit 211 includes a first switch K21, a second switch K22 and a mirror tube M22. The third mirror tube unit 211 includes a first switch K31, a second switch K32 and a mirror tube M23. The fourth mirror tube unit 211 includes a first switch K41, a second switch K42 and a mirror tube M24.

[0034] The first terminal of the first switch K11 is connected to the control terminal of the mirror transistor M21, and the second terminal of the first switch K11 is connected to the control terminal of the first transistor M1 to receive the voltage of the control terminal of the first transistor M1. The first terminal of the second switch K12 is connected to the control terminal of the mirror transistor M21, and the second terminal of the second switch K12 is connected to the first terminal of the mirror transistor M21. The first terminal of the mirror transistor M21 is connected to the ground voltage.

[0035] The first terminal of the first switch K21 is connected to the control terminal of the mirror tube M22, the first terminal of the second switch K22 is connected to the control terminal of the mirror tube M22, the second terminal of the second switch K22 is connected to the first terminal of the mirror tube M22, and the first terminal of the mirror tube M22 is connected to the ground voltage.

[0036] The first terminal of the first switch K31 is connected to the control terminal of the mirror transistor M23, the first terminal of the second switch K32 is connected to the control terminal of the mirror transistor M23, the second terminal of the second switch K32 is connected to the first terminal of the mirror transistor M23, and the first terminal of the mirror transistor M23 is connected to the ground voltage.

[0037] The first terminal of the first switch K41 is connected to the control terminal of the mirror transistor M24, the first terminal of the second switch K42 is connected to the control terminal of the mirror transistor M24, the second terminal of the second switch K42 is connected to the first terminal of the mirror transistor M24, and the first terminal of the mirror transistor M24 is connected to the ground voltage.

[0038] In one embodiment, the second terminals of the first switch K21, the first switch K31, and the first switch K41 are all connected to the control terminal of the mirror transistor M21. That is, the subsequent mirror transistor unit 211 only operates after the first switch K11 is closed; the first switch K11 acts as a master switch. In other embodiments, the second terminals of the first switch K21, the first switch K31, and the first switch K41 can also be connected to the control terminal of the first transistor M1. In this case, each mirror transistor unit 211 can be controlled independently. Alternatively, the second terminal of the first switch K21 can be connected to the control terminal of the mirror transistor M21, the second terminal of the first switch K31 can be connected to the control terminal of the mirror transistor M22, and the second terminal of the first switch K41 can be connected to the control terminal of the mirror transistor M23. In this case, the normal operation of the subsequent mirror transistor unit 211 depends on the control of the first switch of the preceding mirror transistor unit 211.

[0039] The first transistor M1 and the mirror transistors M21, M22, M23, and M24 form a current mirror. When one of the mirror transistors needs to work normally to generate compensation current, the corresponding first and second switches must be closed (regardless of which mirror transistor is selected to generate compensation current, the first switch of the first transistor must be closed). When multiple mirror transistors need to generate compensation current, the corresponding first switches must all be closed (regardless of whether the first mirror transistor needs to generate compensation current, the first switch of the first transistor must be closed). However, it is possible to choose to close the corresponding second switch of one of the mirror transistors to achieve the current mirroring effect.

[0040] The mirror ratios of the first transistor M1, the mirror transistor M21 of the first-position mirror unit 211, the mirror transistor M22 of the second-position mirror unit 211, the mirror transistor M23 of the third-position mirror unit 211, and the mirror transistor M24 of the fourth-position mirror unit 211 are 1:1:2:4:8. The operation of the mirror transistors can be controlled according to the required compensation current. When more mirror units 211 are needed, the mirror ratio can be adjusted based on the mirror ratio between each mirror unit 211 and the first transistor M1, satisfying a 2:1 ratio. n-1 The mirror ratio is set to 1, where n is greater than or equal to 1, and n represents the number of bits in each mirror tube unit 211. In other embodiments, the mirror ratio can be set as needed.

[0041] As shown in Figure 1, the injection module 22 includes a current mirror unit, which is connected to the mirror module 21 and node Q to inject the compensation current I2 into node Q after proportional mirroring.

[0042] The current mirror unit includes a third transistor M3, a fourth transistor M4, a fifth transistor M5, and a sixth transistor M6. The control terminals of the third transistor M3 and the fourth transistor M4 are connected to the second terminal of the third transistor M3. The control terminals of the fifth transistor M5 and the sixth transistor M6, as well as the second terminal of the fifth transistor M5, are connected to the first terminal of the third transistor M3. The second terminal of the sixth transistor M6 is connected to the first terminal of the fourth transistor M4. The first terminals of the fifth transistor M5 and the sixth transistor M6 are connected to the power supply voltage. The second terminal of the third transistor M3 is simultaneously connected to the second terminals of all the mirror transistors. The second terminal of the fourth transistor M4 is connected to node Q to inject the compensation current of the mirror into node Q for current compensation. In other embodiments, the current mirror unit may employ a cascode current mirror.

[0043] The first transistor M1 and its mirror transistors M21, M22, M23, and M24 are N-channel MOSFETs, and the third transistor M3, fourth transistor M4, fifth transistor M5, and sixth transistor M6 are P-channel MOSFETs. In other embodiments, the first transistor M1 and its mirror transistors M21, M22, M23, and M24 are P-channel MOSFETs, and the third transistor M3, fourth transistor M4, fifth transistor M5, and sixth transistor M6 are N-channel MOSFETs.

[0044] The first terminal of the first transistor M1, the first terminals of the mirror transistors M21, M22, M23, and M24, the first terminal of the third transistor M3, the first terminal of the fourth transistor M4, the first terminal of the fifth transistor M5, and the first terminal of the sixth transistor M6 are the sources; the second terminal of the first transistor M1, the second terminals of the mirror transistors M21, M22, M23, and M24, the second terminal of the third transistor M3, the second terminal of the fourth transistor M4, the second terminal of the fifth transistor M5, and the second terminal of the sixth transistor M6 are the drains; the control terminal of the first transistor M1, the control terminals of the mirror transistors M21, M22, M23, and M24, the control terminals of the third transistor M3, the control terminals of the fourth transistor M4, the control terminals of the fifth transistor M5, and the control terminals of the sixth transistor M6 are the gates.

[0045] This embodiment also discloses a chip, including a current-mode digital-to-analog converter (IDAC) and the aforementioned current compensation circuit. The output of the current-mode IDAC is connected to an external load via a bus. The current compensation circuit is connected to the bus to form node Q for current compensation. The chip also includes a voltage-mode digital-to-analog converter (VDAC) and / or an analog-to-digital converter (ADC) connected to the bus. The current-mode IDAC, the voltage-mode IDAC, and / or the ADC constitute an industrial control system.

[0046] As shown in Figure 1, resistor Rp1 is the equivalent resistance of the feedback resistor of the voltage-type digital-to-analog converter (VDAC) and / or the sampling resistor of the analog-to-digital converter (ADC). The presence of resistor Rp1 will cause current shunting (current leakage) of the output current of the current-type digital-to-analog converter (IDAC), thereby reducing the current accuracy of the output current of the current-type digital-to-analog converter (IDAC). Resistor Rp2 is the equivalent resistance of the sampling resistor of the analog-to-digital converter that the user may connect later. The presence of resistor Rp2 will also cause current shunting, resulting in a decrease in the current accuracy of the output current of the current-type digital-to-analog converter (IDAC). Resistor Rload is the load that will be connected later.

[0047] Based on the actual input impedance of the connected bus, the mirror unit 211 can be configured to compensate the output current of the current-mode digital-to-analog converter (IDAC). The compensation current multiplier is 1-15 times the detection current. When current shunting occurs due to the presence of resistors, the current flowing into resistor R will decrease. This can be achieved by configuring the mirror unit 211 to mirror and increase the compensation current. Alternatively, when the load (resistor Rload) increases, the current flowing into resistor R will increase, and the compensation current will also increase. However, the direction of the compensation current is always opposite to the direction of current shunting, thus compensating for the output current of the current-mode IDAC and generating a negative resistance effect. This effectively addresses the output current accuracy issues of the current-mode IDAC caused by load changes and different input impedances of subsequent circuits. When current compensation is not required, the mirror unit 211 can be omitted, resulting in no static power consumption and no high-resistance nodes that may store charge, exhibiting PVT stability.

[0048] It will be apparent to those skilled in the art that this invention is not limited to the details of the exemplary embodiments described above, and that it can be implemented in other specific forms without departing from the spirit or essential characteristics of this invention. Therefore, the embodiments should be considered illustrative and non-limiting in all respects, and the scope of this invention is defined by the appended claims rather than the foregoing description. Thus, it is intended that all variations falling within the meaning and scope of equivalents of the claims be included within this invention. No reference numerals in the claims should be construed as limiting the scope of the claims.

[0049] Furthermore, it should be understood that although this specification describes embodiments, not every embodiment contains only one independent technical solution. This narrative style is merely for clarity. Those skilled in the art should consider the specification as a whole, and the technical solutions in each embodiment can also be appropriately combined to form other embodiments that can be understood by those skilled in the art.

Claims

1. A current compensation circuit, characterized in that, The current compensation circuit is used to compensate the output current of a current-mode digital-to-analog converter. The current compensation circuit includes a negative resistance unit connected to the output terminal of the current-mode digital-to-analog converter. The negative resistance unit includes a detection unit connected to the output terminal of the current-mode digital-to-analog converter to form a node, which shunts the output current of the current-mode digital-to-analog converter to generate a detection current; and a compensation unit connected to the detection unit and the node, which generates a compensation current based on the detection current, flowing in the opposite direction to the detection current and used to inject it into the node.

2. The current compensation circuit according to claim 1, characterized in that, The detection unit includes a resistor, the first end of which is connected to the output of a current-type digital-to-analog converter to form a node, and the second end of which is connected to a compensation unit.

3. The current compensation circuit according to claim 1, characterized in that, The compensation unit includes a mirror module and an injection module. The mirror module is connected to the detection unit to generate a compensation current by proportionally mirroring the detection current. The injection module is connected to the mirror module and the node to inject the compensation current into the node.

4. The current compensation circuit according to claim 3, characterized in that, The mirror module includes a first transistor and a mirror tube unit. The second terminal of the first transistor is connected to the detection unit to receive the detection current. The mirror tube unit is connected to the control terminal of the first transistor to perform proportional mirror detection to generate a compensation current. The injection module is connected to the mirror tube unit to deliver the compensation current to the injection node.

5. The current compensation circuit according to claim 4, characterized in that, The image transistor unit includes a first switch, a second switch, and an image transistor. The first end of the first switch is connected to the control end of the image transistor, and the second end of the first switch is used to receive the voltage from the control end of the first transistor. The first end of the second switch is connected to the control end of the image transistor, and the second end of the second switch is connected to the first end of the image transistor.

6. The current compensation circuit according to claim 4, characterized in that, The mirror image ratio between the mirror unit and the first transistor is 2. n-1 : 1, n is greater than or equal to 1.

7. The current compensation circuit according to claim 6, characterized in that, The number n represents the number of bits in the mirror unit.

8. The current compensation circuit according to claim 3, characterized in that, The injection module includes a current mirror unit, which is connected to the mirror module and the node to inject the compensation current into the node after proportional mirroring.

9. A chip, characterized in that, It includes a current-mode digital-to-analog converter and a current compensation circuit as described in any one of claims 1 to 8, wherein the output terminal of the current-mode digital-to-analog converter is connected to an external load via a bus, and the current compensation circuit is connected to the bus to perform current compensation.

10. The chip according to claim 9, characterized in that, The chip also includes a voltage-type digital-to-analog converter and / or an analog-to-digital converter connected to a bus.

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