4T2FC ferroelectric memory cell and memory array
By designing a 4T2FC ferroelectric memory cell, using four transistors and two ferroelectric capacitors, the problem of durability degradation and data retention capability decline in ferroelectric memory during high-frequency operation is solved, achieving more stable read/write and high-density in-memory computing.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- SHANGHAI SHENMING AOSI SEMICONDUCTOR TECHNOLOGY CO LTD
- Filing Date
- 2025-07-31
- Publication Date
- 2026-05-05
AI Technical Summary
Existing ferroelectric memories are prone to durability degradation, decreased data retention capability, and increased sensitivity to read/write interference during high-frequency operation.
Employing a 4T2FC structure with four transistors and two ferroelectric capacitors, it enhances data retention and write stability through differential polarization encoding and additional memory gate lines.
It improves data retention and read/write stability, enhances current control, reduces charge leakage, and supports high-density in-memory computing operations.
Smart Images
Figure CN224205519U_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of ferroelectric memory technology, and in particular to a 4T2FC ferroelectric memory cell and memory array. Background Technology
[0002] The development of artificial intelligence (AI) and neuromorphic computing has driven the demand for high-speed, high-density memory systems that support non-volatile in-memory computing (IMC). Compute-in-Memory (CiM) is an architecture that integrates computing functions directly into the storage array, reducing energy consumption for data movement.
[0003] Ferroelectric RAM (FRAM) is a new type of non-volatile memory (NVM) that can immediately capture and save critical data when power is interrupted. It is ideal for mission-critical data logging applications. Ferroelectric RAM adopts a low-power, miniaturized design and can provide instant non-volatility and almost unlimited endurance without affecting speed or energy efficiency.
[0004] Existing ferroelectric memories primarily employ ferroelectric field-effect transistors (FeFETs). FeFETs can possess stable multi-level states, allowing for the design of appropriate sensing circuits to detect current or threshold voltage, thus distinguishing between various states in AI applications (in-memory computing). However, due to polarization shielding effects and limitations imposed by ferroelectric domain dynamics, FeFETs are prone to durability degradation, decreased data retention capabilities, and increased sensitivity to read / write interference during high-frequency operation. Summary of the Invention
[0005] To address the shortcomings of existing technologies, the purpose of this application is to provide a 4T2FC ferroelectric memory cell and memory array, which achieves ferroelectric storage by employing four transistors and two ferroelectric capacitors, thereby improving data retention and read / write stability.
[0006] To achieve the above objectives, this application provides a 4T2FC ferroelectric memory cell, comprising:
[0007] A silicon substrate, wherein a first active device region and a second active device region are disposed thereon, which are isolated from each other;
[0008] A first storage transistor and a first control transistor are disposed on the first active device region, and the drain of the first storage transistor is electrically connected to the source of the first control transistor.
[0009] The second storage transistor and the second control transistor are disposed on the second active device region, and the source of the second storage transistor is electrically connected to the drain of the second control transistor.
[0010] The first ferroelectric capacitor and the second ferroelectric capacitor are respectively disposed above the gate stack structure of the first storage transistor and the second storage transistor.
[0011] Further, each of the first storage transistor, the second storage transistor, the first control transistor, and the second control transistor includes:
[0012] A gate stack structure is disposed on the active device region;
[0013] The source diffusion region is disposed on the active device region and located on one side of the gate stack structure;
[0014] The drain diffusion region is disposed on the active device region and located on the other side of the gate stack structure;
[0015] The first ferroelectric capacitor is disposed between the first plate line and the gate stack structure;
[0016] The second ferroelectric capacitor is disposed between the second plate line and the gate stack structure.
[0017] Furthermore, it also includes:
[0018] The storage gate line is connected to the gate stack structure of the first storage transistor and the second storage transistor, respectively;
[0019] The control line is electrically connected to the gate stack structure of the first control transistor and the second control transistor;
[0020] The source line is electrically connected to the source diffusion region of the first storage transistor and / or the second storage transistor.
[0021] The bit line is electrically connected to the drain diffusion region of the first control transistor and / or the second control transistor.
[0022] Furthermore, it also includes:
[0023] The first storage gate contact hole and the second storage gate contact hole are respectively connected to the gate stack structure of the first storage transistor and the second storage transistor;
[0024] The first storage gate contact landing pad and the second storage gate contact landing pad are respectively connected to the gate stack structure of the first storage transistor and the second storage transistor;
[0025] The storage gate line is coupled to the first storage transistor gate and the second storage transistor gate through the first storage gate contact landing pad and the second storage gate contact landing pad.
[0026] Furthermore, it also includes a first through-hole landing pad and a second through-hole landing pad, wherein the first through-hole landing pad is connected to the storage gate line and the bottom electrode of the first ferroelectric capacitor, respectively, and the second through-hole landing pad is connected to the storage gate line and the bottom electrode of the second ferroelectric capacitor, respectively.
[0027] Furthermore, the gate stack structure includes: a gate oxide layer, a high dielectric constant dielectric layer, and a TiN gate electrode; the gate oxide layer is disposed on the active device region; the high dielectric constant dielectric layer and the TiN gate electrode are sequentially stacked on the gate oxide layer.
[0028] Furthermore, it also includes an interlayer dielectric disposed on the source diffusion region and the drain diffusion region, wherein the interlayer dielectric has multiple contact holes and the multiple contact holes are filled with conductive metal.
[0029] Furthermore, each of the first ferroelectric capacitor and the second ferroelectric capacitor includes: a TiN bottom electrode, a ferroelectric layer, and a TiN top electrode.
[0030] Furthermore, the silicon substrate is also provided with shallow trench isolation regions, which respectively surround the first active device region and the second active device region, and the shallow trench isolation regions are filled with oxide.
[0031] To achieve the above objectives, this application provides a memory array comprising a plurality of 4T2FC ferroelectric memory cells as described above.
[0032] The 4T2FC ferroelectric memory cell provided in this application achieves ferroelectric storage by using four transistors and two ferroelectric capacitors, which improves durability while enhancing data retention and write stability.
[0033] Other features and advantages of this application will be set forth in the following description, and will be apparent in part from the description, or may be learned by practicing this application. Attached Figure Description
[0034] The accompanying drawings are provided to further illustrate the present application and form part of the specification. Together with the embodiments of the present application, they serve to explain the present application but do not constitute a limitation thereof. In the drawings:
[0035] Figure 1 This is a schematic diagram of the 4T2FC ferroelectric memory cell structure according to an embodiment of this application;
[0036] Figure 2 This is a top view of a 4T2FC ferroelectric memory cell according to an embodiment of this application. Detailed Implementation
[0037] The preferred embodiments of this application are described below with reference to the accompanying drawings. It should be understood that the preferred embodiments described herein are for illustration and explanation only and are not intended to limit this application.
[0038] Embodiments of this application will now be described in more detail with reference to the accompanying drawings. While some embodiments of this application are shown in the drawings, it should be understood that this application can be implemented in various forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided to provide a more thorough and complete understanding of this application. It should be understood that the drawings and embodiments of this application are for illustrative purposes only and are not intended to limit the scope of protection of this application.
[0039] The term "comprising" and its variations as used herein are open-ended inclusions, meaning "including but not limited to". The term "based on" means "at least partially based on". The term "one embodiment" means "at least one embodiment"; the term "another embodiment" means "at least one additional embodiment"; the term "some embodiments" means "at least some embodiments". Definitions of other terms will be given in the description below.
[0040] It should be noted that the terms "first" and "second" may be used in this application only to distinguish different devices, components or parts, and are not used to define the order of functions performed by these devices, components or parts or their interdependence.
[0041] It should be noted that the terms "one" and "more" used in this application are illustrative rather than restrictive, and those skilled in the art should understand that, unless explicitly stated otherwise in the context, they should be understood as "one or more". "More" should be understood as two or more.
[0042] The following terms may be used in this application:
[0043] 4T2FC (four transistors and two ferroelectric capacitors) ferroelectric memory cell: A ferroelectric memory cell containing 4 transistors and 2 ferroelectric capacitors;
[0044] CFA: First Ferroelectric Capacitor;
[0045] CFB: Second ferroelectric capacitor;
[0046] CT (Control Transistor): A control transistor used to enable or disable access to the memory path;
[0047] ST (Storage Transistor): A storage transistor that serves as the primary switch for storing and sensing storage states;
[0048] PLA: First Plate Line;
[0049] PLB: Second Plate Line;
[0050] SGL (Storage Gate Line): The storage gate line connects to the gate of the storage transistor and is used to maintain the integrity of the ferroelectric gate charge after a write operation.
[0051] BL (Bit Line): The wire connecting the drain of the control transistor, used as a channel for data reading;
[0052] SL (Source Line): The source line is the wire that connects to the source of the storage transistor. It serves as a current loop or voltage reference line and works with the bit line to complete data read and write operations.
[0053] CL (Control Line): The control line is a wire connected to the gate of the control transistor and is used to control the conduction and cutoff of the control transistor.
[0054] Definitions for other terms will be provided in the following description.
[0055] Example 1
[0056] In an embodiment of this application, a 4T2FC ferroelectric memory cell is provided, comprising: a silicon substrate, wherein a first active device region and a second active device region isolated from each other are provided on the silicon substrate; a first storage transistor and a first control transistor are disposed on the first active device region, and the drain of the first storage transistor is electrically connected to the source of the first control transistor; a second storage transistor and a second control transistor are disposed on the second active device region, and the source of the second storage transistor is electrically connected to the drain of the second control transistor; and a first ferroelectric capacitor and a second ferroelectric capacitor are respectively disposed above the gate stack structure of the first storage transistor and the second storage transistor.
[0057] Figure 1 This is a schematic diagram of the 4T2FC ferroelectric memory cell structure according to an embodiment of this application. Figure 2 This is a top view of a 4T2FC ferroelectric memory cell according to an embodiment of this application. Reference will be made below. Figure 1 and Figure 2 The 4T2FC ferroelectric memory cell of the present application embodiment will be described in detail.
[0058] The 4T2FC ferroelectric memory cell of this application embodiment includes:
[0059] A silicon substrate 101 is provided with a first active device region 1011 and a second active device region 1012, and a shallow trench isolation region 1013 for isolating the first active device region 1011 and the second active device region 1012. An oxide (such as SiO2) is deposited in the shallow trench isolation region 1013.
[0060] The first gate stack structure 102, the second gate stack structure 103, the third gate stack structure 104, and the fourth gate stack structure 105 are all disposed on the silicon substrate 101. The first gate stack structure 102 and the second gate stack structure 103 are located on the first active device region 1011 to form the gates of a first control transistor and a first storage transistor connected in series; the third gate stack structure 104 and the fourth gate stack structure 105 are located on the second active device region 1012 to form the gates of a second storage transistor and a second control transistor connected in series.
[0061] Both the first active device region 1011 and the second active device region 1012 are provided with a drain diffusion region 121, a drain-source diffusion region 122, and a source diffusion region 123. The drain diffusion region 121 is respectively disposed on the side of the first gate stack structure 102 away from the second gate stack structure 103 and on the side of the fourth gate stack structure 105 away from the third gate stack structure 104, serving as the drain of two control transistors. The drain-source diffusion region 122 is respectively disposed between the first gate stack structure 102 and the second gate stack structure 103, and between the third gate stack structure 104 and the fourth gate stack structure 105, serving simultaneously as the drain of a storage transistor and the source of a control transistor. The source diffusion region 123 is disposed on the side of the second gate stack structure 103 away from the first gate stack structure 102 and on the side of the third gate stack structure 104 away from the fourth gate stack structure 105, serving as the source of two storage transistors.
[0062] The first storage gate contact hole 106 and the second storage gate contact hole 107 are respectively disposed on the second gate stack structure 103 and the third gate stack structure 104.
[0063] The first storage gate contact landing pad 108 and the second storage gate contact landing pad 109 are respectively disposed on the first storage gate contact hole 106 and the second storage gate contact hole 107, for laying the first storage gate line 110 and the second storage gate line 111.
[0064] The first storage gate line 110 and the second storage gate line 111 are respectively provided with a first through-hole contact pad 112 and a second through-hole contact pad 113 on their top surfaces.
[0065] Two ferroelectric capacitors 116 have a first bottom electrode metal pad 114 and a second bottom electrode metal pad 115 respectively disposed on the first through hole contact pad 112 and the second through hole contact pad 113 at their bottom; and a first top electrode plate 117 and a second top electrode plate 118 respectively disposed on their top for connecting the first plate line 119 and the second plate line 120.
[0066] The first control line 128 and the second control line 129 are respectively arranged on the first gate stack structure 102 and the fourth gate stack structure 105.
[0067] The source line 124 is electrically connected to the source diffusion region 123 through the first conductive metal contact hole 127 arranged in the interlayer medium on the first active device region 1011 and the second active device region 1012, respectively.
[0068] Bit lines 125 are electrically connected to drain diffusion regions 121 through second conductive metal contact holes 126 arranged in the interlayer dielectric on the first active device region 1011 and the second active device region 1012, respectively.
[0069] In the embodiments of this application, each of the first gate stack structure 102, the second gate stack structure 103, the third gate stack structure 104, and the fourth gate stack structure 105, from bottom to top, includes: a gate oxide layer 130, a high dielectric constant (high k) dielectric layer 131, and a TiN gate electrode 132. TiN (titanium nitride) is commonly used as a conductive material for electrodes.
[0070] In the embodiments of this application, the two ferroelectric capacitors 116, from bottom to top, include: a TiN bottom electrode 1161, an HfZrO2 ferroelectric layer 1162, and a TiN top electrode 1163. HfZrO2 (HZO) is hafnium zirconium oxide, a high-k (dielectric constant) dielectric material with ferroelectric properties.
[0071] In the embodiments of this application, the first storage gate line 110 and the second storage gate line 111 are respectively connected to the gates of two storage transistors and respectively coupled to the bottom electrodes of two ferroelectric capacitors 116. These are used to synchronously apply a differential voltage in coordination with the first plate line 119 and the second plate line 120, inducing the two ferroelectric capacitors 116 to reverse polarize. This polarization of the ferroelectric capacitors 116 modulates the threshold voltages of the two storage transistors, thereby achieving differential writing of logic "0" or "1". The first storage gate line 110 and the second storage gate line 111 are also used to prevent charge leakage from the ferroelectric capacitors 116 after the write operation, thus maintaining the integrity of the ferroelectric gate charge.
[0072] Example 2
[0073] In embodiments of this application, a memory array is also provided, comprising multiple 4T2FC ferroelectric memory cells as described above. This memory array employing 4T2FC ferroelectric memory cells, where each memory cell consists of two pairs of storage transistors and control transistors, enhances current control, reduces charge leakage, and improves retention (the ability of data to remain after power loss) and durability. Differential polarization encoding enables high-density in-memory computation operations. Additional storage gate lines (SGLs) prevent charge leakage from the ferroelectric capacitors after writing, thereby improving data retention and write stability.
[0074] It will be understood by those skilled in the art that the above descriptions are merely preferred embodiments of this application and are not intended to limit this application. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art can still modify the technical solutions described in the foregoing embodiments or make equivalent substitutions for some of the technical features. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.
Claims
1. A 4T2FC ferroelectric memory cell, characterized in that, include: A silicon substrate, wherein a first active device region and a second active device region are disposed thereon, which are isolated from each other; A first storage transistor and a first control transistor are disposed on the first active device region, and the drain of the first storage transistor is electrically connected to the source of the first control transistor. The second storage transistor and the second control transistor are disposed on the second active device region, and the source of the second storage transistor is electrically connected to the drain of the second control transistor. The first ferroelectric capacitor and the second ferroelectric capacitor are respectively disposed above the gate stack structure of the first storage transistor and the second storage transistor.
2. The 4T2FC ferroelectric memory cell according to claim 1, characterized in that, Each of the first storage transistor, the second storage transistor, the first control transistor, and the second control transistor includes: A gate stack structure is disposed on the active device region; The source diffusion region is disposed on the active device region and located on one side of the gate stack structure; The drain diffusion region is disposed on the active device region and located on the other side of the gate stack structure; The first ferroelectric capacitor is disposed between the first plate line and the gate stack structure; The second ferroelectric capacitor is disposed between the second plate line and the gate stack structure.
3. The 4T2FC ferroelectric memory cell according to claim 2, characterized in that, Also includes: The storage gate line is connected to the gate stack structure of the first storage transistor and the second storage transistor, respectively; The control line is electrically connected to the gate stack structure of the first control transistor and the second control transistor; The source line is electrically connected to the source diffusion region of the first storage transistor and / or the second storage transistor. The bit line is electrically connected to the drain diffusion region of the first control transistor and / or the second control transistor.
4. The 4T2FC ferroelectric memory cell according to claim 3, characterized in that, Also includes: The first storage gate contact hole and the second storage gate contact hole are respectively connected to the gate stack structure of the first storage transistor and the second storage transistor; The first storage gate contact landing pad and the second storage gate contact landing pad are respectively connected to the gate stack structure of the first storage transistor and the second storage transistor; The storage gate line is coupled to the first storage transistor gate and the second storage transistor gate through the first storage gate contact landing pad and the second storage gate contact landing pad.
5. The 4T2FC ferroelectric memory cell according to claim 3, characterized in that, It also includes a first through-hole landing pad and a second through-hole landing pad, wherein the first through-hole landing pad is connected to the storage gate line and the bottom electrode of the first ferroelectric capacitor, respectively, and the second through-hole landing pad is connected to the storage gate line and the bottom electrode of the second ferroelectric capacitor, respectively.
6. The 4T2FC ferroelectric memory cell according to claim 2, characterized in that, The gate stack structure includes: a gate oxide layer, a high dielectric constant dielectric layer, and a TiN gate electrode; the gate oxide layer is disposed on the active device region; the high dielectric constant dielectric layer and the TiN gate electrode are stacked sequentially on the gate oxide layer.
7. The 4T2FC ferroelectric memory cell according to claim 3, characterized in that, It also includes an interlayer dielectric disposed on the source diffusion region and the drain diffusion region, wherein the interlayer dielectric has a plurality of contact holes and the plurality of contact holes are filled with conductive metal; the source line and the bit line are electrically connected to the source diffusion region and the drain diffusion region through the conductive metal in the contact holes, respectively.
8. The 4T2FC ferroelectric memory cell according to claim 1, characterized in that, Each of the first ferroelectric capacitor and the second ferroelectric capacitor includes: a TiN bottom electrode, a ferroelectric layer, and a TiN top electrode.
9. The 4T2FC ferroelectric memory cell according to claim 1, characterized in that, The silicon substrate is further provided with shallow trench isolation regions, which respectively surround the first active device region and the second active device region, and the shallow trench isolation regions are filled with oxide.
10. A memory array, characterized in that, It includes the 4T2FC ferroelectric memory cell as described in any one of claims 1-9.