Enhanced GaN power device structure with built-in distributed current sampling
By incorporating a built-in distributed current sampling enhanced GaN power device structure, the problems of heat generation and power loss caused by current changes during the switching process of GaN power devices are solved, achieving high-precision current monitoring and safety protection.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- CHENGDU SILICON NITRIDE TECH CO LTD
- Filing Date
- 2025-04-10
- Publication Date
- 2026-05-05
AI Technical Summary
Existing GaN power devices suffer from heat generation and device degradation due to current changes during switching, and the series sampling resistor increases power loss.
An enhanced GaN power device structure with built-in distributed current sampling is adopted. The distributed sampling transistor shares the gate and drain with the main die to achieve real-time current monitoring. A non-active region is added in the disconnected region to improve sampling accuracy.
It achieves high-precision current monitoring, avoids the reduction in sampling accuracy caused by current concentration, reduces power loss, and improves the safety and efficiency of the device.
Smart Images
Figure CN224205522U_ABST
Abstract
Description
Technical Field
[0001] This utility model relates to the technical field, and more specifically, to an enhanced GaN power device structure with built-in distributed current sampling. Background Technology
[0002] Gallium nitride (GaN) is one of the representative third-generation semiconductor materials, possessing a high bandgap. Due to the advantage of its wide bandgap, GaN materials exhibit a higher critical breakdown electric field strength compared to traditional Si materials. GaN materials also have higher thermal conductivity than Si, making them more suitable for applications in extreme environments such as high temperatures. Furthermore, GaN can form AlGaN / GaN heterojunctions with AlGaN, where spontaneous polarization and piezoelectric polarization effects result in a high concentration of two-dimensional electron gas (2DEG) at the AlGaN / GaN heterojunction interface.
[0003] In practical applications, GaN power devices are constantly switching on and off, resulting in continuously changing currents. Especially during the turn-on process, excessive current can lead to overheating, device characteristic degradation, and even device burnout. To ensure safe operation of the devices and the power circuit, it is necessary to monitor the source and drain currents of the GaN power devices to determine their operating status and provide feedback to the driver or controller. For example, if the current is too high during turn-on, the drive signal can be adjusted to reduce the frequency or drive voltage. The most common monitoring method is to connect a sampling resistor in series below the source of the GaN power device and monitor the voltage change across this resistor to achieve real-time monitoring of the device's current. However, this series resistor introduces additional power losses, reducing the overall efficiency of the power system. Utility Model Content
[0004] The purpose of this invention is to provide an enhanced GaN power device structure with built-in distributed current sampling to solve the power loss problem in the prior art.
[0005] This utility model is achieved through the following technical solution:
[0006] An enhanced GaN power device structure with built-in distributed current sampling includes a first interconnect metal serving as the source pad of the main control chip, a source interconnect metal of the sampling transistor, a gate interconnect metal serving as the interconnect between the sampling transistor and the gate metal of the main control chip, and a second interconnect metal serving as the drain pad. The gate interconnect metal is arranged intersectingly with the first interconnect metal. One end of the source interconnect metal of the sampling transistor is connected to a fourth interconnect metal serving as the source pad of the sampling transistor, and one end of the gate interconnect metal is connected to a third interconnect metal serving as the gate pad.
[0007] It also includes an active region, which includes several groups of gate units located between the first interconnect metal and the second interconnect metal. It also includes a main control chip source ohm metal and a sampling transistor source ohm metal. A first non-active region is formed between the main control chip source ohm metal and the sampling transistor source ohm metal, and a second non-active region is formed between the second interconnect metal and the gate units.
[0008] Preferably, the gate unit includes a PGaN and a gate metal, and a main die gate opening and a sampling tube gate opening are provided between the PGaN and the gate metal. The gate metal and the gate interconnect metal are connected through a first through-hole.
[0009] Preferably, it further includes a fifth interconnect metal, which is connected to the main source electrode ohmic metal through a second via and to the first interconnect metal through a third via.
[0010] Preferably, the ohmic metal of the sampling tube source electrode is connected to the sampling tube source electrode interconnect metal through a fourth through hole.
[0011] Preferably, it further includes a sixth interconnect metal and a drain ohmic metal, wherein the sixth interconnect metal is connected to the drain ohmic metal through a fifth via, and the sixth interconnect metal is connected to the second interconnect metal through a sixth via.
[0012] Preferably, one end of the source interconnect metal of the sampling tube is connected to the fourth interconnect metal through a seventh through hole.
[0013] Preferably, one end of the gate interconnect metal is connected to the third interconnect metal through an eighth via.
[0014] Preferably, the gate units are provided in multiple groups.
[0015] The technical solution of this utility model has at least the following advantages and beneficial effects:
[0016] The structure described above, employing this invention, features a built-in distributed current sampling transistor, forming a structure with high sampling accuracy. The distributed sampling transistor shares the gate and drain with the main die of the GaN power device. The current value of the main die of the GaN power device can be accurately calculated using the current ratio between the distributed sampling transistor and the main die, and the current of the distributed sampling transistor itself. This allows for real-time monitoring of the GaN power device current by monitoring the current of the distributed sampling transistor. The current signal output by the distributed sampling transistor serves as the input signal for overcurrent protection circuits, enabling safe operation such as overcurrent protection for the GaN power device. Distributed current sampling ensures uniform sampling of the device, avoiding the risk of reduced sampling accuracy due to concentrated current or localized overheating. This device utilizes a PGaN structure for enhancement mode. The sampling transistor gate opening and the main die gate opening corresponding to the region between the source of the distributed sampling transistor and the source of the main die are also designed to be disconnected. Furthermore, a non-active region is added at the horizontal position corresponding to the disconnected region, further improving the sampling accuracy of the sampling transistor. Attached Figure Description
[0017] To more clearly illustrate the technical solutions of the embodiments of this utility model, the drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this utility model and should not be regarded as a limitation on the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.
[0018] Figure 1 This is a schematic diagram of the overall structure of this utility model;
[0019] Figure 2 This utility model Figure 1 Enlarged view of point A in the middle;
[0020] Figure 3 This utility model Figure 1 Enlarged view of point B in the middle.
[0021] Icons: 1-Gate metal, 2-Main control chip gate opening, 3-PGaN, 4-Main control chip source metal, 5-Fifth interconnect metal, 6-Sixth interconnect metal, 7-Drain metal, 8-Gate interconnect metal, 9-Sampling transistor source interconnect metal, 10-Sampling transistor source metal, 11-First interconnect metal, 12-Third interconnect metal, 13-Second non-active region, 14-Fourth interconnect metal, 15-Second interconnect metal, 16-Active region, 17-First non-active region, 18-Sampling transistor gate opening, 19-Second via, 20-Third via, 21-Fifth via, 22-Sixth via, 23-Fourth via. Detailed Implementation
[0022] To make the objectives, technical solutions, and advantages of the embodiments of this utility model clearer, the technical solutions of the embodiments of this utility model will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this utility model, and not all embodiments. The components of the embodiments of this utility model described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.
[0023] Please refer to Figures 1-3 An enhanced GaN power device structure with built-in distributed current sampling includes a first interconnect metal 11 serving as the source pad of the main control chip, a source interconnect metal 9 of the sampling transistor, a gate interconnect metal 8 serving as the interconnect between the sampling transistor and the gate metal 1 of the main control chip, and a second interconnect metal 15 serving as the drain pad. The gate interconnect metal 8 is arranged intersectingly with the first interconnect metal 11. One end of the source interconnect metal 9 of the sampling transistor is connected to a fourth interconnect metal 14 serving as the source pad of the sampling transistor, and one end of the gate interconnect metal 8 is connected to a third interconnect metal 12 serving as the gate pad. It also includes an active region 16, which includes a plurality of gate units located between the first interconnect metal 11 and the second interconnect metal 15. It also includes a source ohmic metal 4 of the main control chip and a source ohmic metal 10 of the sampling transistor. A first non-active region 17 is formed between the source ohmic metal 4 of the main control chip and the source ohmic metal 10 of the sampling transistor, and a second non-active region 13 is formed between the second interconnect metal 15 and the gate units.
[0024] The structure described above, employing this invention, features a built-in distributed current sampling transistor, forming a structure with high sampling accuracy. The distributed sampling transistor shares the gate and drain with the main die of the GaN power device. The current value of the main die of the GaN power device can be accurately calculated using the current ratio between the distributed sampling transistor and the main die, and the current of the distributed sampling transistor itself. This allows for real-time monitoring of the GaN power device current by monitoring the current of the distributed sampling transistor. The current signal output by the distributed sampling transistor serves as the input signal for overcurrent protection circuits, enabling safe operation such as overcurrent protection for the GaN power device. Distributed current sampling ensures uniform sampling of the device, avoiding the risk of reduced sampling accuracy due to concentrated current or localized overheating. This device utilizes a PGaN 3 structure for enhancement-mode operation. The sampling transistor gate opening and the main die gate opening in the region between the source of the distributed sampling transistor and the source of the main die are also disconnected. Furthermore, a non-active region 16 is added at the horizontal position corresponding to the disconnected region, further improving the sampling accuracy of the sampling transistor.
[0025] In one exemplary embodiment of this utility model, the gate unit includes a PGaN 3 and a gate metal 1. A main die gate opening 2 and a sampling tube gate opening 18 are provided between the PGaN 3 and the gate metal 1. The gate metal 1 and the gate interconnect metal 8 are connected through a first through hole.
[0026] Specifically, it also includes a fifth interconnect metal 5 disposed below the first interconnect metal 11, a main control chip source ohm metal 4 disposed below the fifth interconnect metal 5, the fifth interconnect metal being connected to the main control chip source ohm metal 4 through a second via 19, and the fifth interconnect metal 5 being connected to the first interconnect metal 11 through a third via 20; a sampling tube source ohm metal 10 disposed below the sampling tube source interconnect metal in the active region, the sampling tube source ohm metal 10 being connected to the sampling tube source interconnect metal 9 through a fourth via 23; a sixth interconnect metal 6 disposed below the second interconnect metal 15, a drain ohm metal 7 disposed below the sixth interconnect metal 6, the sixth interconnect metal 6 being connected to the drain ohm metal 7 through a fifth via 21, and the sixth interconnect metal 6 being connected to the second interconnect metal 15 through a sixth via; one end of the sampling tube source interconnect metal 9 being connected to the fourth interconnect metal 14 through a seventh via; and one end of the gate interconnect metal 8 being connected to the third interconnect metal 12 through an eighth via.
[0027] Furthermore, this structure employs distributed sampling, meaning each capacitor (CE11) of the main power chip has its own sampling structure. This avoids the low sampling accuracy issues caused by uneven current distribution when sampling from a single capacitor. The gate openings of the main power chip and the sampling transistor are disconnected, ensuring that the PGaN3 between the main power chip gate opening 2 and the sampling transistor gate opening 18 does not contact the gate metal 1. This prevents the channel beneath the PGaN3 between the main power chip gate opening 2 and the sampling transistor gate opening 18 from opening when the device is powered on. If the channel were not disconnected, the area beneath the disconnected PGaN3 would conduct when the device is powered on, causing the current flowing through this area to randomly flow to the source of the main power chip or the sampling transistor. This would cause the current ratio between the sampling transistor and the main power chip to deviate from the design value, resulting in inaccurate sampling. Meanwhile, a first non-active region 17 is added between the source metal 4 of the main control chip and the source metal 10 of the sampling transistor, and a second non-active region 13 is added at the same horizontal position between the gate metal 1 and the drain metal 7. This can avoid the sampling inaccuracy caused by the random collection of the current flowing out of the drain by the source of the main control chip or the source of the sampling transistor, and further improve the sampling accuracy.
[0028] The manufacturing method of this invention includes the following steps:
[0029] PGaN 3 is etched on the GaN epitaxial layer, followed by passivation of the surface by growing an insulating dielectric. N-ion implantation is performed outside the active region 16, inside the second non-active region 13, and inside the first non-active region 17 to form the active region 16, the second non-active region 13, and the first non-active region 17. The dielectric is etched to form ohmic contact openings. Ohmic metal is deposited and etched to form source and drain ohmic metals, including drain ohmic metal 7, main chip source ohmic metal 4, and sampling diode source ohmic metal 10. An insulating dielectric is grown, and openings are made in the insulating dielectric of the gate region to form main chip gate opening 2. A sampling tube gate opening 18 is formed, gate metal is deposited and etched to form gate metal 1, insulating dielectric IMD1 is grown, and through-holes are formed by etching the insulating dielectric above the drain ohmic metal 7, the main control chip source ohmic metal 4, the sampling tube source ohmic metal 10, and the gate metal 1. W metal is then filled to form the first through-hole, the second through-hole 19, the fourth through-hole 23, and the fifth through-hole 21, respectively. A first layer of interconnect metal is deposited and etched to form the drain sixth interconnect metal 6, the main control chip fifth interconnect metal 5, the gate interconnect metal 8, and the sampling tube source interconnect metal 9. Insulating dielectric I is then grown. MD2, an insulating dielectric is etched above the sixth interconnect metal 6 of the drain, the fifth interconnect metal 5 of the main source, the gate interconnect metal 8 and the source interconnect metal 9 of the sampling tube to form vias and fill them with W metal to form the sixth via 22, the third via 20, the eighth via and the seventh via, respectively. A second layer of interconnect metal is deposited and etched to form the second interconnect metal 15 of the drain, the first interconnect metal 11 of the main source, the third interconnect metal 12 and the fourth interconnect metal 14, respectively.
[0030] The above are merely preferred embodiments of this utility model and are not intended to limit the scope of this utility model. Various modifications and variations can be made to this utility model by those skilled in the art. Any modifications, equivalent substitutions, or improvements made within the spirit and principles of this utility model should be included within the protection scope of this utility model.
Claims
1. An enhanced GaN power device structure with built-in distributed current sampling, characterized in that, It includes a first interconnect metal (11) used as the source pad of the main control chip, a source interconnect metal (9) of the sampling tube, a gate interconnect metal (8) used as the interconnect of the gate metal (1) of the sampling tube and the main control chip, and a second interconnect metal (15) used as the drain pad. The gate interconnect metal (8) is arranged to cross the first interconnect metal (11) adjacent to it. One end of the source interconnect metal (9) of the sampling tube is connected to a fourth interconnect metal (14) used as the source pad of the sampling tube. One end of the gate interconnect metal (8) is connected to a third interconnect metal (12) used as the gate pad. It also includes an active region (16), which includes several sets of gate units. The gate units are located between the first interconnect metal (11) and the second interconnect metal (15). It also includes a main control chip source ohmic metal (4) and a sampling tube source ohmic metal (10). A first non-active region (17) is formed between the main control chip source ohmic metal (4) and the sampling tube source ohmic metal (10). A second non-active region (13) is formed between the second interconnect metal (15) and the gate units.
2. The enhanced GaN power device structure with built-in distributed current sampling according to claim 1, characterized in that, The gate unit includes a PGaN (3) and a gate metal (1). A main die gate opening (2) and a sampling tube gate opening (18) are provided between the PGaN (3) and the gate metal (1). The gate metal (1) and the gate interconnect metal (8) are connected through a first through hole.
3. The enhanced GaN power device structure with built-in distributed current sampling according to claim 1, characterized in that, It also includes a fifth interconnect metal (5), which is connected to the main core source electrode ohmic metal (4) through a second through hole (19) and is connected to the first interconnect metal (11) through a third through hole (20).
4. The enhanced GaN power device structure with built-in distributed current sampling according to claim 1, characterized in that, The sampling tube source electrode ohmic metal (10) is connected to the sampling tube source electrode interconnect metal (9) through the fourth through hole (23).
5. The enhanced GaN power device structure with built-in distributed current sampling according to claim 1, characterized in that, It also includes a sixth interconnect metal (6) and a drain ohmic metal (7), wherein the sixth interconnect metal (6) is connected to the drain ohmic metal (7) through a fifth via (21), and the sixth interconnect metal (6) is connected to the second interconnect metal (15) through a sixth via (22).
6. The enhanced GaN power device structure with built-in distributed current sampling according to claim 1, characterized in that, One end of the sampling tube source interconnect metal (9) is connected to the fourth interconnect metal (14) through the seventh through hole.
7. The enhanced GaN power device structure with built-in distributed current sampling according to claim 1, characterized in that, One end of the gate interconnect metal (8) is connected to the third interconnect metal (12) through an eighth through hole.
8. The enhanced GaN power device structure with built-in distributed current sampling according to claim 1, characterized in that, The gate unit is provided in multiple groups.