Packaging structure of superconducting quantum chip and electronic equipment

Abstract

The utility model provides a packaging structure of a superconducting quantum chip and electronic equipment, and relates to the technical field of superconducting quantum. Through a dual airtight packaging mode, the problem that a functional circuit of the superconducting quantum chip is oxidized in the packaging process is solved, the surface loss of the superconducting quantum chip and the related loss of materials are inhibited, the high performance of the superconducting quantum chip is ensured, and the packaging reliability of the superconducting quantum chip is improved. Meanwhile, moisture, oxygen, pollutants and the like can be effectively isolated, the problem that functional lines of the superconducting quantum chip are oxidized and deteriorated due to the fact that the functional lines make contact with the atmospheric environment in the storage process is solved, and therefore the problems that working parameters of the superconducting quantum chip change, performance is reduced and the service life is shortened are solved. And oxidation and chemical corrosion of a superconducting material of the superconducting quantum chip in a low-temperature environment can be prevented, and the long-term stability of the superconducting quantum chip in a dilution refrigerator is improved, so that the low-temperature performance of the superconducting quantum chip is improved.

Description

Technical Field

[0001] This application relates to the field of superconducting quantum technology, and more specifically, to a packaging structure and electronic device for a superconducting quantum chip. Background Technology

[0002] The core function of superconducting quantum chips relies on the superconducting properties of microstructures such as Josephson junctions. Their material systems (such as aluminum, niobium, and titanium nitrides) readily react with oxygen and water vapor in the environment at room temperature, generating insulating oxides (such as Al₂O₃ and NbO). x Especially during the packaging of superconducting quantum chips, it is unavoidable to expose the chips to the conventional environment, resulting in oxidation defects in the chip circuitry. This oxide layer formed by oxidation in the environment significantly increases the interface defect density, leading to a decrease in the reliability of the superconducting quantum chip. This can cause changes in operating parameters such as shortened coherence time of qubits and a decrease in the resonant cavity quality factor, and even irreversible damage such as quantum state leakage. Therefore, improving the problem of chip circuitry oxidation during the packaging process of superconducting quantum chips has become one of the main research directions for researchers today. Utility Model Content

[0003] In view of this, this application provides a packaging structure and electronic device for a superconducting quantum chip, which effectively solves the existing technical problems, improves the problem of oxidation of functional circuits in the functional circuit region during the packaging process of the superconducting quantum chip, and improves the reliability and low-temperature performance of the superconducting quantum chip packaging.

[0004] To achieve the above objectives, the technical solution provided in this application is as follows:

[0005] A packaging structure for a superconducting quantum chip, characterized in that it comprises:

[0006] A superconducting quantum chip, wherein one side surface of the superconducting quantum chip includes a functional circuit region and an edge sealing region surrounding the functional circuit region;

[0007] A control chip is disposed opposite to the superconducting quantum chip, and the first solder joint of the control chip is soldered to the solder joint of the functional circuit area;

[0008] A sealing ring is located between the superconducting quantum chip and the control chip, and the sealing ring is correspondingly disposed in the edge sealing area. A first sealing cavity is formed between the superconducting quantum chip, the sealing ring and the control chip, and the first solder joint is located in the first sealing cavity.

[0009] The encapsulation box includes a box body and a cover plate. The cover plate is welded to the opening of the box body to form a second sealed cavity. The superconducting quantum chip, the sealing ring, and the control chip are all located in the second sealed cavity. The second solder joint of the control chip is welded to the solder joint inside the box body. At least one of the first sealed cavity and the second sealed cavity is filled with an inert gas.

[0010] Optionally, the inert gas includes at least one of nitrogen, helium, and argon.

[0011] Optionally, the first solder joint is located on the surface of the control chip facing the superconducting quantum chip, and the second solder joint is located on the surface of the control chip away from the superconducting quantum chip.

[0012] Optionally, both the first solder joint and the second solder joint are located on the surface of the control chip facing the superconducting quantum chip, the second solder joint is located outside the first sealed cavity, and the second solder joint located on the same side surface of the control chip as the first solder joint is located outside the first sealed cavity.

[0013] Optionally, the first solder joint and a portion of the second solder joint are located on the surface of the control chip facing the superconducting quantum chip, while the remaining portion of the second solder joint is located on the surface of the control chip away from the superconducting quantum chip.

[0014] Optionally, when the second solder joint and the first solder joint are located on the surface of the control chip facing the superconducting quantum chip, the second solder joint is wire-welded to the solder joint inside the package.

[0015] Optionally, the solder used to weld the first solder joint to the solder joint of the functional circuit area includes In.

[0016] Optionally, the solder used to weld the second solder joint to the solder joint inside the package includes In.

[0017] Optionally, the sealing ring may be made of photoresist.

[0018] Based on the same inventive concept, this application also provides an electronic device, which includes the above-described packaging structure of the superconducting quantum chip.

[0019] Compared with existing technologies, the technical solution provided in this application has at least the following advantages:

[0020] This application provides a packaging structure and electronic device for a superconducting quantum chip. During the packaging process, a first sealed cavity is formed by the superconducting quantum chip, a sealing ring, and a control chip, while a second sealed cavity is formed by a housing and a cover plate. This dual-hermetic packaging method mitigates the oxidation problem of the superconducting quantum chip's functional circuitry during packaging, suppresses surface and material-related losses, ensures high performance, and improves the reliability of the packaging. Simultaneously, the dual-hermetic packaging structure effectively isolates the superconducting quantum chip from moisture, oxygen, and contaminants, preventing oxidation and deterioration of the functional circuitry due to contact with the atmospheric environment during storage. This avoids changes in operating parameters, performance degradation, and lifespan reduction. Furthermore, the dual-hermetic packaging structure prevents oxidation and chemical corrosion of the superconducting quantum chip's superconducting materials at low temperatures, improving the long-term stability of the superconducting quantum chip in dilution refrigerators and thus enhancing its low-temperature performance. Attached Figure Description

[0021] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of this application. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0022] Figure 1 A flowchart illustrating a packaging method for a superconducting quantum chip provided in this application embodiment;

[0023] Figure 2 A schematic diagram of the packaging structure of a superconducting quantum chip provided in an embodiment of this application;

[0024] Figure 3 A flowchart illustrating another packaging method for a superconducting quantum chip provided in this application embodiment;

[0025] Figures 4-8 for Figure 3 A schematic diagram of the corresponding structure of the middle part of the steps;

[0026] Figure 9 A schematic diagram of another packaging structure for a superconducting quantum chip provided in an embodiment of this application;

[0027] Figure 10 This is a schematic diagram of the packaging structure of another superconducting quantum chip provided in an embodiment of this application.

[0028] Figure label:

[0029] 100 - Superconducting quantum chip; 200 - Control chip; 210 - First solder joint; 220 - Second solder joint; 300 - Housing; 310 - External pin; 400 - Cover plate; 500 - Sealing ring; 610 - First sealing cavity; 620 - Second sealing cavity; A1 - Functional circuit area; A2 - Edge sealing area; BOE - Buffer oxide etching solution; UP - Ultrapure water. Detailed Implementation

[0030] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0031] As described in the background section, the core function of superconducting quantum chips relies on the superconducting properties of microstructures such as Josephson junctions. Their material systems (such as aluminum, niobium, and titanium nitrides) readily react with oxygen and water vapor in the environment at room temperature, generating insulating oxides (such as Al₂O₃ and NbO). x Especially during the packaging of superconducting quantum chips, it is unavoidable to expose the chips to the conventional environment, resulting in oxidation defects in the chip circuitry. This oxide layer formed by oxidation in the environment significantly increases the interface defect density, leading to a decrease in the reliability of the superconducting quantum chip. This can cause changes in operating parameters such as shortened coherence time of qubits and a decrease in the resonant cavity quality factor, and even irreversible damage such as quantum state leakage. Therefore, improving the problem of chip circuitry oxidation during the packaging process of superconducting quantum chips has become one of the main research directions for researchers today.

[0032] Based on this, the embodiments of this application provide a packaging method, packaging structure and electronic device for a superconducting quantum chip, which effectively solves the existing technical problems, improves the problem of oxidation of functional circuits in the functional circuit area of ​​the superconducting quantum chip during the packaging process, and improves the reliability and low temperature performance of the superconducting quantum chip packaging.

[0033] To achieve the above objectives, the technical solutions provided in this application are as follows, in specific combination with... Figures 1 to 10 The technical solutions provided in the embodiments of this application will be described in detail.

[0034] Combination Figure 1 and Figure 2 As shown, Figure 1 A flowchart illustrating a packaging method for a superconducting quantum chip provided in this application embodiment. Figure 2This is a schematic diagram of a packaging structure for a superconducting quantum chip provided in an embodiment of this application. The packaging method for the superconducting quantum chip includes:

[0035] S1. A superconducting quantum chip 100, a control chip 200, and a packaging box are provided, wherein the packaging box includes a box body 300 and a cover plate 400. One side surface of the superconducting quantum chip 100 includes a functional circuit region A1 and an edge sealing region A2 surrounding the functional circuit region A1; that is, the same surface of the superconducting quantum chip 100 (i.e., Figure 2 The surface of the superconducting quantum chip 100 facing the control chip 200 is divided into two regions. One region is the functional circuit region A1, which contains functional circuits (not shown). The other region is the edge sealing region A2, which forms a seal with the control chip 200. The edge sealing region A2 is a ring surrounding the functional circuit region A1. The edge sealing region A2 can be a regular or irregular ring, such as a circular ring or a square ring. This application does not impose any specific limitations on this. The functional circuit region A1 includes multiple solder joints (not shown). The control chip 200 includes multiple first solder joints 210 corresponding to the functional circuit region A1. The control chip 200 also has multiple second solder joints 220 corresponding to the solder joints (not shown) inside the housing 300 of the package. The housing 300 includes an opening that matches the cover plate 400. The exterior of the housing 300 also has multiple external pins 310. The external pins 310 are electrically connected to the solder joints inside the housing 300 through wiring in the housing 300. S2. A sealing ring 500 is formed on the edge sealing area A2.

[0036] S3. Perform deoxidation treatment on the functional circuit area A1.

[0037] S4. Within a first set time, the deoxidized superconducting quantum chip 100 is transferred to a welding device in an inert atmosphere. Under the protection of the inert atmosphere, the solder joints of the functional circuit area A1 are welded to the first solder joint 210 of the control chip 200, and the second solder joint 220 of the control chip 200 is welded to the solder joints inside the housing 300. A first sealing cavity 610 is formed between the superconducting quantum chip 100, the sealing ring 500, and the control chip 200, and the first solder joint 210 is located inside the first sealing cavity 610, while the second solder joint 220 is located outside the first sealing cavity 610.

[0038] S5. Within a second set time, the box 300, which has been welded and loaded with the superconducting quantum chip 100 and the control chip 200, is transferred to an inert atmosphere glove box. The cover plate 400 is aligned with the opening of the box 300 and welded to form a second sealed cavity 620, wherein the superconducting quantum chip 100, the sealing ring 500 and the control chip 200 are all located in the second sealed cavity 620.

[0039] Understandably, the technical solution provided in this application, during the packaging process of the superconducting quantum chip 100, forms a first sealed cavity 610 through the superconducting quantum chip 100, the sealing ring 500, and the control chip 200, and a second sealed cavity 620 through the housing 300 and the cover plate 400. This dual hermetic packaging method improves the oxidation problem of the functional circuitry of the superconducting quantum chip 100 during packaging, suppresses surface loss and material-related losses of the superconducting quantum chip 100, ensures high performance of the superconducting quantum chip 100, and improves the reliability of the superconducting quantum chip 100 packaging. Simultaneously, the packaging structure obtained by the dual hermetic packaging method can effectively isolate moisture, oxygen, and contaminants, preventing oxidation and deterioration of the functional circuitry of the superconducting quantum chip 100 due to contact with the atmospheric environment during storage. This avoids changes in the operating parameters, performance degradation, and lifespan reduction of the superconducting quantum chip 100. Furthermore, the packaging structure obtained by adopting a dual hermetic encapsulation method can prevent the oxidation and chemical corrosion of the superconducting material of the superconducting quantum chip 100 in a low-temperature environment, improve the long-term stability of the superconducting quantum chip 100 in the dilution refrigerator, and thus improve the low-temperature performance of the superconducting quantum chip.

[0040] refer to Figure 3 The diagram shows a flowchart of another packaging method for a superconducting quantum chip provided in this application embodiment. After deoxidizing the functional circuit region A1 in step S3, and before transferring the superconducting quantum chip 100 to the welding equipment in step S4, the method further includes: S31, performing an oxidation suppression treatment on the superconducting quantum chip 100. Then, within a first predetermined time period, the oxidation-suppressed superconducting quantum chip 100 is transferred to the welding equipment in an inert atmosphere environment. This prevents secondary oxidation of the functional circuit region A1 of the superconducting quantum chip 100, avoiding any impact on the performance of the superconducting quantum chip 100. Optionally, performing the oxidation suppression treatment on the superconducting quantum chip 100 may include immersing the superconducting quantum chip 100 in ultrapure water (UP).

[0041] The following is in conjunction with the appendix Figure 4 To be continued Figure 8 The encapsulation method provided in the embodiments of this application will be described in more detail. Figures 4 to 8 for Figure 3 A schematic diagram of the corresponding structure for some of the steps.

[0042] like Figure 4 As shown, corresponding to step S2, a sealing ring 500 is formed on the edge sealing area A2 of the superconducting quantum chip 100.

[0043] In some embodiments, step S2 of this application, forming a sealing ring 500 on the edge sealing region A2, includes: forming a sealing ring 500 made of photoresist on the edge sealing region A2, which improves the performance of the sealing ring 500 itself and further improves the reliability of the packaging structure of the superconducting quantum chip 100. Optionally, the sealant provided in this application embodiment can be a negative photoresist, such as SU-8, AZ5214, etc. Firstly, the sealing ring 500 formed by the photoresist can play a sealing role due to its dense cross-linked structure. After UV exposure, photoresist can form a three-dimensional cross-linked network structure (epoxy cross-linking). The sealing ring 500 formed after curing has extremely low porosity, effectively isolating moisture, oxygen, and contaminants. Therefore, the sealing ring 500 formed by photoresist ensures good airtightness of the first sealing cavity 610. This not only prevents the functional circuitry of the superconducting quantum chip 100 from being oxidized and deteriorated during the packaging process, but also prevents oxidation and deterioration of the functional circuitry due to contact with the atmospheric environment during the storage stage after packaging. This avoids problems such as changes in the operating parameters, performance degradation, and lifespan reduction of the superconducting quantum chip 100. At the same time, the good airtightness of the first sealing cavity 610 composed of the photoresist sealing ring 500 also prevents the oxidation and chemical corrosion of the superconducting material (such as niobium or aluminum) of the superconducting quantum chip 100 in low-temperature environments, improving the long-term stability of the superconducting quantum chip 100 in dilution refrigerators (mK level temperatures). Secondly, the sealing ring 500 formed by photoresist has low moisture absorption and high environmental adaptability. The photoresist has a low moisture absorption rate (less than 0.1%), allowing it to maintain stable mechanical and dielectric properties in humid environments and avoiding performance degradation caused by moisture penetration. Combined with the photoresist's thermal stability (heat resistance temperature greater than 200℃), the sealing ring 500 can withstand thermal cycling shocks, reducing the risk of interface cracking caused by thermal stress. Thirdly, the photoresist-formed sealing ring 500 is compatible with low-temperature processes. The photoresist has a low curing shrinkage rate (less than 5%), and by optimizing the baking process, stress accumulation can be further reduced. This mitigates the difference in thermal expansion coefficients between the photoresist-formed sealing ring 500 and the superconducting quantum chip 100 during the welding and bonding process, preventing seal failure due to temperature changes.

[0044] The process of forming a photoresist-based sealing ring 500 on the edge sealing area A2 as described in this embodiment includes:

[0045] Step S21: Spin-coat a photoresist layer on one side of the functional circuit region A1 of the superconducting quantum chip 100 and perform a first baking. Use a negative photoresist such as SU-8 or AZ5214. Spin-coat at 3000-5000 rpm for 60-180 seconds, then allow it to stand for 5-10 minutes to eliminate air bubbles, forming a photoresist layer on the functional circuit region A1. Then perform a first baking of the photoresist layer. This first baking can be a soft baking, specifically baking on a hot plate at 75-95℃ for 180-300 seconds.

[0046] Step S22: Expose the photoresist layer and perform a second baking. Use an LED (light-emitting diode) light source, align with a contact mask, or use a laser direct-write device to expose the photoresist layer. The exposure dose can be 200-500 mJ / cm². 2 The LED light source is ultraviolet light, such as with a wavelength of 365nm. Then, the photoresist layer is baked a second time. This second baking is a post-baking process and can be done in stages. Specifically, the second baking involves first baking with a hot plate at 65-95℃ for 60-180 seconds, and then baking with a hot plate at 95-115℃ for 300-600 seconds.

[0047] Step S23: Develop the photoresist layer using a developer to form a photoresist ring on the edge sealing region A2, and then perform a third baking. Immerse the superconducting quantum chip 100 with the prepared photoresist layer in the developer for 90-180 seconds, and alternately rinse with isopropanol until no residue remains to complete the development process. The developer can be MR-Dev600 developer. Then, perform a third baking on the obtained photoresist ring. The third baking is a hard baking, that is, baking at 180-250℃ for 900-1800 seconds. This three-baking method enhances the mechanical strength of the prepared photoresist ring (i.e., the sealing ring 500).

[0048] Step S24: Immerse the superconducting quantum chip 100 in an intermediate solvent to replace the residual developer on the superconducting quantum chip 100. After rinsing, the superconducting quantum chip 100 is immersed in the intermediate solvent for 10-15 minutes. The intermediate solvent can be ethanol or acetone, thereby replacing the residual developer. This replacement step can be performed once or repeated multiple times. That is, one replacement of the residual developer takes 10-15 minutes, and this replacement step can be repeated multiple times, such as three times, to ensure complete replacement of the residual developer.

[0049] Step S25: Perform a critical point drying process on the superconducting quantum chip 100 to form the sealing ring 500, thereby removing residual solution from the superconducting quantum chip 100. Specifically, transfer the superconducting quantum chip 100 to a high-pressure drying chamber and slowly inject liquid CO2 (purity not less than 99.99%), immersing the superconducting quantum chip 100 in the liquid CO2. The CO2 flow rate can be controlled at 0.5 L / min to avoid mechanical impact on the superconducting quantum chip 100 and structural damage. This step can be repeated multiple times. The immersion time of the superconducting quantum chip 100 in liquid CO2 can be controlled to 5 minutes each time. Then, the liquid CO2 is removed and re-injected according to the above steps. This step is repeated 5-8 times to ensure that the residual solution concentration is less than 0.1%.

[0050] like Figure 5 As shown, corresponding to step S3, the functional circuit region A1 undergoes deoxidation treatment. Specifically, the deoxidation treatment of the functional circuit region A1 provided in this application embodiment includes: immersing the superconducting quantum chip 100 in buffer oxide etchant (BOE) to remove the natural oxide layer of the functional circuit region A1. To improve the deoxidation effect on the functional circuit region A1, the superconducting quantum chip 100 can be vertically immersed in the buffer oxide etchant (BOE), and the buffer oxide etchant (BOE) can be stirred by nitrogen bubbling, thereby enhancing the reaction uniformity.

[0051] The formulation of the buffer oxide etching solution BOE provided in this application embodiment can be NH4F:HF (volume ratio) = 6:1 (or other ratios, such as 4:1, 5:1, 7:1, etc.). A soluble complex is formed by the reaction of fluoride ions (F-) with the natural oxide layer (such as Al2O3) on the aluminum / niobium surface, with the reaction formula Al2O3 + 6HF → 2AlF3 + 3H2O. Since the oxidation rate of the aluminum film under natural conditions is approximately 0.01-0.1 nm / day, the temperature of the buffer oxide etching solution BOE provided in this application embodiment can be 20-25℃, and the immersion time of the superconducting quantum chip 100 in the buffer oxide etching solution BOE can be 30-60 seconds. This can remove 3-5 nm of oxide layer, ensuring a high deoxidation effect on the functional circuit area A1.

[0052] like Figure 6As shown, corresponding to step S31, the superconducting quantum chip 100 undergoes oxidation suppression treatment. Specifically, the superconducting quantum chip 100 can be immersed in ultrapure water UP (resistivity not less than 18.2 MΩ·cm). The chemical stability of ultrapure water UP can prevent secondary oxidation of the functional circuit region A1 of the superconducting quantum chip 100, ensuring that the interface contact resistance is less than 1 mΩ, thus avoiding any impact on the performance of the superconducting quantum chip 100. Simultaneously, a combination of megasonic-assisted cleaning (1 MHz) and ozone water (5 ppm) cleaning is used to remove residual fluorides and particulate contamination, preventing crystallization or gas release (such as H2) at low temperatures (mK level). Finally, nitrogen drying is performed.

[0053] like Figure 7 As shown, corresponding to step S4, the superconducting quantum chip 100 after oxidation inhibition treatment is transferred to a welding device in an inert atmosphere environment within a first set time. Under the protection of the inert atmosphere environment, the solder joints at the functional circuit area A1 are welded to the first solder joint 210 of the control chip 200, and then the second solder joint 220 of the control chip 200 is welded to the solder joints inside the housing 300 of the packaging box. A first sealed cavity 610 is formed between the superconducting quantum chip 100, the sealing ring 500, and the control chip 200. Optionally, the inert gas provided in this application embodiment may include at least one of nitrogen, helium, and argon. It may be a single-element gas or a mixture of multiple elements. This application does not impose specific limitations on this.

[0054] It should be noted that the control chip 200 and the housing 300 provided in this application embodiment can be placed in the welding equipment before the superconducting quantum chip 100 is transferred to the welding equipment; or, the control chip 200 and the housing 300 can be transferred to the welding equipment simultaneously with the superconducting quantum chip 100; or, the superconducting quantum chip 100 is already in an inert atmosphere environment, therefore, the control chip 200 and the housing 300 can also be placed in the welding equipment after the superconducting quantum chip 100 is transferred to the welding equipment. This application does not impose specific limitations on these aspects.

[0055] In some embodiments, the first set time can be 1 minute. The welding equipment can be a flip-chip bonding machine, wherein the flip-chip bonding machine can be an FC150 flip-chip bonding machine. After placing the superconducting quantum chip 100, the control chip 200, and the package housing 300 into the flip-chip bonding machine, a spectroscopic prism microscope can first be used to insert between the chips. Then, relevant parameters are adjusted to align the solder joints at the functional circuit area A1 of the superconducting quantum chip 100 with the first solder joint 210 of the control chip 200, and to align the second solder joint 220 of the control chip 200 with the solder joints inside the package housing 300. Then, pressure is applied at room temperature (e.g., 20-50 N / mm). 2The solder joints at functional circuit area A1 are soldered to the first solder joint 210 of control chip 200, and the solder joints inside housing 300 are soldered to the second solder joint 220 of control chip 200. A first sealed cavity 610 is formed between superconducting quantum chip 100, sealing ring 500, and control chip 200, and the first sealed cavity 610 is filled with inert gas to inhibit oxidation of functional circuits during packaging preservation. The sealing ring 500 can serve as a mechanical stop structure, allowing the distance between superconducting quantum chip 100 and control chip 200 to be 10-20 micrometers. Finally, a vacuum oven is used for drying. The parameters of the vacuum oven can be 50℃ and 2×10⁻⁶. 4 The drying time can be approximately 12 hours to remove the solvent absorbed by the sealing ring 500. For example, the control chip 200 is eutectic bonded to the package body 300 via TSV (Through Silicon Via) technology and pre-evaporated indium pillars (second solder joint 220). Functional circuitry is formed on the side of the control chip 200 that is flip-chip bonded to the superconducting quantum chip 100 (i.e., the side of the control chip 200 where the first solder joint 210 is formed).

[0056] It should be noted that the solder joints of the functional circuit area A1 provided in this application embodiment can be soldered to the first solder joint 210 of the control chip 200, and the second solder joint 220 of the control chip 200 can be soldered to the solder joints inside the housing 300. These solder joints can be a soldering area used only to illustrate the soldering connection. When soldering the solder joints at the functional circuit area A1 and the first solder joint 210, the solder can be placed at the solder joints at the functional circuit area A1, or the solder can be placed at the first solder joint 210, or... Solder can be applied to both the solder joint in functional circuit area A1 and the first solder joint 210, and then the solder joint in functional circuit area A1 and the first solder joint 210 are aligned and soldered. Similarly, when soldering the second solder joint 220 and the solder joint inside the housing 300, solder can be applied to the second solder joint 220, or the solder joint inside the housing 300, or solder can be applied to both the second solder joint 220 and the solder joint inside the housing 300, and then the second solder joint 220 and the solder joint inside the housing 300 are aligned and soldered. Alternatively, the solder joint in functional circuit area A1, the first solder joint 210, the second solder joint 220, and the solder joint inside the housing 300 not only serve as a welding area to indicate the welding connection, but also actually contain solder. During the welding process, the solder joint in functional circuit area A1 and the first solder joint 210 can be directly soldered, and the second solder joint 220 and the solder joint inside the housing 300 can be directly soldered. Alternatively, some of the solder joints at functional circuit area A1, the first solder joint 210, the second solder joint 220, and the solder joints within the housing 300 may be soldering areas used only for illustrative purposes, while the remaining portions may be solder joints with actual solder. For example, if the solder joint at functional circuit area A1 is a soldering area used only for illustrative purposes, and the first solder joint 210 is a solder joint with actual solder, solder can be applied to the solder joint at functional circuit area A1 before soldering the solder joint at functional circuit area A1 to the first solder joint 210. Alternatively, solder can be applied to the solder joint at functional circuit area A1 without applying solder, and the solder of the first solder joint 210 can be used to achieve soldering with the solder joint at functional circuit area A1. This application does not impose specific limitations on this. Optionally, the solder used for bonding may be In (indium). In is soft and can reduce damage to the chip during soldering.

[0057] In the control chip 200, the first solder joint 210 is electrically connected to the solder joint in the functional circuit area A1 and is located inside the first sealed cavity 610, while the second solder joint 220 needs to be electrically connected to the solder joint inside the housing 300 and is located outside the first sealed cavity 610. In this embodiment, the location of the second solder joint 220 is not specifically limited. Optionally, the first solder joint 210 and the second solder joint 220 provided in this embodiment can be located on opposite surfaces of the control chip 200, wherein the first solder joint 210 is located on the surface of the control chip 200 facing the superconducting quantum chip 100, and the second solder joint 220 is located on the surface of the control chip 200 away from the superconducting quantum chip 100. Alternatively, the first solder joint 210 and the second solder joint 220 provided in this embodiment may be located on the same surface of the control chip 200, that is, both the first solder joint 210 and the second solder joint 220 are located on the surface of the control chip 200 facing the superconducting quantum chip 100, wherein the second solder joint 220 is located outside the first sealing cavity 610. Alternatively, the first solder joint 210 and a portion of the second solder joint 220 provided in this embodiment may be located on the surface of the control chip 200 facing the superconducting quantum chip 100, and the remaining portion of the second solder joint 220 may be located on the surface of the control chip 200 away from the superconducting quantum chip 100, and the second solder joint 220 located on the same surface as the first solder joint 210 on the control chip 200 is located outside the first sealing cavity 610.

[0058] like Figure 8 As shown, corresponding to step S5, within a second set time (which can be 1 minute), the box 300, which has been welded and loaded with the superconducting quantum chip 100 and the control chip 200, is transferred to an inert atmosphere glove box. The cover plate 400 is then aligned with the opening of the box 300 and welded to form a second sealed cavity 620. Optionally, some preparatory work needs to be done before placing the box 300 and the cover plate 400 into the inert atmosphere glove box. For example, the matching size of the opening of the cover plate 400 and the box 300 is tested. When the opening of the box 300 is rectangular, the length and width of the rectangular cover plate 400 should be 0.05-0.1 mm smaller than the length and width of the opening of the box 300; when the opening of the box 300 is circular, the diameter of the circular cover plate 400 should be 0.05-0.1 mm smaller than the diameter of the opening of the box 300. Additionally, the cover plate 400 needs to be cleaned of surface oil and oxide layers, and then baked to dehumidify. The cleaned cover plate 400 can be placed in an oven and vacuumed to a specified value (e.g., not exceeding 1×10⁻⁶). -3The gas is heated to a set temperature (e.g., not exceeding 150℃) and held for a certain period of time. Additionally, the environment within the inert atmosphere glove box needs to be adjusted. The glove box can be filled with positive-pressure nitrogen or a nitrogen-helium mixture (moisture not exceeding 40ppm), and the environment within the inert atmosphere glove box should be set to a ≥8 level cleanroom. A level 8 cleanroom is equivalent to a 100,000-class cleanroom, meaning ≥0.5-micron ions are 352-3520 particles / L, and ≥5-micron ions are 3-29 particles / L.

[0059] After preparation, the cover plate 400 and the box body 300 are transferred to an inert atmosphere glove box to align the cover plate 400 with the opening of the box body 300 and weld it to form a second sealed cavity 620. The cover plate 400 can be placed in the inert atmosphere glove box before the box body 300 is transferred; or, the cover plate 400 can be transferred to the inert atmosphere glove box simultaneously with the box body 300; or, the cover plate 400 can be placed in the inert atmosphere glove box after the box body 300 is transferred. This application does not impose specific limitations on this. The method of welding the cover plate 400 with the opening of the box body 300 to form the second sealed cavity 620, as provided in this embodiment, includes, for example but not limited to, using a parallel seam welding process, welding the cover plate 400 with the opening of the box body 300 to form the second sealed cavity 620, which is filled with inert gas. The second sealed cavity 620 formed by the parallel seam welding process has high airtightness, with an inert gas leakage rate of less than 1×10⁻⁶. -9 mbar·L / s avoids interface delamination problems caused by low-temperature frosting and moisture penetration. One method is parallel seam welding, a type of resistance welding. During seam welding, electrodes apply a certain pressure to the components being welded while intermittently applying electricity. The contact between the electrodes and the Joule heat generated by the resistance melt and bond the housing 300 and the cover plate 400, achieving an airtight weld. This ensures that the formed second sealed cavity 620 is isolated from the external environment and also prevents moisture erosion. This seam welding process is the same as existing technologies, so this application will not elaborate further.

[0060] Based on the same inventive concept, this application also provides a packaging structure for a superconducting quantum chip, which can be fabricated using the packaging method provided in any of the above embodiments. Continuing... Figure 2As shown, the packaging structure of the superconducting quantum chip provided in this application embodiment includes: a superconducting quantum chip 100, one side surface of the superconducting quantum chip 100 including a functional circuit region A1 and an edge sealing region A2 surrounding the functional circuit region A1, the functional circuit region A1 being disposed on the functional circuit and including a plurality of solder joints; and a control chip 200, the control chip 200 being disposed opposite to the superconducting quantum chip 100, the side surface of the control chip 200 facing the superconducting quantum chip 100 being provided with a plurality of first solder joints 210, the first solder joints 210 of the control chip 200 being soldered to the solder joints of the functional circuit region A1. A sealing ring 500 is located between the superconducting quantum chip 100 and the control chip 200, and is correspondingly disposed in the edge sealing area A2. A first sealing cavity 610 is formed between the superconducting quantum chip 100, the sealing ring 500, and the control chip 200, and the first solder joint 210 is located within the first sealing cavity 610. A packaging box includes a box body 300 and a cover plate 400. The cover plate 400 is welded to the opening of the box body 300 to form a second sealing cavity 620. The superconducting quantum chip 100, the sealing ring 500, and the control chip 200 are all located within the second sealing cavity 620. The control chip 200 includes a plurality of second solder joints 220 located outside the first sealing cavity 610, and the second solder joints 220 of the control chip 200 are welded to solder joints inside the box body 300. The outer surface of the housing 300 is also provided with a plurality of external pins 310, which are electrically connected to solder joints inside the housing 300 through wiring in the housing 300. Optionally, the first sealing cavity 610 provided in this application embodiment is filled with inert gas; and / or, the second sealing cavity 620 is filled with inert gas; that is, at least one of the first sealing cavity and the second sealing cavity is filled with inert gas.

[0061] Optionally, the inert gas provided in this application embodiment may include at least one of nitrogen, helium, and argon. It can be a single-element gas or a mixture of multiple elements, and this application does not impose specific limitations on it. Furthermore, the material of the sealing ring 500 provided in this application embodiment includes photoresist, and this application does not impose limitations on it. It can also be other materials with good density, which need to be specifically selected according to the actual application. In addition, the solder used for welding the first solder joint 210 to the solder joint of the functional circuit area A1 provided in this application embodiment includes In; and / or, the solder used for welding the second solder joint 220 to the solder joint within the housing 300 includes In (indium). In material is soft and can reduce damage to the chip during soldering. In some other embodiments, the solder used for soldering may also be other materials, and this application does not impose specific limitations on it.

[0062] In some embodiments, the first solder joint 210 of the control chip 200 provided in this application is electrically connected to the solder joint of the functional circuit area A1 and is located inside the first sealed cavity 610, while the second solder joint 220 needs to be electrically connected to the solder joint inside the housing 300 and is located outside the first sealed cavity 610. This application does not impose specific restrictions on the location of the second solder joint 220. Continuing as... Figure 2 As shown, the first solder joint 210 and the second solder joint 220 provided in this embodiment can be located on two opposite surfaces of the control chip 200, that is, the first solder joint 210 is located on the surface of the control chip 200 facing the superconducting quantum chip 100, and the second solder joint 220 is located on the surface of the control chip 200 away from the superconducting quantum chip 100. Or as... Figure 9 The schematic diagram of the packaging structure of the superconducting quantum chip shown in this application embodiment indicates that the first solder joint 210 and the second solder joint 220 can be located on the same surface of the control chip 200, that is, both the first solder joint 210 and the second solder joint 220 are located on the surface of the control chip 200 facing the superconducting quantum chip 100. The second solder joint 220 is located outside the first sealed cavity 610, and in this case, the second solder joint 220 can be soldered to the solder joint inside the housing 300 by wire bonding. Alternatively, as... Figure 10 The schematic diagram of the packaging structure of the superconducting quantum chip shown in this application embodiment indicates that the first solder joint 210 and part of the second solder joint 220 are both located on the surface of the control chip 200 facing the superconducting quantum chip 100. Furthermore, the second solder joint 220 located on the same surface of the control chip 200 as the first solder joint 210 is located outside the first sealing cavity 610, and this part of the second solder joint 220 can be soldered to the solder joint inside the housing 300 by wire bonding. The remaining part of the second solder joint 220 is located on the surface of the control chip 200 away from the superconducting quantum chip 100, and this remaining part of the second solder joint 220 can be electrically connected to the solder joint inside the housing 300 by solid-state welding (such as eutectic welding). Based on the welding method of the second solder point 220 of the control chip 200 and the solder point inside the housing 300, the packaging structure provided in this application embodiment includes, but is not limited to, BGA (Ball Grid Array), LCC (Leadless Chip Carrier), QFP (Quad Flat Package), DIP (Dual In-line Package), PGA (Pin Grid Array Package), and other packaging methods.

[0063] Based on the same inventive concept, this application also provides an electronic device, which includes the packaging structure of the superconducting quantum chip of any of the above embodiments. Optionally, the electronic device can be a quantum computer, etc., and this application does not impose specific limitations on it.

[0064] In summary, this application provides a packaging method, packaging structure, and electronic device for a superconducting quantum chip. During the packaging process, a first sealed cavity is formed by the superconducting quantum chip, a sealing ring, and a control chip, while a second sealed cavity is formed by the packaging box and a cover plate. This dual-hermetic packaging method mitigates the oxidation problem of the functional circuitry of the superconducting quantum chip during packaging, suppresses surface and material-related losses, ensures high performance, and improves the reliability of the superconducting quantum chip packaging. Simultaneously, the packaging structure obtained through this dual-hermetic packaging method effectively isolates moisture, oxygen, and contaminants, preventing oxidation and deterioration of the functional circuitry due to contact with the atmospheric environment during storage. This avoids changes in the operating parameters, performance degradation, and lifespan reduction of the superconducting quantum chip. Furthermore, the dual-hermetic packaging structure prevents oxidation and chemical corrosion of the superconducting quantum chip's superconducting material at low temperatures, improving the long-term stability of the superconducting quantum chip in dilution refrigerators, thereby enhancing its low-temperature performance.

[0065] In the description of the embodiments of this application, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", "axial", "radial", "circumferential" and other terms indicating the orientation or positional relationship are based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the embodiments of this application and simplifying the description, and are not intended to indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application.

[0066] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of embodiments of this application, "multiple" means at least two, such as two, three, etc., unless otherwise explicitly specified.

[0067] In the embodiments of this application, unless otherwise explicitly specified and limited, terms such as "installation," "connection," "linking," and "fixing" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection, an electrical connection, or a connection that allows communication between them; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components, unless otherwise explicitly limited. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.

[0068] In the embodiments of this application, unless otherwise expressly specified and limited, "above" or "below" the second feature can mean that the first feature is in direct contact with the second feature, or that the first feature is in indirect contact with the second feature through an intermediate medium. Furthermore, "above," "on top of," and "over" the second feature can mean that the first feature is directly above or diagonally above the second feature, or simply that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature can mean that the first feature is directly below or diagonally below the second feature, or simply that the first feature is at a lower horizontal level than the second feature.

[0069] In the embodiments of this application, the terms "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., refer to specific features, structures, materials, or characteristics described in connection with that embodiment or example, which are included in at least one embodiment or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Furthermore, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0070] Although embodiments of this application have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting this application. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of this application.

Claims

1. A packaging structure for a superconducting quantum chip, characterized in that, include: A superconducting quantum chip, wherein one side surface of the superconducting quantum chip includes a functional circuit region and an edge sealing region surrounding the functional circuit region; A control chip is disposed opposite to the superconducting quantum chip, and the first solder joint of the control chip is soldered to the solder joint of the functional circuit area; A sealing ring is located between the superconducting quantum chip and the control chip, and the sealing ring is correspondingly disposed in the edge sealing area. A first sealing cavity is formed between the superconducting quantum chip, the sealing ring and the control chip, and the first solder joint is located in the first sealing cavity. The encapsulation box includes a box body and a cover plate. The cover plate is welded to the opening of the box body to form a second sealed cavity. The superconducting quantum chip, the sealing ring, and the control chip are all located in the second sealed cavity. The second solder joint of the control chip is welded to the solder joint inside the box body. At least one of the first sealed cavity and the second sealed cavity is filled with an inert gas.

2. The packaging structure of the superconducting quantum chip according to claim 1, characterized in that, The inert gas includes at least one of nitrogen, helium, and argon.

3. The packaging structure of the superconducting quantum chip according to claim 1, characterized in that, The first solder joint is located on the surface of the control chip facing the superconducting quantum chip, and the second solder joint is located on the surface of the control chip away from the superconducting quantum chip.

4. The packaging structure of the superconducting quantum chip according to claim 1, characterized in that, Both the first solder joint and the second solder joint are located on the surface of the control chip facing the superconducting quantum chip, and the second solder joint is located outside the first sealed cavity.

5. The packaging structure of the superconducting quantum chip according to claim 1, characterized in that, The first solder joint and part of the second solder joint are located on the surface of the control chip facing the superconducting quantum chip, and the remaining part of the second solder joint is located on the surface of the control chip away from the superconducting quantum chip. Furthermore, the second solder joint located on the same side of the control chip as the first solder joint is located outside the first sealed cavity.

6. The packaging structure of the superconducting quantum chip according to claim 4 or 5, characterized in that, When the second solder joint and the first solder joint are located on the surface of the control chip facing the superconducting quantum chip, the second solder joint is wire-welded to the solder joint inside the package.

7. The packaging structure of the superconducting quantum chip according to claim 1, characterized in that, The solder used to weld the first solder joint to the solder joint of the functional circuit area includes In.

8. The packaging structure of the superconducting quantum chip according to claim 1, characterized in that, The solder used to weld the second solder joint to the solder joint inside the package includes In.

9. The packaging structure of the superconducting quantum chip according to claim 1, characterized in that, The sealing ring is made of photoresist.

10. An electronic device, characterized in that, The electronic device includes the packaging structure of the superconducting quantum chip according to any one of claims 1-9.

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