Packaging structure for chip

Abstract

The utility model discloses a packaging structure for a chip, which comprises an electric connection limiting frame, an electric connection clamping groove is arranged in the electric connection limiting frame, the electric connection clamping groove is arranged in four inner walls, the outer part of the electric connection clamping groove is communicated with a plurality of electric connection jacks, and the plurality of electric connection jacks are respectively arranged in four side walls of the electric connection limiting frame. Through the combination of the electric connection limiting frame and the lamination limiting frame, the modular packaging of the integrated chip is realized, the design facilitates the installation, replacement and expansion of the integrated chip, the flexibility and maintainability of the packaging are improved, the multi-layer lamination of the integrated chip can be realized through the increase and decrease of the lamination limiting frame, and the packaging efficiency is improved. The structural design is suitable for application scenes needing high integration, the packaging density and the space utilization rate are effectively improved, the connecting lines are etched in the connecting pole pieces, customized design can be carried out according to the connecting requirements of different types of integrated chips, and the compatibility and adaptability of the packaging structure to different chips are improved through the design.

Description

Technical Field

[0001] This utility model belongs to the technical field of chip packaging, specifically relating to a chip packaging structure. Background Technology

[0002] With the rapid development of semiconductor technology, the integration level and performance of integrated circuits (ICs) are constantly improving, placing higher demands on chip packaging technology. Traditional chip packaging methods often struggle to meet the miniaturization, high performance, and high reliability requirements of modern electronic devices. Therefore, developing a new chip packaging structure to adapt to the diverse needs of integrated chips and improve packaging flexibility, reliability, and efficiency has become an urgent need for the industry.

[0003] As integrated circuits become increasingly complex, their connection requirements to external circuits are becoming more diverse and sophisticated. Traditional packaging methods typically use a single packaging frame, which is difficult to adapt to integrated circuits of different sizes and shapes. This also limits chip stacking and multi-level integration, affecting package space utilization and electrical performance. Furthermore, integrated circuits are susceptible to external environmental influences during operation, such as temperature changes, humidity, and dust, all of which can damage the chip's stability and lifespan.

[0004] To address these issues, this patent proposes a novel chip packaging structure. Through innovative design and technical means, it solves the problems of existing packaging technologies in terms of adaptability, reliability, and space utilization. It provides an efficient, flexible, and reliable new solution for integrated chip packaging, which has significant industrial application value and market prospects. Utility Model Content

[0005] The purpose of this invention is to provide a chip packaging structure to solve the problem mentioned in the background art that traditional packaging methods usually use a single packaging frame, which is difficult to adapt to integrated chips of different sizes and shapes.

[0006] To achieve the above objectives, this utility model provides the following technical solution: a chip packaging structure, including an electrical connection limiting frame, wherein an electrical connection slot is provided inside the electrical connection limiting frame and is opened inside four inner walls, and multiple electrical connection holes are connected to the outside of the electrical connection slot, and the multiple electrical connection holes are respectively opened inside the four side walls of the electrical connection limiting frame, and multiple connecting pins are connected to the four side walls of the electrical connection limiting frame through the multiple electrical connection holes, and the multiple connecting pins are respectively inserted into the multiple electrical connection holes, and overlapping limiting frames are snapped into the upper and lower ends of the electrical connection limiting frame.

[0007] Preferably, the electrical connection limiting frame and the overlapping limiting frame are made of insulating material, the four side walls of the electrical connection limiting frame are flush with the four side walls of the overlapping limiting frame, and the four inner walls of the electrical connection limiting frame are flush with the four inner walls of the overlapping limiting frame.

[0008] Preferably, both the electrical connection limiting frame and the stacking limiting frame are provided with connecting electrodes, and connecting lines are etched inside the connecting electrodes. The connecting lines inside the connecting electrodes located inside the electrical connection limiting frame are connected to multiple connecting pins.

[0009] Preferably, the electrical connection limiting frame is engaged with the connecting electrode through the electrical connection slot, and the lower end of the stacking limiting frame has an electrical board slot, and the connecting electrode is engaged inside the electrical board slot of the stacking limiting frame.

[0010] Preferably, integrated chips are attached to both the upper and lower ends of the connecting electrode, and multiple integrated chips are respectively snapped into the upper and lower ends of the electrical connection limiting frame and the end of the stacked limiting frame away from the connecting foot.

[0011] Preferably, the outer walls of the plurality of integrated chips are respectively flush with the outer walls of the upper and lower ends of the electrical connection limiting frame and the outer wall of the stacked limiting frame away from the electrical connection limiting frame, and the plurality of integrated chips are respectively connected to two connecting electrodes at the upper and lower ends through a plurality of connecting posts.

[0012] Preferably, the plurality of connecting posts pass through the outer interior of the upper and lower ends of the plurality of connecting electrodes and the inner interior of the outer walls of the upper and lower ends of the plurality of integrated chips, and the plurality of connecting posts inside the end of the connecting electrodes and the integrated chips that are in contact with each other correspond one-to-one and are connected to each other.

[0013] Preferably, the inner outer sides of the upper and lower ends of the electrical connection limiting frame and the inner outer side of the stacked limiting frame away from the electrical connection limiting frame are provided with limiting slots, and the stacked limiting frame can be engaged with the electrical connection limiting frame through the circuit board slot and the limiting slot.

[0014] Compared with the prior art, the present invention provides a chip packaging structure with the following advantages:

[0015] 1. Modular packaging design: By combining electrical connection limiting frames and stacked limiting frames, modular packaging of integrated chips is achieved. This design facilitates the installation, replacement and expansion of integrated chips, and improves the flexibility and maintainability of packaging.

[0016] 2. Multi-layer integrated chip stacking: By adding or removing stacking limit frames, multi-layer integrated chips can be stacked. This structural design is suitable for application scenarios that require high integration and effectively improves packaging density and space utilization.

[0017] 3. Customized Connector Electrodes: The connector electrodes have internally etched connecting lines, allowing for customized design based on the connection requirements of different types of integrated chips. This design improves the compatibility and adaptability of the packaging structure to different chips.

[0018] 4. Precise alignment mechanism: The use of the limit slot and the circuit board slot together ensures the precise alignment between the electrical connection limit frame and the stacking limit frame. This mechanism guarantees the accurate connection between the integrated chip and the connecting electrode, improving the accuracy and reliability of the packaging.

[0019] 5. Secure connection between integrated chip and connecting electrode: The integrated chip and connecting electrode are securely connected in a one-to-one correspondence through connecting posts. This design not only simplifies the connection process, but also improves the accuracy and stability of the connection.

[0020] 6. Application of insulating materials: The electrical connection limit frame and the stacked limit frame are made of insulating materials, which effectively isolate the integrated chip from the external environment, provide good electrical isolation and mechanical protection, and enhance the safety and durability of the package.

[0021] 7. Optimization of external connection interface: The connection pins retained after packaging serve as access points for external circuits. This design simplifies the connection process with external circuits and improves the versatility and ease of use of the packaged product. Attached Figure Description

[0022] Figure 1 This is a three-dimensional structural diagram of the chip packaging structure of this utility model.

[0023] Figure 2 This is an exploded view of the chip packaging structure of this utility model.

[0024] Figure 3 This is a schematic diagram of the electrical connection limiting frame connection structure of this utility model.

[0025] Figure 4 For the present utility model Figure 3 Enlarged diagram of point A in the middle.

[0026] Figure 5 This is a schematic diagram of the connection structure of the stacked limiting frame of this utility model.

[0027] Figure 6 For the present utility model Figure 5 Enlarged diagram of point B in the middle.

[0028] In the diagram: 1. Electrical connection limiting frame; 2. Electrical connection slot; 3. Electrical connection socket; 4. Connecting pin; 5. Overlapping limiting frame; 6. Connecting electrode; 7. Integrated chip; 8. Connecting post; 9. Limiting slot. Detailed Implementation

[0029] The technical solutions of the present utility model will be clearly and completely described below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are only some embodiments of the present utility model, and not all embodiments. Based on the embodiments of the present utility model, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of the present utility model.

[0030] This utility model provides, for example Figures 1-6 The chip packaging structure shown includes an electrical connection limiting frame 1. An electrical connection slot 2 is provided inside the electrical connection limiting frame 1, and the electrical connection slot 2 is formed inside four inner walls. Multiple electrical connection holes 3 are connected to the outside of the electrical connection slot 2, and the multiple electrical connection holes 3 are respectively formed inside the four side walls of the electrical connection limiting frame 1. Multiple connecting pins 4 are connected to the four side walls of the electrical connection limiting frame 1 through the multiple electrical connection holes 3, and the multiple connecting pins 4 are respectively inserted into the multiple electrical connection holes 3. Stacked limiting frames 5 are clamped at both the top and bottom of the electrical connection limiting frame 1. Connecting electrodes 6 are provided inside both the electrical connection limiting frame 1 and the stacked limiting frames 5. Integrated chips 7 are attached to the top and bottom of the connecting electrodes 6. Since the integrated chip 7 is relatively fragile and needs to be connected to external circuits, it needs to be packaged to achieve the desired connection between the chip and the external circuitry. The system provides connection, support, and protection between multiple integrated chips 7. Integrated chips 7 are supported by electrical connection limiting frames 1 and stacking limiting frames 5, and multiple integrated chips 7 are connected through multiple connecting electrodes 6. Finally, the connecting electrodes 6, which are snapped into the electrical connection limiting frames 1, are connected to multiple connecting pins 4, which are snapped into the side wall, and are connected to external circuits through the multiple connecting pins 4. The connecting electrodes 6 are snapped into the electrical connection limiting frames 1 through electrical connection slots 2, and the multiple connecting pins 4 are connected to the connecting electrodes 6 through multiple electrical connection sockets 3, which communicate with the electrical connection slots 2. This allows multiple integrated chips 7 to be stacked vertically through the electrical connection limiting frames 1 and stacking limiting frames 5, and to be connected through the multiple connecting electrodes 6. Furthermore, the number of stacked layers of multiple integrated chips 7 can be increased or decreased by adding or removing stacking limiting frames 5.

[0031] Preferably, the electrical connection limiting frame 1 and the stacking limiting frame 5 are made of insulating material. The four side walls of the electrical connection limiting frame 1 are flush with the four side walls of the stacking limiting frame 5, and the four inner walls of the electrical connection limiting frame 1 are flush with the four inner walls of the stacking limiting frame 5. This allows the electrical connection limiting frame 1 and the stacking limiting frame 5 to support multiple integrated chips 7 while also isolating them internally to prevent external interference and thus protect the multiple integrated chips 7.

[0032] Preferably, each of the multiple connecting electrodes 6 has a connecting line etched inside, so that multiple connecting pins 4 are connected to the multiple connecting electrodes 6 through the connecting line, and are connected to multiple integrated chips 7 through the multiple connecting electrodes 6. Moreover, the connecting electrodes 6 can adapt to the connection between different types of integrated chips 7 by changing the internally etched connecting lines.

[0033] Preferably, the lower end of the stacking limiting frame 5 has an electrical board slot, and the connecting electrode 6 is snapped into the electrical board slot of the stacking limiting frame 5, so that the connecting electrode 6 located inside the stacking limiting frame 5 can be supported and protected by the stacking limiting frame 5, and can be limited by the electrical board slot of the stacking limiting frame 5, so that the connecting electrode 6 can be accurately attached and connected to the integrated chip 7.

[0034] Preferably, multiple integrated chips 7 are respectively snapped into the inner ends of the upper and lower ends of the electrical connection limiting frame 1 and the inner end of the stacked limiting frame 5 away from the connecting pin 4. The outer walls of the multiple integrated chips 7 are respectively flush with the outer walls of the upper and lower ends of the electrical connection limiting frame 1 and the outer wall of the stacked limiting frame 5 away from the electrical connection limiting frame 1. This ensures that the outer walls of the upper and lower ends of the electrical connection limiting frame 1 and the stacked limiting frame 5 do not obstruct the bonding connection between the integrated chips 7 and the connecting electrode 6, so that the multiple integrated chips 7 can be tightly bonded to the connecting electrode 6, ensuring a stable connection between the multiple integrated chips 7.

[0035] Preferably, multiple integrated chips 7 are connected to two connecting electrodes 6 at the top and bottom ends respectively through multiple connecting posts 8. The multiple connecting posts 8 pass through the outer interior of the upper and lower ends of the multiple connecting electrodes 6 and the inner interior of the outer walls of the upper and lower ends of the multiple integrated chips 7. Since the multiple connecting posts 8 inside the connecting surfaces between the mutually attached connecting electrodes 6 and integrated chips 7 correspond one-to-one, the connecting electrodes 6 and integrated chips 7 can be connected through the one-to-one corresponding multiple connecting posts 8, which can not only make the connection between the connecting electrodes 6 and integrated chips 7 more convenient, but also make the connection between the connecting electrodes 6 and integrated chips 7 more precise.

[0036] Preferably, limit slots 9 are provided on the inner outer sides of the upper and lower ends of the electrical connection limit frame 1 and on the inner outer side of the stacked limit frame 5 away from the electrical connection limit frame 1. The stacked limit frame 5 can be engaged with the electrical connection limit frame 1 through the circuit board slot and the limit slot 9, so that the electrical connection limit frame 1 and the stacked limit frame 5, and the stacked limit frame 5 and the stacked limit frame 5 can be engaged with each other through the circuit board slot and the limit slot 9. This restricts the position between the electrical connection limit frame 1 and the multiple stacked limit frames 5, so that the connecting electrode 6 and the integrated chip 7 inside the multiple stacked limit frames 5 can be accurately connected, ensuring the stable connection between the multiple integrated chips 7. After the multiple integrated chips 7 are connected, the entire connection is encapsulated, and multiple connecting pins 4 are exposed during encapsulation, so that the encapsulated chip can be connected to the external circuit through the multiple connecting pins 4.

[0037] Finally, it should be noted that the above description is only a preferred embodiment of the present utility model and is not intended to limit the present utility model. Although the present utility model has been described in detail with reference to the foregoing embodiments, those skilled in the art can still modify the technical solutions described in the foregoing embodiments or make equivalent substitutions for some of the technical features. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present utility model should be included within the protection scope of the present utility model.

Claims

1. A chip packaging structure, characterized in that, The device includes an electrical connection limiting frame (1), which has an electrical connection slot (2) inside. The electrical connection slot (2) is located inside the four inner walls. The electrical connection slot (2) is connected to multiple electrical connection holes (3) outside. The multiple electrical connection holes (3) are located inside the four side walls of the electrical connection limiting frame (1). The four side walls of the electrical connection limiting frame (1) are connected to multiple connecting feet (4) through the multiple electrical connection holes (3). The multiple connecting feet (4) are inserted into the multiple electrical connection holes (3). The upper and lower ends of the electrical connection limiting frame (1) are clamped with overlapping limiting frames (5).

2. The chip packaging structure according to claim 1, characterized in that: The electrical connection limiting frame (1) and the superimposed limiting frame (5) are made of insulating material. The four side walls of the electrical connection limiting frame (1) are flush with the four side walls of the superimposed limiting frame (5), and the four inner walls of the electrical connection limiting frame (1) are flush with the four inner walls of the superimposed limiting frame (5).

3. The chip packaging structure according to claim 2, characterized in that: Both the electrical connection limiting frame (1) and the stacking limiting frame (5) are provided with connecting electrode plates (6), and connecting lines are etched inside the connecting electrode plates (6). The connecting lines inside the connecting electrode plates (6) located inside the electrical connection limiting frame (1) are connected to multiple connecting pins (4).

4. A chip packaging structure according to claim 3, characterized in that: The electrical connection limiting frame (1) is connected to the connecting electrode (6) through the electrical connection slot (2). The lower end of the stacking limiting frame (5) has an electrical board slot, and the connecting electrode (6) is connected inside the electrical board slot of the stacking limiting frame (5).

5. A chip packaging structure according to claim 4, characterized in that: The connecting electrode (6) has integrated chips (7) attached to both the upper and lower ends, and multiple integrated chips (7) are respectively snapped into the upper and lower ends of the electrical connection limiting frame (1) and the end of the stacking limiting frame (5) away from the connecting foot (4).

6. A chip packaging structure according to claim 5, characterized in that: The outer walls of the multiple integrated chips (7) are flush with the outer walls of the upper and lower ends of the electrical connection limiting frame (1) and the outer wall of the stacked limiting frame (5) away from the electrical connection limiting frame (1). The multiple integrated chips (7) are connected to the two connecting electrodes (6) at the upper and lower ends through multiple connecting posts (8).

7. A chip packaging structure according to claim 6, characterized in that: Multiple connecting posts (8) pass through the outer interior of the upper and lower ends of multiple connecting electrodes (6) and the inner interior of the outer walls of the upper and lower ends of multiple integrated chips (7), and the multiple connecting posts (8) inside the contact end of the connecting electrodes (6) and integrated chips (7) correspond one to one and are connected to each other.

8. A chip packaging structure according to claim 4, characterized in that: Limiting slots (9) are provided on the inner outer sides of the upper and lower ends of the electrical connection limiting frame (1) and on the inner outer side of the stacked limiting frame (5) away from the electrical connection limiting frame (1). The stacked limiting frame (5) can be engaged with the electrical connection limiting frame (1) through the electrical board slot and the limiting slot (9).

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