Long-distance IC bus signal enhancement circuit capable of intelligently inhibiting signal reflection

Abstract

The utility model relates to the technical field of I2C communication, in particular to a long-distance I2C bus signal enhancement circuit capable of intelligently inhibiting signal reflection. The circuit comprises a micro-control unit, an I2C bus and a slave, the slave is connected with the I2C bus through a common mode choke, the I2C bus is connected with the micro-control unit sequentially through a resistance matching network and a repeater, and a data line of the I2C bus is further connected with the micro-control unit through a differential voltage feedback circuit and used for dynamically monitoring data signals of the I2C bus. And the driving end of the resistance matching network is connected with the micro-control unit. According to the utility model, common-mode interference is suppressed through the common-mode choke, and parasitic capacitance and parasitic inductance are isolated through the repeater, so that the edge slope of a signal is optimized; through the resistance matching network and the differential voltage feedback circuit, the circuit resistance value is adjusted in real time, the signal reflection and offset phenomena are inhibited, and the signal quality is effectively improved.

Description

Technical Field

[0001] This utility model relates to I 2 In the field of communication technology, this invention relates in particular to a long-distance I / O method that intelligently suppresses signal reflection. 2 C-bus signal enhancement circuit. Background Technology

[0002] In industrial IoT sensor networking scenarios, long-range I / O 2 C-type transmission faces signal integrity degradation issues. A wire harness exceeding 1 meter introduces parasitic capacitance exceeding 150pF and characteristic impedance exceeding 80Ω, leading to I... 2 The C signal rise time exceeds 200ns, and the edge slope is less than 0.5V / μs, violating bus specifications. Simultaneously, there is increased noise coupling; mechanical vibration and the electromagnetic environment introduce 50kHz–1MHz common-mode noise with a peak-to-peak value of 200mV, leading to a decrease in signal-to-noise ratio and an increase in data error rate. Existing technologies use fixed resistor switching matching, which cannot dynamically adapt to harness impedance fluctuations and lacks integrated signal shaping and high-frequency filtering design, making it difficult to meet long-distance I / O requirements. 2 C-transmission reliability requirements. Summary of the Invention

[0003] To solve the above problems, this utility model provides a long-distance I 2 The C-bus signal enhancement circuit can monitor and provide feedback on the signal status in the circuit, and adjust the matching resistor in real time to reduce signal offset and reflection.

[0004] The specific solution of this utility model is as follows:

[0005] A long-distance I-type intelligent signal reflection suppression system 2 C-bus signal enhancement circuit, including microcontroller unit, I-bus signal enhancement circuit. 2 C-bus and slave device, the slave device connected to I-bus via common mode choke. 2 C bus connection, the I 2 The C bus is connected to the microcontroller unit sequentially via a resistor matching network, a repeater, and the I... 2 The C-bus data lines are also connected to the microcontroller unit via a differential voltage feedback circuit for dynamic monitoring of I. 2 C-bus data signals; the resistor matching network driver is connected to the microcontroller unit and is used to respond to the feedback I... 2 The resistance value of the matching network is dynamically adjusted according to the C bus data signal status.

[0006] This invention addresses the shortcomings in transmission of long cables exceeding 1 meter in length by adding a common-mode choke, a resistor matching network, a repeater, and a differential voltage feedback circuit to the circuit. Through a triple mechanism of "common-mode noise suppression + dynamic threshold decision + dynamic adjustment of the resistor matching network," it suppresses common-mode interference, shortens signal rise / fall time, and effectively avoids sampling errors caused by edge deterioration due to capacitive load.

[0007] Because the slave device is installed externally, it needs to be connected to the internal circuitry via a long cable, resulting in significant distributed capacitance (approximately 100-200 pF per meter) and inductance (approximately 0.5-1 μH per meter). This leads to prolonged signal rise / fall times (e.g., a 1.5-meter cable increases the rise time from the standard 100 ns to over 220 ns), and edge slopes below bus specification requirements (e.g., <0.5V / μs), potentially even triggering MCU sampling errors. This invention incorporates a common-mode choke at the slave device's output. The slave device has SDA and SCL pins. One end of the common-mode choke connects to the SDA and SCL pins respectively, and the other end connects to the first data line and the first clock line respectively. Utilizing the physical layer filtering mechanism of the common-mode choke, this invention specifically addresses the I / O problem. 2 The common-mode noise pollution problem in C-line transmission plays a key role in improving the bus's anti-interference capability and extending the reliable transmission distance (which can extend the effective communication distance from 1.5 meters to 3-5 meters).

[0008] Because the characteristic impedance of the cable is severely mismatched with the IIC standard pull-up resistor, signal reflection occurs, resulting in overshoot and undershoot. The overshoot amplitude can reach 30% of the power supply voltage, leading to incorrect logic level judgment. Therefore, this utility model addresses this issue in IIC... 2 A resistor matching network is connected in series on both the data and clock lines of the C circuit. The specific structure is as follows: The resistor matching network includes two branches, each consisting of an electronic load and a fixed resistor. The W pin of one electronic load is connected to the first data line, and its L pin is led out to the second data line via the fixed resistor. The W pin of the other electronic load is connected to the first clock line, and its L pin is led out to the second clock line via the fixed resistor. The SCLK, DIN, and CS# pins of the two electronic loads are connected to the P0.03 / AIN1, P0.04 / AIN2, and P0.05 / AIN3 pins of the microcontroller unit via the IIC_SCL_R, IIC_SDA_R, and CS leads, respectively. The resistor matching network consists of adjustable and fixed resistors. The microcontroller unit can dynamically adjust the adjustable resistors based on feedback from the feedback circuit, thereby eliminating signal reflections caused by impedance mismatch, optimizing signal edge slope and timing consistency, balancing load capacitance and drive capability, and enhancing the bus's anti-interference robustness.

[0009] Furthermore, the SCLA and SDAA pins of the repeater are connected to the second clock line and the second data line, respectively, and its SCLB and SDAB pins are connected to the P0.26 and P0.27 pins of the microcontroller unit via the third clock line and the third data line, respectively. The repeater includes a buffer and a Schmitt trigger. The buffer, by reducing the output impedance, increases the drive current by more than 10 times, effectively shortening the signal rise / fall time and satisfying I0. 2 The C-bus specifies strict requirements for edge slope to prevent sampling errors caused by edge degradation due to capacitive loads. Simultaneously, the high input impedance and low output impedance of the buffer provide electrical isolation, decoupling the parasitic parameters of long cables from the preceding driver circuitry. This prevents sudden load changes in the subsequent stage from impacting the main controller and also prevents the total load capacitance from exceeding I when multiple slave devices are connected in parallel. 2 The C-bus has a 400pF limit, which improves system robustness.

[0010] Furthermore, the differential voltage feedback circuit includes a differential amplifier and an operational amplifier. The non-inverting input of the differential amplifier is connected to the first data line, its inverting input is grounded, and its output is connected to the non-inverting input of the operational amplifier. The inverting input of the operational amplifier is connected to its output, and the output of the operational amplifier is connected to the P0.02 / AIN0 pin of the microcontroller unit via a filter circuit. This invention dynamically monitors I by setting up a differential voltage feedback circuit. 2 The C data signal amplitude is used to filter out overshoot and undershoot waveforms of a certain amplitude and feed them back to the microcontroller unit. The resistance value of the resistor matching network is adjusted in time to compensate for the level offset and attenuation of long-distance transmission.

[0011] This invention suppresses common-mode interference through a common-mode choke and optimizes signal edge slope by isolating parasitic capacitance and inductance through a repeater. It also improves signal quality by adjusting circuit resistance in real time through a resistor matching network and differential voltage feedback circuit to suppress signal reflection and offset. Attached Figure Description

[0012] Figure 1 This is a schematic diagram of the principle of this utility model;

[0013] Figure 2 This is the circuit diagram of the microcontroller unit;

[0014] Figure 3 This is the circuit diagram of a barometric pressure sensor;

[0015] Figure 4 This is the circuit diagram of the first branch of the resistor matching network;

[0016] Figure 5 This is the circuit diagram of the second branch of the resistor matching network.

[0017] Figure 6 This is the circuit diagram of a repeater;

[0018] Figure 7 This is the circuit diagram of a differential voltage feedback circuit. Detailed Implementation

[0019] The following uses the barometric pressure sensor I... 2 Taking the C-bus circuit as an example, the embodiments of this utility model will be described in detail with reference to the accompanying drawings.

[0020] A long-distance I-type intelligent signal reflection suppression system 2 C-bus signal enhancement circuit, such as Figure 1 As shown, it includes a pressure sensor, a common-mode choke, a resistor matching network, a repeater, and a microcontroller unit. The pressure sensor is located externally to the device and is connected via I... 2 The C bus connects to the host within the device, the I... 2 The C bus is equipped with a common-mode choke to suppress common-mode interference. Then, the I... 2 The C bus is connected to the microcontroller unit sequentially via a resistor matching network, a repeater, and the I... 2 The C-bus data lines are also connected to the microcontroller unit via a differential voltage feedback circuit for dynamic monitoring of I. 2 C-bus data signals. The resistor matching network driver is connected to the microcontroller unit and is used to respond to the feedback I... 2 The resistance value of the resistor matching network is dynamically adjusted according to the C-bus data signal status. The repeater contains a buffer and a Schmitt trigger. Utilizing the high input impedance and low output impedance characteristics of the buffer, the parasitic parameters of long cables are isolated, the drive current is increased, and the signal rise / fall time is shortened.

[0021] Combined with appendix Figure 2-7 The circuit structure of this utility model will be described in detail below.

[0022] like Figure 3 As shown, the barometric pressure sensor U7 collects signals and outputs them to the common mode choke L6 through the SDA and SCL pins. The other end of the common mode choke L6 leads out the first data line SDA2 and the first clock line SCL2. The first data line SDA2 and the first clock line SCL2 are connected to the DC power supply VO through pull-up resistors R37 and R38.

[0023] like Figure 2 , 4As shown in Figure 5, the resistor matching network includes a first branch and a second branch. The first branch includes a first electronic load Rv1 and a first fixed resistor Rf1, and the second branch includes a second electronic load Rv2 and a second fixed resistor Rf2. The first data line SDA2, led out from the common-mode choke L6, is connected to the W pin of the first electronic load. The L pin of the first electronic load Rv1 is connected to the first fixed resistor Rf1, and then the second data line SDA_OUTSIDE is led out. The first clock line SCL2, led out from the common-mode choke L6, is connected to the W pin of the second electronic load Rv2. The L pin of the second electronic load Rv2 is connected to the second fixed resistor Rf2, and then the second clock line SCL_OUTSIDE is led out. The SCLK pin, DIN pin, and CS# pin of the first and second electronic loads are connected to the P0.03 / AIN1 pin, P0.04 / AIN2 pin, and P0.05 / AIN3 pin of the microcontroller U13 via the IIC_SCL_R lead, IIC_SDA_R lead, and CS lead, respectively. 2 The C bus signal is filtered by a common-mode choke and then connected in series with a resistor matching network. The driver of the resistor matching network is connected to the microcontroller unit, which adjusts the resistance value in the circuit.

[0024] like Figure 2 , 6 As shown, the repeater U11 is model PCA9517ADP,118. The SCLA and SDAA pins of repeater U11 are connected to the DC power supply VO via pull-up resistors R28 and R29, respectively, and are also connected to the second clock line SCL_OUTSIDE and the second data line SDA_OUTSIDE from the electronic load. Its SCLB and SDAB pins are connected to the DC power supply VCC via pull-up resistors R26 and R27, respectively, and are also connected to the P0.26 and P0.27 pins of the microcontroller U13 via the third clock line SCL and the third data line SDA. 2 The C-bus signal is connected to a repeater, which contains a buffer and a Schmitt trigger. The buffer is used to increase the drive current, shorten the signal rise / fall time, and isolate parasitic parameters so as to output a high-quality signal to the microcontroller unit.

[0025] like Figure 3 , 7As shown, the differential voltage feedback circuit includes a differential amplifier U9 and an operational amplifier U12.2. The non-inverting input of differential amplifier U9 is connected to the first data line SDA2 from the common-mode choke to acquire the SDA signal in the bus; the inverting input of differential amplifier U9 is grounded. The output of differential amplifier U9 is connected to the non-inverting input of operational amplifier U12.2, and the output of operational amplifier U12.2 is connected to the P0.02 / AIN0 pin of the microcontroller unit via a filter circuit to feed back the acquired SDA signal to the microcontroller unit, which then judges the signal condition in the circuit and adjusts the resistance of the resistor matching network.

Claims

1. A long-distance I-type intelligent signal reflection suppression system 2 C-bus signal enhancement circuit, including microcontroller unit, I-bus signal enhancement circuit. 2 C-bus and slave device, characterized in that: The slave device passes through a common mode choke and I 2 C bus connection, the I 2 The C bus is connected to the microcontroller unit sequentially via a resistor matching network, a repeater, and the I... 2 The C-bus data lines are also connected to the microcontroller unit via a differential voltage feedback circuit for dynamic monitoring of I. 2 C-bus data signals; the resistor matching network driver is connected to the microcontroller unit and is used to respond to the feedback I... 2 The resistance value of the matching network is dynamically adjusted according to the C bus data signal status.

2. The long-distance intelligent signal reflection suppression method according to claim 1 2 The C-bus signal enhancement circuit is characterized by: The slave device has an SDA pin and an SCL pin. One end of the common-mode choke is connected to the SDA pin and the SCL pin of the slave device, respectively, and the other end is connected to the first data line and the first clock line, respectively.

3. The long-distance I-type intelligent signal reflection suppression according to claim 2 2 The C-bus signal enhancement circuit is characterized by: The resistor matching network includes two branches, each including an electronic load and a fixed resistor. The W pin of one electronic load is connected to the first data line, and its L pin is led out to the second data line through the fixed resistor. The W pin of the other electronic load is connected to the first clock line, and its L pin is led out to the second clock line through the fixed resistor. The SCLK pin, DIN pin, and CS# pin of the two electronic loads are connected to the P0.03 / AIN1 pin, P0.04 / AIN2 pin, and P0.05 / AIN3 pin of the microcontroller unit through the IIC_SCL_R lead, IIC_SDA_R lead, and CS lead, respectively.

4. The long-distance intelligent signal reflection suppression method according to claim 3 2 The C-bus signal enhancement circuit is characterized by: The repeater's SCLA and SDAA pins are connected to the second clock line and the second data line, respectively, and its SCLB and SDAB pins are connected to the microcontroller's P0.26 and P0.27 pins via the third clock line and the third data line, respectively.

5. The long-distance I-type intelligent signal reflection suppression according to claim 2 2 The C-bus signal enhancement circuit is characterized by: The differential voltage feedback circuit includes a differential amplifier and an operational amplifier. The non-inverting input of the differential amplifier is connected to the first data line, its inverting input is grounded, and its output is connected to the non-inverting input of the operational amplifier. The inverting input of the operational amplifier is connected to its output, and the output of the operational amplifier is connected to the P0.02 / AIN0 pin of the microcontroller unit via a filter circuit.

Images