5G networked industrial data acquisition system

Abstract

The utility model provides a 5G networked industrial data acquisition system, and relates to the technical field of data acquisition systems, the 5G networked industrial data acquisition system comprises a control module, the control module is internally provided with a dual-channel data processor, and the dual-channel data processor is used for processing data; the 5G communication module is connected with the first sending end of the control module and used for sending data; the data acquisition module comprises an uplink RS485 circuit and a downlink MBUS circuit; the uplink RS485 circuit is connected with a first receiving end of the control module and is used for acquiring PLC equipment data; the downlink MBUS circuit is connected with a second receiving end of the control module and is used for receiving analog data; and the power supply module is used for supplying power to the control module, the 5G communication module and the data acquisition module.

Description

Technical Field

[0001] This application relates to the technical field of data acquisition systems, and in particular to a 5G-connected industrial data acquisition system. Background Technology

[0002] In today's era of rapid industrial automation development, industrial data acquisition systems have become a key support for promoting intelligent and efficient industrial production. With the deepening of the Industry 4.0 concept, the demand for real-time and accurate collection and analysis of various data, such as equipment operating status and production parameters, in industrial production processes is becoming increasingly urgent. This data is not only crucial for optimizing production processes and improving product quality, but also a core element for achieving predictive maintenance, reducing production costs, and enhancing enterprise competitiveness. As a bridge connecting industrial equipment and upper-level management systems, the performance of industrial data acquisition systems directly affects the operational efficiency and intelligence level of the entire industrial production system.

[0003] Chinese invention patent application CN115426627A discloses an industrial IoT data acquisition box based on a 5G network. This acquisition box includes a monitoring center, and a data acquisition module, a data processing module, and a storage module electrically connected to the monitoring center. The data acquisition module consists of multiple data acquisition terminals, responsible for continuously acquiring industrial data generated by each data port and attempting to synchronize the data. The data processing module processes the industrial data acquired by different data acquisition terminals, converting it into a data stream and encrypting it. The storage module saves the encrypted data stream and decrypts it upon retrieval. During data processing, it establishes a temporary data storage area, selects a primary data port, synchronizes other data based on the time the primary data port acquires data, marks data gaps and acquires corresponding tags and data, converts it into a raw data stream, and then encrypts it.

[0004] In real-world industrial environments, various types of industrial equipment exist, such as PLCs and sensors, which may require different interfaces for data acquisition. This patent may not be fully compatible with all types of device interfaces, and its data processing flow is relatively fixed, lacking flexibility and adaptability when facing diverse processing needs for different types of industrial data. Utility Model Content

[0005] In order to improve the processing efficiency of various industrial data, this application provides a 5G-connected industrial data acquisition system.

[0006] The technical solution adopted in this application is as follows:

[0007] A 5G-connected industrial data acquisition system includes:

[0008] The control module has a built-in dual-channel data processor for processing data;

[0009] The 5G communication module is connected to the first transmitter of the control module and is used to transmit data;

[0010] The data acquisition module includes an uplink RS485 circuit and a downlink MBUS circuit; the uplink RS485 circuit is connected to the first receiving end of the control module and is used to acquire data from the PLC device; the downlink MBUS circuit is connected to the second receiving end of the control module and is used to receive analog data.

[0011] The power supply module is used to power the control module, 5G communication module, and data acquisition module.

[0012] The upstream RS485 circuit of this application is connected to the first receiving end of the control module and is dedicated to acquiring data from the PLC device. It can stably and accurately obtain information such as the operating status and control commands of the PLC device, providing reliable data support for the automation control of industrial production. The RS485 interface is widely used in the industrial field, and many PLC devices support this interface. Therefore, the upstream RS485 circuit has good compatibility and can be easily connected to various types of PLC devices for data acquisition, reducing the difficulty and cost of system integration.

[0013] The downlink MBUS circuit of this application is connected to the second receiving end of the control module to receive analog data. In industrial production, many sensors and devices generate analog signals, such as temperature sensors and pressure sensors. The MBUS circuit can effectively receive this analog data and convert it into digital signals for processing by the control module.

[0014] The control module of this application incorporates a dual-channel data processor, which, compared to a single-channel processor, can process two different data streams simultaneously, resulting in higher data processing efficiency within the same timeframe. For complex industrial data processing tasks, such as simultaneous data calculation, analysis, judgment, and decision support, the dual-channel data processor can divide the workload among different tasks. One channel handles data with high real-time requirements, such as equipment status monitoring data, enabling rapid analysis and feedback; the other channel handles data with slightly lower real-time requirements but high computational demands, such as statistical analysis of production data, thereby improving the overall system's adaptability to complex tasks. The dual-channel design also provides redundancy; if one channel fails, the other can continue operating, ensuring that the system's basic data processing functions remain unaffected, thus improving system reliability and stability.

[0015] Optionally, the data acquisition module further includes at least one analog-to-digital conversion unit, which includes an ADC chip. The digital output terminal of the ADC chip is connected to the fourth receiving terminal of the control module for converting analog signals into digital signals.

[0016] The ADC chip (Analog-to-Digital Converter) in the analog-to-digital conversion unit converts the analog signals received by the data acquisition module into discrete digital signals. By directly transmitting the converted analog signals to the control module, this application reduces the complex analog signal transmission and processing procedures between the data acquisition module and the control module, thus simplifying the system architecture.

[0017] Optionally, the analog-to-digital conversion unit further includes a MAX384 multiplexer chip, the signal selection terminal of which is connected to the second control terminal of the control module, and the signal output terminal of which is connected to the analog input terminal of the ADC chip.

[0018] The introduction of the MAX384 multiplexing chip enables a single ADC chip to process data from multiple analog signal channels. Through the connection between its signal selection terminal and the second control terminal of the control module, the analog signals from different channels are transmitted to the ADC chip for conversion in sequence under the control of the control module. Thus, multi-channel analog signal acquisition is achieved with fewer ADC chips, effectively optimizing hardware resources and reducing system costs.

[0019] By using the MAX384 multiplexing chip, this application eliminates the need to lay separate lines to the ADC chip for each analog signal channel. Instead, multiple analog signal sources are connected to the corresponding channel inputs of the MAX384 multiplexing chip, and the signal output of the MAX384 is connected to the analog input of the ADC chip via a single line. This solution simplifies the wiring complexity of the circuit board, reduces signal interference and attenuation problems that may result from long-distance wiring, and improves the reliability and stability of the circuit.

[0020] Optionally, the analog-to-digital conversion unit further includes an anti-aliasing filter, the signal output terminal of which is connected to the signal input terminal of the MAX384 multiplexer chip.

[0021] The anti-aliasing filter is connected before the signal input of the MAX384 multiplexer chip. It can filter out high-frequency components in the analog signal that are higher than half the sampling frequency in advance, thereby improving the accuracy of the signals input to the MAX384 multiplexer chip and subsequent ADC chips.

[0022] Optionally, the system further includes:

[0023] The bus switching module includes a multiplexer and a protocol physical layer conversion chip;

[0024] The signal input terminal of the multiplexer is connected to the first control terminal of the control module, and the signal output terminal of the multiplexer is connected to the signal input terminal of the protocol physical layer conversion chip.

[0025] The multiplexer in the bus switching module works in conjunction with the protocol-physical layer conversion chip, enabling the system to flexibly adapt to various bus protocols. In industrial scenarios, different devices may use different bus protocols for communication, such as CAN bus, RS-485 bus, and Ethernet bus. The multiplexer dynamically selects different signal channels based on commands issued by the control module's first control terminal, transmitting control signals to the protocol-physical layer conversion chip. The protocol-physical layer conversion chip is then responsible for converting the physical layer signals of one bus protocol into physical layer signals of another, achieving seamless connection and communication between devices using different protocols.

[0026] Optionally, the system further includes:

[0027] The data buffer module includes at least one dual-port RAM storage unit. The signal input terminal of the dual-port RAM storage unit is connected to the second transmitting terminal of the control module, and the signal output terminal of the dual-port RAM storage unit is connected to the signal input terminal of the 5G communication module.

[0028] Dual-port RAM storage units can temporarily store data sent by the control module until the 5G communication module is ready to receive and transmit this data. Dual-port RAM storage units allow simultaneous read and write operations, reducing the waiting time required for alternating read and write operations in traditional single-port memory. In industrial real-time control systems, time accuracy is crucial; reducing waiting time ensures timely transmission and processing of control commands and data, improving data processing efficiency.

[0029] Optionally, the system further includes:

[0030] The image acquisition module has its signal output terminal connected to the third receiving terminal of the control module to acquire visual data from industrial equipment.

[0031] Optionally, the system further includes an edge computing module, which includes an FPGA chip and a dual-port SRAM chip. The signal input terminal of the FPGA chip is connected to the output terminal of the image acquisition module, and the signal output terminal of the FPGA chip is connected to the signal input terminal of the dual-port SRAM chip. The signal output terminal of the dual-port SRAM chip is connected to the third receiving terminal of the control module.

[0032] After the image acquisition module outputs image data, the FPGA chip can process multiple pixels or image regions simultaneously, shortening the image data processing time. The dual-port SRAM chip has high-speed read and write characteristics, and the image data processed by the FPGA chip can be quickly stored in the dual-port SRAM chip. At the same time, the control module can read the processed data from the other port of the dual-port SRAM chip in a timely manner. The above scheme reduces the waiting and blocking of data during transmission and improves the smoothness and real-time performance of image data processing.

[0033] Optionally, both the upstream RS485 circuit and the downstream MBUS circuit have a protection circuit at their signal receiving ends. The protection circuit includes a TVS diode array to suppress electrostatic discharge and surge voltage.

[0034] Optionally, the protection circuit further includes a common-mode choke for filtering out common-mode electromagnetic interference.

[0035] In summary, this application includes at least one of the following beneficial technical effects:

[0036] 1. The upstream RS485 circuit of this application is connected to the first receiving end of the control module and is dedicated to acquiring data from the PLC device. It can stably and accurately obtain information such as the operating status and control commands of the PLC device, providing reliable data support for the automation control of industrial production. The RS485 interface is widely used in the industrial field, and many PLC devices support this interface. Therefore, the upstream RS485 circuit has good compatibility and can be easily connected to various types of PLC devices for data acquisition, reducing the difficulty and cost of system integration.

[0037] 2. The control module of this application incorporates a dual-channel data processor. Compared to a single-channel processor, it can process two different data streams simultaneously, resulting in higher data processing efficiency within the same timeframe. For complex industrial data processing tasks, such as simultaneous data calculation, analysis, judgment, and decision support, the dual-channel data processor can divide the workload among different tasks. One channel handles data with high real-time requirements, such as equipment status monitoring data, enabling rapid analysis and feedback; the other channel handles data with slightly lower real-time requirements but high computational demands, such as statistical analysis of production data, thereby improving the system's adaptability to complex tasks. The dual-channel design also provides redundancy; if one channel fails, the other can continue operating, ensuring that the system's basic data processing functions remain unaffected, thus improving system reliability and stability. Attached Figure Description

[0038] Figure 1 This is the circuit schematic diagram of the control module of this application;

[0039] Figure 2 This is the circuit schematic of the uplink RS485 circuit of this application;

[0040] Figure 3 This is the circuit schematic of the downlink MBUS circuit of this application;

[0041] Figure 4 This is the circuit schematic of the analog-to-digital conversion unit of this application;

[0042] Figure 5 This is the circuit schematic diagram of the power module of this application;

[0043] Figure 6 This is a circuit schematic diagram of the multiplexer and protocol physical layer conversion chip of this application;

[0044] Figure 7 This is the circuit schematic of the data buffer module of this application;

[0045] Figure 8 This is the circuit schematic of the edge computing module of this application. Detailed Implementation

[0046] The following combination Figures 1 to 8 This application will be described in further detail.

[0047] This embodiment discloses a 5G-connected industrial data acquisition system, including: a control module, a 5G communication module, a data acquisition module, a power supply module, a bus switching module, a data buffer module, an image acquisition module, and an edge computing module, which improves the processing efficiency of various industrial data. The structure and connection method of this embodiment are described below:

[0048] The control module has a built-in dual-channel data processor for receiving data, processing data, sending control signals, and coordinating the work of various modules.

[0049] The first transmitting end of the control module is connected to the 5G communication module to send processed data to the cloud or host computer. The 5G communication module features high speed, low latency, and large capacity, meeting the high data transmission requirements of the Industrial Internet of Things (IIoT). The control module can transmit important production data, equipment status information, and other data to the cloud or host computer in real time via the 5G communication module, enabling remote monitoring and management.

[0050] For example, refer to Figure 1 In this embodiment, the control module uses an STM32H743VIT6 chip, the 5G communication module uses an RM500Q-GL module, and the image acquisition module uses a Sony IMX219 image sensor. The connection methods of the above parts are as follows:

[0051] The first transmitting pin (PG14) of the STM32H743VIT6 chip is connected to the PCIe interface (pins B11 / B13) of the 5G communication module; the first receiving pin (PG9) of the STM32H743VIT6 chip is connected to the RO pin of the uplink RS485 circuit; the second receiving pin (PB1) of the STM32H743VIT6 chip is connected to the DATA_OUT pin of the downlink MBUS circuit; and the fourth receiving pin (PD11) of the STM32H743VIT6 chip is connected to the DOUT pin (SPI) of the ADC chip. Connections: The first control pins PC0-PC7 (GPIO control) of the STM32H743VIT6 chip are connected to the signal input pins S1-S8 of the multiplexer; the second control pins PE0-PE2 (GPIO) of the STM32H743VIT6 chip are connected to the signal selection pins A0-A2 (control bits) of the MAX384 multiplexer chip; the third receiving pins PF9-PF16 (DCMI_D0-DCMI_D7) of the STM32H743VIT6 chip are connected to the data output pins D0-D7 of the image acquisition module.

[0052] In addition to the aforementioned key pin connections, the pin connections in this embodiment also include:

[0053] The PG0 pin of the STM32H743VIT6 chip is connected to the RESET pin of the 5G communication module to provide a low-level reset signal. The PB0 pin of the STM32H743VIT6 chip is connected to the EN pin of the 5G communication module to provide power. The PC8 pin of the STM32H743VIT6 chip is connected to the STATUS pin of the 5G communication module to read its operating status.

[0054] The PC6 pin of the STM32H743VIT6 chip is connected to the DCMI_CLK clock pin of the image acquisition module for outputting clock control signals. The PF8 pin of the STM32H743VIT6 chip is connected to the HSYNC synchronization pin of the image acquisition module for reading frame synchronization signals.

[0055] In other embodiments, if the multiplexer needs to be expanded to 16 channels, the PD0-PD2 pins of the STM32H743VIT6 chip are connected to the A0-A2 pins of another multiplexer.

[0056] The data acquisition module includes an uplink RS485 circuit, a downlink MBUS circuit, and at least one analog-to-digital conversion unit.

[0057] The control module is connected to the uplink RS485 circuit through the first receiving end to achieve stable communication with the PLC device.

[0058] The second receiver of the control module is connected to a downlink MBUS circuit to receive analog data from various sensors. In industrial settings, temperature sensors, pressure sensors, flow sensors, and other sensors generate analog signals, which are transmitted to the control module by the downlink MBUS circuit.

[0059] Both the upstream RS485 circuit and the downstream MBUS circuit have protection circuits at their signal receiving ends. These protection circuits include a TVS diode array and a common-mode choke. The TVS diode array can quickly respond to electrostatic discharge and surge voltages, clamping them within a safe voltage range and protecting the circuit from damage caused by high-energy pulses. The common-mode choke effectively filters out common-mode electromagnetic interference in the industrial environment, reducing interference from external electromagnetic fields on data transmission and improving the accuracy and stability of the acquired data.

[0060] For example, refer to Figure 2 and Figure 3 In this embodiment, the uplink RS485 circuit uses the MAX3485ESA+ chip, the downlink MBUS circuit uses the TSS721A chip, the TVS diode array uses the RCLAMP1521P.TCT chip or the RCLAMP0524J chip, and the common-mode choke uses the DLW43SH101XK2 chip or the B82789C0103N001 chip. The connection method of each circuit or unit of the data acquisition module is as follows:

[0061] The A / B bus terminals of the MAX3485ESA+ chip are connected to a PLC device (such as Port0 of a Siemens S7-1200). The direction control pins of the MAX3485ESA+ chip—the transmit enable pin (DE) and the receive enable pin (RE)—are shorted and connected to the GPIO pins of the PLC device. When the GPIO pin output of the PLC device is high, the MAX3485ESA+ chip is in transmit mode (A bus output, B bus input); when the GPIO pin output of the PLC device is low, the MAX3485ESA+ chip is in receive mode (A bus input, B bus output). The VCC of the MAX3485ESA+ chip is electrically connected to the 3.3V / 5V output pins of the power module.

[0062] The TSS721A chip's MBUS bus (DATA+ / DATA-) connects to various sensors.

[0063] Optionally, the I / O 1 pin of the TVS diode array is connected to the A line of the MAX3485ESA+ chip or the DATA+ line of the TSS721A chip; the I / O 2 pin of the TVS diode array is connected to the B line of the MAX3485ESA+ chip or the DATA- line of the TSS721A chip.

[0064] Optionally, the common-mode choke is connected in series at the front end of the A / B line of the MAX3485ESA+ chip or in series at the front end of the MBUS bus DATA+ / DATA- of the TSS721A chip.

[0065] In other embodiments, the TVS diode array is connected to the MAX3485ESA+ chip or the TSS721A chip via a common-mode choke.

[0066] The third receiving end of the control module is connected to the signal output end of the image acquisition module to acquire visual data from industrial equipment. The image acquisition module includes a high-definition camera, image sensor, etc., and can capture image information during industrial production processes, such as product appearance and equipment surface condition.

[0067] The analog-to-digital conversion unit includes an ADC chip, a MAX384 multiplexer chip, and an anti-aliasing filter.

[0068] The signal selection terminal of the MAX384 multiplexer is connected to the second control terminal of the control module. Under the control of the second control terminal of the control module, the MAX384 multiplexer can dynamically select different analog signal channels, integrating multiple analog signal sources into the input terminal of an ADC chip. The ADC chip then converts the selected analog signal into a digital signal and transmits the converted data to the fourth receiving terminal of the control module through its digital output terminal.

[0069] In industrial monitoring systems, it is sometimes necessary to simultaneously acquire analog signals such as temperature and pressure from multiple different locations. The MAX384 multiplexer chip can, according to the instructions of the control module, sequentially transmit the analog signals from each channel through its own signal output terminal to the analog input terminal of the ADC chip for analog-to-digital conversion. This achieves efficient acquisition and processing of multi-channel analog signals, reducing hardware costs and circuit complexity.

[0070] The signal output of the anti-aliasing filter is connected to the signal input of the MAX384 multiplexer chip. During analog signal sampling, if the sampling frequency does not satisfy the Nyquist sampling theorem, high-frequency signals will alias into the low-frequency band, causing signal distortion. The function of the anti-aliasing filter is to filter out high-frequency components in the analog signal that are higher than half the sampling frequency, thereby reducing aliasing.

[0071] For example, refer to Figure 4In this embodiment, the ADC chip used is the ADS1256IDBR chip (24-bit Σ-Δ ADC), the MAX384 multiplexing chip is the MAX384CPN+ chip, and the anti-aliasing filter is the LTC1562CGN chip. The models and connection methods of each chip in the analog-to-digital conversion unit are as follows:

[0072] The analog input pins AIN0-AIN7 of the ADS1256IDBR chip are connected to the signal output pin COM of the MAX384 multiplexer chip.

[0073] The signal input pins IN0-IN15 of the MAX384CPN+ chip are connected to the LPFOUT pin of each LTC1562CGN anti-aliasing filter chip. The second control pins PE0-PE2 (GPIO) of the STM32H743VIT6 chip are connected to the signal selection pins A0-A2 (control bits) of the MAX384 multiplexer chip. (Note: The last sentence appears to be incomplete and possibly refers to a connection to a different chip.) Figure 2 As shown in the diagram, it will not be marked again here. The MAX384CPN+ chip selects the active channel through the A0-A2 address pins (e.g., A0=0, A1=1, A2=0 selects channel 3), and the strobe signal is output from the COM pin.

[0074] The IN+ pin of the LTC1562CGN anti-aliasing filter chip is used to receive the analog signal INPUT from the downlink MBUS circuit, and the BYPASS pin is grounded through a resistor to serve as IN-, forming a differential input.

[0075] Reference Figure 5 The power supply module powers the control module, 5G communication module, and data acquisition module. It also powers the bus switching module, data buffer module, image acquisition module, and edge computing module. The power supply module receives either direct current (AC) or alternating current (DC) as its input.

[0076] For example, the power module uses the LM2596S-5.0 and is connected to the power input pins of other modules via the power output pins.

[0077] In industrial production, different devices may use different bus protocols for communication, such as CAN bus, PROFIBUS bus, and Ethernet bus. Under the control of the control module, the bus switching module can flexibly adapt to multiple bus protocols, enabling seamless connection and communication between devices. The bus switching module in this embodiment includes a multiplexer and a protocol-physical layer conversion chip.

[0078] The signal input terminal of the multiplexer is connected to the first control terminal of the control module, and the signal output terminal of the multiplexer is connected to the signal input terminal of the protocol physical layer conversion chip. The control module can send control signals to the multiplexer through the first control terminal to select different bus protocol channels and realize communication switching between devices with different bus protocols.

[0079] Optionally, the protocol physical layer conversion chip can also send feedback signals to the control module through its output terminal.

[0080] For example, refer to Figure 6 In this embodiment, the multiplexer uses the ADG1606BRUZ chip, and the protocol physical layer conversion chip uses the MAX13080ESA+ chip. The connection methods of each part are as follows:

[0081] The protocol physical layer conversion chip connects the TXD pin of the MAX13080ESA+ chip to the COM pin of the ADG1606BRUZ chip. The output pin RO of the MAX13080ESA+ chip is connected to the SPI_MISO pin of the control module.

[0082] In this embodiment, the signals at the signal input terminals of the ADG1606BRUZ (e.g., S1 represents Modbus RTU, S2 represents CAN, and S3 represents Profibus) are switched and uniformly converted by the MAX13080ESA+ into UART / TTL signals for processing by the control module.

[0083] The data buffer module includes at least one dual-port RAM storage unit. The signal input terminal of the dual-port RAM storage unit is connected to the second transmitting terminal of the control module, and the signal output terminal of the dual-port RAM storage unit is connected to the signal input terminal of the 5G communication module. The control module can first store the data to be transmitted in the dual-port RAM storage unit, and then the 5G communication module reads the data from the dual-port RAM storage unit for transmission. This solves the problem of mismatch between the data generation rate of the control module and the data transmission rate of the 5G communication module, improving the stability and smoothness of data transmission.

[0084] For example, refer to Figure 7 In this embodiment, the dual-port RAM storage unit uses the IDT70V27L20PFGI chip. The D0-D17 pins of the IDT70V27L20PFGI chip are connected to the PA0-PA17 pins of the control module; the Q0-Q17 pins of the IDT70V27L20PFGI chip are connected to the PCIe data line of the signal input terminal of the 5G communication module.

[0085] In other embodiments, the system further includes an edge computing module, which includes an FPGA chip and a dual-port SRAM chip. The signal input terminal of the FPGA chip is connected to the output terminal of the image acquisition module, and the signal output terminal of the FPGA chip is connected to the signal input terminal of the dual-port SRAM chip. The signal output terminal of the dual-port SRAM chip is connected to the third receiving terminal of the control module.

[0086] The FPGA chip performs preliminary processing and analysis on the image data, such as image preprocessing and target detection. The processed results are stored in a dual-port SRAM chip, and then transmitted to the third receiving end of the control module through the signal output terminal of the dual-port SRAM chip.

[0087] For example, refer to Figure 8 The FPGA chip used is the Xilinx Zynq-7020 chip, and the dual-port SRAM chip is the CY7C1061DV33-10ZSXI chip. The signal input terminals IO0-IO7 of the Xilinx Zynq-7020 chip are connected to the D0-D7 pins of the image acquisition module; the signal input terminals DQ0-DQ7 of the CY7C1061DV33-10ZSXI chip are connected to the IO8-IO15 pins of the Xilinx Zynq-7020 chip; and the signal output terminals Q0-Q7 of the CY7C1061DV33-10ZSXI chip are connected to the third receiving terminal PF9-PF16 pins of the control module.

[0088] In addition to the aforementioned key pin connections, the pin connections in this embodiment also include:

[0089] The frame synchronization signal pin FS of the image acquisition module is connected to the GPIO_0 pin of the FPGA chip. When the image acquisition module starts to acquire a new frame of image, it will generate a pulse signal on the FS pin. By detecting the level change on the GPIO_0 pin, the FPGA chip can accurately identify the arrival of the new frame of image data, thereby initializing the relevant image processing parameters, such as the frame counter and the image buffer address.

[0090] The image acquisition module's line synchronization signal pin HS is connected to the GPIO_1 pin of the FPGA chip. During the acquisition of one frame of image data, the image acquisition module generates a pulse signal on the HS pin after each line of pixel data is acquired. By monitoring the level changes of the GPIO_1 pin, the FPGA chip can accurately determine the starting position of each line of image data, thereby storing the received pixel data into memory in the correct order.

[0091] The pixel clock signal PCLK pin of the image acquisition module is connected to the CLK_IN_0 pin of the FPGA chip. The FPGA chip samples the data on the D0-D7 pins output by the image acquisition module according to the rising or falling edge of the PCLK signal in order to acquire image data at the correct time.

[0092] The write enable pin (WE) of the dual-port SRAM chip is connected to the GPIO_2 pin of the FPGA chip. When the FPGA chip needs to write data to the dual-port SRAM chip, it sets the GPIO_2 pin to an active level (low level), allowing data to be written to the specified memory cell via pins DQ0-DQ7. After the write operation is complete, the FPGA chip sets the GPIO_2 pin to an inactive level, disabling the write operation.

[0093] The chip select signal CS pin of the dual-port SRAM chip is connected to the GPIO_3 pin of the FPGA chip. When the FPGA chip needs to access the dual-port SRAM chip, it sets the GPIO_3 pin to an active level (low level), thus selecting the dual-port SRAM chip, allowing read and write operations. After the access is complete, the FPGA chip sets the GPIO_3 pin to an inactive level, deselecting the dual-port SRAM chip.

[0094] The output enable signal OE pin of the dual-port SRAM chip is connected to the GPIO_4 pin of the FPGA chip. When the FPGA chip needs to read data from the dual-port SRAM chip, it sets the GPIO_4 pin to an active level (low level). At this time, the dual-port SRAM chip outputs the data stored at the specified address through pins Q0-Q7. After the read operation is completed, the FPGA chip sets the GPIO_4 pin to an inactive level, disabling data output.

[0095] The clock signal CLK pin of the dual-port SRAM chip is connected to the CLK_IN_1 pin of the FPGA chip.

[0096] The working principle of this embodiment is as follows:

[0097] This 5G-connected industrial data acquisition system is centered around a control module. It acquires digital signals from PLC devices and analog signals from various sensors via uplink RS485 circuits and downlink MBUS circuits, respectively. Anti-interference protection is achieved using a TVS diode array and a common-mode choke. Analog signals are processed by an anti-aliasing filter and then dynamically switched between channels by a MAX384 multiplexer chip before being converted into digital signals by an ADC chip. Simultaneously, the image acquisition module transmits industrial scene image data to the control module via a DCMI interface. The FPGA chip performs edge preprocessing (such as target detection) on the images and stores them in a dual-port SRAM before feeding them back to the control module. The system supports adaptive switching of multiple bus protocols through a multiplexer and a protocol physical layer conversion chip. The dual-port RAM storage unit buffers data to match the transmission rate differences between the control module and the 5G communication module. Finally, the processed production data, equipment status, and image analysis results are uploaded to the cloud in real time via the 5G network, enabling remote monitoring and closed-loop control. The power module provides stable power to the entire system, ensuring efficient and reliable operation in complex industrial environments.

[0098] The above are all preferred embodiments of this application, and are not intended to limit the scope of protection of this application. Therefore, all equivalent changes made in accordance with the structure, shape and principle of this application should be covered within the scope of protection of this application.

Claims

1. A 5G-connected industrial data acquisition system, characterized in that, include: The control module has a built-in dual-channel data processor for processing data; The 5G communication module is connected to the first transmitter of the control module and is used to transmit data; The data acquisition module includes an uplink RS485 circuit and a downlink MBUS circuit; the uplink RS485 circuit is connected to the first receiving end of the control module and is used to acquire data from the PLC device; the downlink MBUS circuit is connected to the second receiving end of the control module and is used to receive analog data. The power supply module is used to power the control module, 5G communication module, and data acquisition module.

2. The 5G-connected industrial data acquisition system according to claim 1, characterized in that, The data acquisition module further includes at least one analog-to-digital conversion unit, which includes an ADC chip. The digital output terminal of the ADC chip is connected to the fourth receiving terminal of the control module and is used to convert analog signals into digital signals.

3. The 5G-connected industrial data acquisition system according to claim 2, characterized in that, The analog-to-digital conversion unit also includes a MAX384 multiplexer chip. The signal selection terminal of the MAX384 multiplexer chip is connected to the second control terminal of the control module, and the signal output terminal of the MAX384 multiplexer chip is connected to the analog input terminal of the ADC chip.

4. The 5G-connected industrial data acquisition system according to claim 3, characterized in that, The analog-to-digital conversion unit also includes an anti-aliasing filter, the signal output terminal of which is connected to the signal input terminal of the MAX384 multiplexer chip.

5. The 5G-connected industrial data acquisition system according to claim 1, characterized in that, The system also includes: The bus switching module includes a multiplexer and a protocol physical layer conversion chip; The signal input terminal of the multiplexer is connected to the first control terminal of the control module, and the signal output terminal of the multiplexer is connected to the signal input terminal of the protocol physical layer conversion chip.

6. The 5G-connected industrial data acquisition system according to claim 1, characterized in that, The system also includes: The data buffer module includes at least one dual-port RAM storage unit. The signal input terminal of the dual-port RAM storage unit is connected to the second transmitting terminal of the control module, and the signal output terminal of the dual-port RAM storage unit is connected to the signal input terminal of the 5G communication module.

7. The 5G-connected industrial data acquisition system according to claim 1, characterized in that, The system also includes: The image acquisition module has its signal output terminal connected to the third receiving terminal of the control module to acquire visual data from industrial equipment.

8. The 5G-connected industrial data acquisition system according to claim 7, characterized in that, The system also includes an edge computing module, which includes an FPGA chip and a dual-port SRAM chip. The signal input terminal of the FPGA chip is connected to the output terminal of the image acquisition module, and the signal output terminal of the FPGA chip is connected to the signal input terminal of the dual-port SRAM chip. The signal output terminal of the dual-port SRAM chip is connected to the third receiving terminal of the control module.

9. The 5G-connected industrial data acquisition system according to claim 1, characterized in that, Both the upstream RS485 circuit and the downstream MBUS circuit have protection circuits at their signal receiving ends. These protection circuits include a TVS diode array to suppress electrostatic discharge and surge voltage.

10. The 5G-connected industrial data acquisition system according to claim 9, characterized in that, The protection circuit also includes a common-mode choke for filtering out common-mode electromagnetic interference.

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