Circuit structure for reducing chip heating through divider resistor

Abstract

The utility model provides a circuit structure for reducing heating of a chip through a divider resistor, and the circuit structure comprises a power supply management circuit which comprises a first power supply input port which is used for receiving an external input voltage which is 3.3 V direct current; the second power supply input port is independent of the first power supply input port and is used for supplying power to the outside of the core logic circuit; the VDDIN is connected with a power switch LDOEN for controlling the on / off of a second path of power supply, and the VDDIN is the name of a power supply input pin of the chip core or the power supply input of the chip core; a resistor is connected to an input circuit of the VDDIN and is used for dividing voltage, namely a divider resistor, so that the input voltage of the VDDIN is reduced; and the plurality of low dropout regulator LDOs are used for converting the input voltage into different output voltages. After a built-in LDO (Low Dropout Regulator) realizes voltage conversion, a circuit structure for reducing chip heating through a divider resistor solves the problem of serious chip heating.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor integrated circuit design, and specifically relates to a circuit structure that reduces chip heat generation through voltage divider resistors. Background Technology

[0002] In the field of chip design, heat control is of paramount importance. As a core component of modern electronic devices, the performance and stability of chips directly affect the operation of the entire system. However, chips inevitably generate heat during operation, and if this heat is not effectively controlled, it can lead to a series of serious problems.

[0003] Effective heat control in chip design is not only crucial for chip performance and reliability, but also a key factor in ensuring the smooth progress of chip verification and improving verification accuracy and efficiency.

[0004] Currently, the power supply design of laptop ISP chips is mainly based on low-dropout linear regulators (LDOs), which convert the input 3.3V / 5V voltage into the voltage required for chip operation. The reason for integrating the LDOs into the chip is the extremely small PCB area of ​​laptop ISP modules (generally no more than 2mm in height). Placing LDOs on such a small PCB is quite difficult, and if there are many LDOs, placement and routing become very challenging. In other words, in existing technology, laptop ISP chip designers typically adopt a solution of integrating the LDOs into the chip itself.

[0005] However, integrating LDOs into the chip has its drawbacks. Current technical solutions have the following disadvantages: LDOs generate significant heat, which in turn causes the chip to overheat.

[0006] In addition, the technical terms in this field include:

[0007] Core: The digital logic section of a chip, including most digital modules such as the chip's CPU. Utility Model Content

[0008] To address the aforementioned issues, the purpose of this application is to provide a circuit structure that reduces chip heat generation by using voltage divider resistors after voltage conversion via a built-in LDO, thereby resolving the problem of severe chip overheating.

[0009] Specifically, this utility model provides a circuit structure for reducing chip heat generation through voltage divider resistors. The circuit structure includes a power management circuit, comprising:

[0010] The first power input port is used to receive an external input voltage, which is 3.3V DC.

[0011] The second power input port, independent of the first power input port, is used to provide external power to the core logic circuit.

[0012] VDDIN is connected to the power switch LDO_EN, which controls the on / off state of the second power supply. VDDIN is the name of the power supply input pin of the chip core or refers to the power input of the chip core. A resistor is connected to the input circuit of VDDIN to divide the voltage, i.e., a voltage divider resistor, thereby reducing the input voltage of VDDIN.

[0013] Multiple low-dropout linear regulators (LDOs) are used to convert the input voltage into different output voltages.

[0014] The circuit structure also includes:

[0015] The first low-dropout linear regulator, LDO3, converts the input voltage into the first output voltage, which supplies the core logic circuit.

[0016] The second low-dropout linear regulator, LDO2, converts the input voltage into a second output voltage to supply the AON module;

[0017] The third low-dropout linear regulator, LDO1, converts the input voltage into a third output voltage, which is supplied to the physical layer interface circuit.

[0018] The input voltage is 3.3V DC, the first output voltage is 0.9V, the second output voltage is 0.9V, and the third output voltage is 1.8V; the core logic circuit is C200Core Logics, the AON module is C200 AON, and the physical layer interface circuit is C2001.8V IO / MIPIPHY.

[0019] The circuit also includes:

[0020] One direct power distribution path supplies the input voltage directly to another physical layer interface circuit; another power distribution path supplies the third output voltage to the low-voltage input / output interface.

[0021] The other physical layer interface circuit is C200 3.3V IO / USB PHY / RC, and the low voltage input / output interface is VDDIO33.

[0022] The circuit structure also includes:

[0023] An enable control circuit, LDO_EN, is used to control the enable terminals of each low-dropout linear regulator to achieve dynamic control of the output voltage.

[0024] The resistance value is determined according to the required voltage division ratio to ensure that the input voltage of VDDIN meets the operating voltage requirements of the core logic circuit.

[0025] The circuit structure further includes:

[0026] Dual power input:

[0027] The first power input is VDDIO33, which is the chip's 3.3V input. The LDO itself is powered by VDDIO33. The LDO's function is to convert the voltage input from VDDIN and VDDIO33 to output the required voltage.

[0028] The second power input, independent of the first power input, is used to provide external power to the C200 Core Logics. The VDDIN is the power input for the C200 Core Logics.

[0029] Voltage divider resistors:

[0030] The voltage divider resistors are connected to the external input circuitry of the C200 Core Logics to reduce the input voltage of VDDIN, thereby reducing the chip's heat generation.

[0031] LDO voltage regulator:

[0032] LD03, connected to VDDIN, is used to regulate the input voltage xV to 0.9V and to power the C200 Core Logics;

[0033] LD02, connected to VDDIO33, is used to regulate the 3.3V input voltage to 0.9V and to provide power to the C200AON;

[0034] LD01, connected to VDDIO33, is used to regulate the 3.3V input voltage to 1.8V and to power VDDI018 and C2001.8V IO / MIPIPHY;

[0035] Enable signal control:

[0036] The LDO3_EN signal, connected to LD03, is used to control the enabling or disabling of LD03; the LDO1_EN signal, connected to LD01, is used to control the enabling or disabling of LD01.

[0037] Core logic circuit:

[0038] The C200 Core Logics, connected to the output of the LD03, is powered by the 0.9V voltage provided by the LD03 and is used to perform the main calculation and control functions of the system.

[0039] AON module power supply:

[0040] C200 AON, connected to the output of LD02, is powered by the 0.9V voltage provided by LD02 and is used for system monitoring and wake-up functions in low-power mode;

[0041] I / O and USB power:

[0042] VDDI033, connected to the 3.3V power input, is used to provide 3.3V power to the C200 3.3V IO / USB PHY / RC;

[0043] C200 3.3V IO / USB PHY / RC, connected to VDDI033, is used for communication functions of I / O and USB interfaces;

[0044] 1.8VI / O and MIPIPHY:

[0045] VDDI018 is connected to the output of LD01 and is powered by the 1.8V voltage provided by LD01 to provide power to C200 1.8VIO / MIPIPHY and CIS;

[0046] C200 1.8V IO / MIPIPHY, connected to VDDI018, is used for communication functions of 1.8VI / O and MIPI interfaces;

[0047] Image sensor:

[0048] The CIS, connected to VDDI018 and powered by 1.8V from LD01, is used to capture image data.

[0049] Therefore, the advantage of this solution is:

[0050] (1) Significantly reduce chip heat generation: Theoretically, this technical solution can reduce chip core heat generation by up to 51%. The higher the core current, the more obvious the effect of reducing chip heat generation.

[0051] (2) The solution is simple to implement and low in cost: In addition to making the power supply of the core independent at the chip level, only an external resistor is needed to significantly reduce the heat generation of the chip. Compared with traditional heat dissipation methods such as adding a copper thermal conductive layer in the PCB or adding an external heat sink, it has the advantages of low cost and good effect. Attached Figure Description

[0052] The accompanying drawings, which are provided to further illustrate the present invention and form part of this application, do not constitute a limitation thereof.

[0053] Figure 1This is a schematic diagram of the circuit structure of this utility model. Detailed Implementation

[0054] To better understand the technical content and advantages of this utility model, a further detailed description of this utility model is now provided in conjunction with the accompanying drawings.

[0055] Compared with the prior art, this utility model has two main key modifications:

[0056] (1) Change the circuit input of the chip from a single power input to a dual power input, so that the core is powered externally independently;

[0057] (2) Connect a resistor to the external input circuit of the core to divide the voltage, thereby reducing the input voltage of VDDIN.

[0058] This invention utilizes a circuit structure that reduces chip heat generation through voltage divider resistors, as shown in the diagram. Figure 1 As shown, the description is as follows:

[0059] The circuit structure includes a power management circuit, comprising:

[0060] The first power input port is used to receive an external input voltage, which is 3.3V DC.

[0061] The second power input port, independent of the first power input port, is used to provide external power to the core logic circuit.

[0062] The power switch LDO_EN controls the on / off state of the second power supply (see reference for specific LDO numbers). Figure 1 (As shown) connected to VDDIN, where VDDIN is the name of the power supply input pin of the chip core or refers to the power supply input of the chip core;

[0063] A resistor is connected to the input circuit of VDDIN to act as a voltage divider, thereby reducing the input voltage of VDDIN.

[0064] Multiple low-dropout linear regulators (LDOs) are used to convert the input voltage into different output voltages.

[0065] The circuit structure also includes:

[0066] The first low-dropout linear regulator, LDO3, converts the input voltage into the first output voltage, which supplies the core logic circuit.

[0067] The second low-dropout linear regulator, LDO2, converts the input voltage into a second output voltage to supply the AON module;

[0068] The third low-dropout linear regulator, LDO1, converts the input voltage into a third output voltage, which is supplied to the physical layer interface circuit.

[0069] The input voltage is 3.3V DC, the first output voltage is 0.9V, the second output voltage is 0.9V, and the third output voltage is 1.8V; the core logic circuit is C200Core Logics, the AON module is C200 AON, and the physical layer interface circuit is C2001.8V IO / MIPIPHY.

[0070] The circuit also includes:

[0071] One direct power distribution path supplies the input voltage directly to another physical layer interface circuit; another power distribution path supplies the third output voltage to the low-voltage input / output interface.

[0072] The other physical layer interface circuit is C200 3.3V IO / USB PHY / RC, and the low voltage input / output interface is VDDIO33.

[0073] The circuit structure also includes:

[0074] An enable control circuit, LDO_EN, is used to control the enable terminals of each low-dropout linear regulator to achieve dynamic control of the output voltage.

[0075] The resistance value is determined according to the required voltage division ratio to ensure that the input voltage of VDDIN meets the operating voltage requirements of the core logic circuit.

[0076] The circuit structure further includes:

[0077] Dual power input:

[0078] The first power input is VDDIO33, which is the chip's 3.3V input. The LDO itself is powered by VDDIO33. The LDO's function is to convert the voltage input from VDDIN and VDDIO33 to output the required voltage.

[0079] The second power input, independent of the first power input, is used to provide external power to the C200 Core Logics. The VDDIN is the power input for the C200 Core Logics.

[0080] Voltage divider resistors:

[0081] The voltage divider resistors are connected to the external input circuitry of the C200 Core Logics to reduce the input voltage of VDDIN, thereby reducing the chip's heat generation.

[0082] LDO voltage regulator:

[0083] LD03, connected to VDDIN, is used to regulate the input voltage (xV) to 0.9V and to power the C200Core Logics;

[0084] LD02, connected to VDDIO33, is used to regulate the 3.3V input voltage to 0.9V and to provide power to the C200AON;

[0085] LD01, connected to VDDIO33, is used to regulate the 3.3V input voltage to 1.8V and to power VDDI018 and C2001.8V IO / MIPIPHY;

[0086] Enable signal control:

[0087] The LDO3_EN signal, connected to LD03, is used to control whether LD03 is enabled or disabled.

[0088] The LDO1_EN signal is connected to LD01 and is used to control whether LD01 is enabled or disabled.

[0089] Core logic circuit:

[0090] The C200 Core Logics, connected to the output of the LD03, is powered by the 0.9V voltage provided by the LD03 and is used to perform the main calculation and control functions of the system.

[0091] AON module power supply:

[0092] C200 AON, connected to the output of LD02, is powered by the 0.9V voltage provided by LD02 and is used for system monitoring and wake-up functions in low-power mode;

[0093] I / O and USB power:

[0094] VDDI033, connected to the 3.3V power input, is used to provide 3.3V power to the C200 3.3V IO / USB PHY / RC;

[0095] C200 3.3V IO / USB PHY / RC, connected to VDDI033, is used for communication functions of I / O and USB interfaces;

[0096] 1.8VI / O and MIPIPHY:

[0097] VDDI018 is connected to the output of LD01 and is powered by the 1.8V voltage provided by LD01 to provide power to C200 1.8VIO / MIPIPHY and CIS;

[0098] C200 1.8V IO / MIPIPHY, connected to VDDI018, is used for communication functions of 1.8VI / O and MIPI interfaces;

[0099] Image sensor:

[0100] The CIS, connected to VDDI018 and powered by 1.8V from LD01, is used to capture image data.

[0101] In addition, it also includes:

[0102] 1. VDDIO18:

[0103] VDDIO18 is a power supply voltage designation, indicating a 1.8V input / output I / O voltage rail. In circuit design, I / O voltage rails are the voltages that supply power to the input / output ports of a device, ensuring that these ports can communicate correctly with external devices or circuits. Figure 1 In this circuit, VDDIO18 is supplied by an LDO1 regulator, which converts the 3.3V voltage to 1.8V.

[0104] 2.C200 1.8V IO / MIPIPHY:

[0105] C200 1.8VIO / MIPIPHY refers to a specific circuit module that requires a 1.8V power supply to operate. This module may include physical layer interfaces such as MIPI (Mobile Industry Processor Interface) PHY, a high-speed serial interface used in mobile devices for connecting cameras, displays, etc. Figure 1 In the diagram, the C200 1.8V IO / MIPIPHY is connected to VDDIO18, indicating that it is powered by the 1.8V voltage rail. In the power management circuitry, the combination of VDDIO18 and C200 1.8V IO / MIPIPHY ensures that interface modules requiring 1.8V power can obtain a stable power supply, thereby supporting normal operation of the device and communication with other devices.

[0106] The above description is merely a preferred embodiment of the present utility model and is not intended to limit the present utility model. For those skilled in the art, various modifications and variations can be made to the embodiments of the present utility model. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present utility model should be included within the protection scope of the present utility model.

Claims

1. A circuit structure for reducing chip heat generation using voltage divider resistors, characterized in that, The circuit structure includes a power management circuit, comprising: The first power input port is used to receive an external input voltage, which is 3.3V DC. The second power input port, independent of the first power input port, is used to provide external power to the core logic circuit. VDDIN is connected to the power switch LDO_EN, which controls the on / off state of the second power supply. VDDIN is the name of the power supply input pin of the chip core or refers to the power supply input of the chip core. Connect a resistor to the input circuit of VDDIN to act as a voltage divider, thereby reducing the input voltage of VDDIN. Multiple low-dropout linear regulators (LDOs) are used to convert the input voltage into different output voltages.

2. The circuit structure for reducing chip heat generation through voltage divider resistors according to claim 1, characterized in that, The circuit structure also includes: The first low-dropout linear regulator, LDO3, converts the input voltage into the first output voltage, which supplies the core logic circuit. The second low-dropout linear regulator, LDO2, converts the input voltage into a second output voltage to supply the AON module; The third low-dropout linear regulator, LDO1, converts the input voltage into a third output voltage, which is supplied to the physical layer interface circuit.

3. The circuit structure for reducing chip heat generation through voltage divider resistors as described in claim 2, characterized in that, The input voltage is 3.3V DC, the first output voltage is 0.9V, the second output voltage is 0.9V, and the third output voltage is 1.8V; the core logic circuit is C200 Core Logics, the AON module is C200 AON, and the physical layer interface circuit is C200 1.8V IO / MIPI PHY.

4. The circuit structure for reducing chip heat generation through voltage divider resistors according to claim 1, characterized in that, The circuit also includes: A direct power distribution path supplies the input voltage directly to another physical layer interface circuit. A power distribution path supplies a third output voltage to the low-voltage input / output interface.

5. The circuit structure for reducing chip heat generation through voltage divider resistors according to claim 4, characterized in that, The other physical layer interface circuit is C200 3.3V IO / USB PHY / RC, and the low voltage input / output interface is VDDIO33.

6. The circuit structure for reducing chip heat generation through voltage divider resistors according to claim 1, characterized in that, The circuit structure also includes: An enable control circuit, LDO_EN, is used to control the enable terminals of each low-dropout linear regulator to achieve dynamic control of the output voltage.

7. The circuit structure for reducing chip heat generation by using voltage divider resistors according to any one of claims 1 to 6, characterized in that, The resistance value is determined according to the required voltage division ratio to ensure that the input voltage of VDDIN meets the operating voltage requirements of the core logic circuit.

8. The circuit structure for reducing chip heat generation through voltage divider resistors according to claim 7, characterized in that, The circuit structure further includes: Dual power input: The first power input is VDDIO33, which is the chip's 3.3V input. The LDO itself is powered by VDDIO33. The LDO's function is to convert the voltage input from VDDIN and VDDIO33 to output the required voltage. The second power input, independent of the first power input, is used to provide external power to the C200 Core Logics. The VDDIN is the power input for the C200 Core Logics. Voltage divider resistors: The voltage divider resistors are connected to the external input circuit of the C200 Core Logics to reduce the input voltage of VDDIN, thereby reducing the heat generated by the chip. LDO voltage regulator: LD03, connected to VDDIN, is used to regulate the input voltage xV to 0.9V and to power the C200 Core Logics; LD02, connected to VDDIO33, is used to regulate the 3.3V input voltage to 0.9V and to provide power to the C200 AON; LD01, connected to VDDIO33, is used to regulate the 3.3V input voltage to 1.8V and to power VDDI018 and C200 1.8VIO / MIPI PHY; Enable signal control: The LDO3_EN signal, connected to LD03, is used to control whether LD03 is enabled or disabled. The LDO1_EN signal is connected to LD01 and is used to control whether LD01 is enabled or disabled. Core logic circuit: The C200 Core Logics, connected to the output of the LD03, is powered by the 0.9V voltage provided by the LD03 and is used to perform the main calculation and control functions of the system. AON module power supply: C200 AON, connected to the output of LD02, is powered by the 0.9V voltage provided by LD02 and is used for system monitoring and wake-up functions in low-power mode; I / O and USB power: VDDI033, connected to the 3.3V power input, is used to provide 3.3V power to the C200 3.3V IO / USB PHY / RC; C200 3.3V IO / USB PHY / RC, connected to VDDI033, is used for communication functions of I / O and USB interfaces; 1.8VI / O and MIPI PHY: VDDI018 is connected to the output of LD01 and is powered by the 1.8V voltage provided by LD01 to provide power to the C200 1.8V IO / MIPI PHY and CIS. C200 1.8V IO / MIPI PHY, connected to VDDI018, is used for communication functions of the 1.8VI / O and MIPI interfaces; Image sensor: The CIS, connected to VDDI018 and powered by 1.8V from LD01, is used to capture image data.

Images