Power module

Abstract

The utility model provides a power module, which comprises the following steps: the power module comprises a lining plate and a power circuit arranged on the lining plate, the power circuit comprises a Vienna rectifier circuit and a three-phase full-bridge circuit, and the output end of the Vienna rectifier circuit is connected with the input end of the three-phase full-bridge circuit; wherein power devices in the Vienna rectification circuit and the three-phase full-bridge circuit are composed of a plurality of power chips with corresponding functions, and the power chips are silicon carbide power chips. The power factor of the power module can be improved by adopting the Vienna rectifying circuit, meanwhile, the output current of the power module is improved through the plurality of power chips, so that the output power is improved, a silicon carbide-based chip is further adopted to replace an existing silicon-based chip, the size of the chip can be reduced, and the cost is reduced. Therefore, under the condition that higher output power is set, the size of the power module is prevented from being increased.

Description

Technical Field

[0001] This utility model relates to the field of semiconductors, and more particularly to a power module. Background Technology

[0002] The existing PIM2 package has a low output power, with the highest specification being only 1200V and 35A. If a chip with a higher output power is used directly, the size of the resulting power module will increase, which is unacceptable. Therefore, how to increase the output power without increasing the size of the existing power module is an urgent problem to be solved. Utility Model Content

[0003] The main objective of this invention is to propose a power module that aims to solve the problem of increasing output power without increasing the size of existing power modules in the prior art.

[0004] To achieve the above objectives, this utility model provides a power module, which includes a substrate and a power circuit disposed on the substrate. The power circuit includes a Vienna rectifier circuit and a three-phase full-bridge circuit, wherein the output terminal of the Vienna rectifier circuit is connected to the input terminal of the three-phase full-bridge circuit; wherein:

[0005] The power devices in the Vienna rectifier circuit and the three-phase full-bridge circuit are composed of several functionally corresponding power chips, and the power chips are silicon carbide power chips.

[0006] Optionally, the power module further includes a lead frame and several pins; the power devices of the Vienna rectifier circuit include a first silicon carbide diode, a second silicon carbide diode, a third silicon carbide diode, a fourth silicon carbide diode, a fifth silicon carbide diode, and a sixth silicon carbide diode constituting the three-phase rectifier circuit, and a first silicon carbide MOSFET, a second silicon carbide MOSFET, a third silicon carbide MOSFET, a fourth silicon carbide MOSFET, a fifth silicon carbide MOSFET, and a sixth silicon carbide MOSFET constituting the bidirectional switching circuit; the power devices of the three-phase full-bridge circuit include a seventh silicon carbide MOSFET, an eighth silicon carbide MOSFET, a ninth silicon carbide MOSFET, a tenth silicon carbide MOSFET, an eleventh silicon carbide MOSFET, and a twelfth silicon carbide MOSFET; wherein:

[0007] The electrodes of the silicon carbide diode and the silicon carbide MOS transistor are led out to the pins through the lead frame.

[0008] Optionally, each silicon carbide diode in the Vienna rectifier circuit is formed by two silicon carbide diode chips connected in parallel, and each silicon carbide MOSFET in the Vienna rectifier circuit is formed by three silicon carbide MOSFET chips connected in parallel;

[0009] Each silicon carbide MOSFET in the three-phase full-bridge circuit is formed by connecting three silicon carbide MOSFET chips in parallel.

[0010] Optionally, each silicon carbide diode in the Vienna rectifier circuit is composed of a silicon carbide diode chip, and each silicon carbide MOSFET in the Vienna rectifier circuit is obtained by connecting two silicon carbide MOSFET chips in parallel;

[0011] Each silicon carbide MOSFET in the three-phase full-bridge circuit is formed by connecting two silicon carbide MOSFET chips in parallel.

[0012] Optionally, the anode electrodes of the first silicon carbide diode, the second silicon carbide diode, and the third silicon carbide diode are led out to the first pin through the lead frame;

[0013] The cathode electrode of the first silicon carbide diode, the anode electrode of the fourth silicon carbide diode, and the drain electrode of the first silicon carbide MOS transistor are led out to the second pin through the lead frame;

[0014] The cathode electrode of the second silicon carbide diode, the anode electrode of the fifth silicon carbide diode, and the drain electrode of the second silicon carbide MOS transistor are led out to the third pin through the lead frame;

[0015] The cathode electrode of the third silicon carbide diode, the anode electrode of the sixth silicon carbide diode, and the drain electrode of the third silicon carbide MOS transistor are led out to the fourth pin through the lead frame;

[0016] The cathode electrodes of the fourth, fifth, and sixth silicon carbide diodes are led out to the twenty-ninth pin through the lead frame;

[0017] The drain electrode of the seventh silicon carbide MOS transistor, the drain electrode of the eighth silicon carbide MOS transistor, and the drain electrode of the ninth silicon carbide MOS transistor are led out to the fifth pin through the lead frame;

[0018] The source electrode of the seventh silicon carbide MOS transistor and the drain electrode of the tenth silicon carbide MOS transistor are led out to the sixth pin through the lead frame;

[0019] The gate electrode of the seventh silicon carbide MOS transistor is led out to the seventh pin through the lead frame;

[0020] The source electrode of the eighth silicon carbide MOS transistor and the drain electrode of the eleventh silicon carbide MOS transistor are led out to the eighth pin through the lead frame;

[0021] The gate electrode of the eighth silicon carbide MOS transistor is led out to the ninth pin through the lead frame;

[0022] The source electrode of the ninth silicon carbide MOS transistor and the drain electrode of the twelfth silicon carbide MOS transistor are led out to the tenth pin through the lead frame;

[0023] The gate electrode of the ninth silicon carbide MOS transistor is led out to the eleventh pin through the lead frame;

[0024] The source electrode of the twelfth silicon carbide MOS transistor is led out to the fourteenth pin through the lead frame;

[0025] The gate electrode of the twelfth silicon carbide MOS transistor is led out to the fifteenth pin through the lead frame;

[0026] The source electrode of the eleventh silicon carbide MOS transistor is led out to the sixteenth pin through the lead frame;

[0027] The gate electrode of the eleventh silicon carbide MOS transistor is led out to the seventeenth pin through the lead frame;

[0028] The source electrode of the tenth silicon carbide MOS transistor is led out to the eighteenth pin through the lead frame;

[0029] The gate electrode of the tenth silicon carbide MOS transistor is led out to the nineteenth pin through the lead frame;

[0030] The gate electrode of the third silicon carbide MOS transistor is led out to the twentieth pin through the lead frame;

[0031] The source electrode of the third silicon carbide MOS transistor and the source electrode of the sixth silicon carbide MOS transistor are led out to the twenty-first pin through the lead frame;

[0032] The gate electrode of the sixth silicon carbide MOS transistor is led out to the twenty-second pin through the lead frame;

[0033] The gate electrode of the fifth silicon carbide MOS transistor is led out to the twenty-third pin through the lead frame;

[0034] The source electrode of the second silicon carbide MOS transistor and the source electrode of the fifth silicon carbide MOS transistor are led out to the twenty-fourth pin through the lead frame;

[0035] The gate electrode of the second silicon carbide MOS transistor is led out to the twenty-fifth pin through the lead frame;

[0036] The gate electrode of the first silicon carbide MOS transistor is led out to the twenty-sixth pin through the lead frame;

[0037] The source electrode of the first silicon carbide MOS transistor and the source electrode of the fourth silicon carbide MOS transistor are led out to the twenty-seventh pin through the lead frame;

[0038] The gate electrode of the fourth silicon carbide MOS transistor is led out to the twenty-eighth pin through the lead frame;

[0039] The drain electrodes of the fourth, fifth, and sixth silicon carbide MOS transistors are led out to the thirtieth pin through the lead frame.

[0040] Optionally, the lead frame includes multiple lead frame mounting frames and multiple lead frame connecting frames; wherein:

[0041] The set lead frame is provided with a plurality of power devices, the drain of the silicon carbide MOS transistor is soldered on the set lead frame, and the set lead frame leads the set power devices to the same pin, the same set lead frame or the electrode of the same power device;

[0042] The connection lead frame is connected to the drain or source of the silicon carbide MOS transistor via bonding wires, and the drain or source of the silicon carbide MOS transistor is led out to the corresponding pin.

[0043] Optionally, the lead frame includes a first lead frame, a second lead frame, a third lead frame, a fourth lead frame, a fifth lead frame, and a sixth lead frame; the first lead frame has a first silicon carbide diode and a first silicon carbide MOSFET disposed on it; the second lead frame has a second silicon carbide diode and a second silicon carbide MOSFET disposed on it; the third lead frame has a fourth silicon carbide diode disposed on it; the fourth lead frame has a fifth silicon carbide diode and a sixth silicon carbide diode disposed on it; the fifth lead frame has a fourth silicon carbide MOSFET, a fifth silicon carbide MOSFET, and a sixth silicon carbide MOSFET disposed on it; and the sixth lead frame has a third silicon carbide diode disposed on it; wherein:

[0044] The first lead frame and the second lead frame are tripod-shaped frames, wherein the tripod-shaped frames have platforms at both ends for welding power devices, and the middle of the tripod-shaped frames sinks to the bottom;

[0045] The fifth setting of the lead frame is a mountain-shaped frame, wherein the mountain-shaped frame has three protruding platforms for welding power devices on the bottom edge, and each platform is corresponding to a silicon carbide MOSFET.

[0046] in:

[0047] The bottom of the first lead frame is positioned opposite to the bottom of the second lead frame;

[0048] The third lead frame is disposed on the lower side of the first lead frame, and the fourth lead frame is disposed on the lower side of the second lead frame.

[0049] The third and fourth lead frames are connected by bonding wires across the bottom of the first and second lead frames.

[0050] The first lead frame sets one end of the first silicon carbide MOS transistor and the second lead frame sets one end of the second silicon carbide MOS transistor, which are located between the two platforms of the mountain-shaped frame. The platform where the fourth silicon carbide MOS transistor is located is opposite to the first silicon carbide MOS transistor, and the platform where the fifth silicon carbide MOS transistor is located is opposite to the second silicon carbide MOS transistor.

[0051] The sixth lead frame is disposed between the fourth lead frame and the corresponding pin.

[0052] Optionally, the lead frame further includes a seventh lead frame, an eighth lead frame, a ninth lead frame, a tenth lead frame, and an eleventh lead frame; the third silicon carbide MOSFET is disposed on the seventh lead frame, and the sixth lead frame is connected to the seventh lead frame via bonding wires; the tenth silicon carbide MOSFET is disposed on the eighth lead frame, the eleventh silicon carbide MOSFET is disposed on the ninth lead frame, and the twelfth silicon carbide MOSFET is disposed on the tenth lead frame; the seventh, eighth, and ninth silicon carbide MOSFETs are disposed on the eleventh lead frame; wherein:

[0053] The eighth, ninth, and tenth lead frame sets are tripod-shaped frames, wherein one end of the tripod-shaped frame is provided with a platform for welding power devices, and the middle of the tripod-shaped frame sinks to the bottom.

[0054] The eleventh setting is a mountain-shaped lead frame, wherein the mountain-shaped frame has three protruding platforms for welding power devices on the bottom edge, and each platform corresponds to a silicon carbide MOS transistor.

[0055] in:

[0056] The seventh setting is the pin configuration relative to the third silicon carbide MOS transistor;

[0057] The platform of the eighth lead frame is positioned relative to the pin of the tenth silicon carbide MOS transistor, and the other end of the eighth lead frame is positioned between the two platforms of the eleventh lead frame where the seventh silicon carbide MOS transistor and the eighth silicon carbide MOS transistor are located.

[0058] The platform of the ninth lead frame is positioned relative to the pin of the eleventh silicon carbide MOS transistor, and the other end of the ninth lead frame is positioned between the two platforms of the eleventh lead frame containing the eighth silicon carbide MOS transistor and the ninth silicon carbide MOS transistor.

[0059] The platform of the tenth lead frame is positioned relative to the pin corresponding to the eleventh silicon carbide MOS transistor, and the other end of the ninth lead frame is positioned relative to the platform of the ninth silicon carbide MOS transistor located in the eleventh lead frame.

[0060] in:

[0061] The first lead frame is connected to the anode electrode of the fourth silicon carbide diode via a bonding wire; the second lead frame is connected to the anode electrode of the fifth silicon carbide diode via a bonding wire; and the sixth lead frame is connected to the anode electrode of the sixth silicon carbide diode via a bonding wire.

[0062] The eighth lead frame is connected to the source electrode of the seventh silicon carbide MOS transistor via a bonding wire and led out to the corresponding pin;

[0063] The ninth configuration provides a lead frame that is connected to the source electrode of the eighth silicon carbide MOS transistor via a bonding wire and leads out to the corresponding pin;

[0064] The tenth lead frame is connected to the source electrode of the ninth silicon carbide MOS transistor via a bonding wire and led out to the corresponding pin.

[0065] Optionally, the connecting lead frame includes six first connecting lead frames, three second connecting lead frames, one third connecting lead frame, six fourth connecting lead frames, and three fifth connecting lead frames; wherein:

[0066] The first connection lead frame is connected to the gate electrode of the silicon carbide MOS transistor in the Vienna rectifier circuit via bonding wires and led out to the corresponding pin;

[0067] The second connecting lead frame is connected to the source electrodes of two silicon carbide MOS transistors in the same phase of the Vienna rectifier circuit via bonding wires, and led out to the corresponding pins. The second connecting lead frame is disposed between the lead frames of the two silicon carbide MOS transistors.

[0068] The third connecting lead frame is connected to the cathode electrodes of the first silicon carbide diode, the second silicon carbide diode, and the third silicon carbide diode respectively via bonding wires, and led out to the corresponding pins. The third connecting lead frame is disposed between the lead frame and the corresponding pin of the corresponding silicon carbide diode.

[0069] The fourth connection lead frame is connected to the gate electrode of the silicon carbide MOS transistor in the three-phase full-bridge circuit through bonding wires, and led out to the corresponding pin. The fourth connection lead frame is disposed between the lead frame of the corresponding silicon carbide MOS transistor and the corresponding pin.

[0070] The fifth connection lead frame is connected to the source electrodes of the tenth silicon carbide MOS transistor, the eleventh silicon carbide MOS transistor, and the twelfth silicon carbide MOS transistor one by one via bonding wires, and led out to the corresponding pins. The fifth connection lead frame is disposed between the lead frame of the corresponding silicon carbide MOS transistor and the corresponding pin.

[0071] Optionally, the liner is a ceramic liner.

[0072] This utility model proposes a power module, which includes a substrate and a power circuit disposed on the substrate. The power circuit includes a Vienna rectifier circuit and a three-phase full-bridge circuit, with the output terminal of the Vienna rectifier circuit connected to the input terminal of the three-phase full-bridge circuit. The power devices in the Vienna rectifier circuit and the three-phase full-bridge circuit are composed of several functionally corresponding power chips, which are silicon carbide power chips. By using a Vienna rectifier circuit, the power factor of the power module can be improved. Simultaneously, by using several power chips, the output current of the power module can be increased, thereby increasing the output power. Furthermore, by using silicon carbide-based chips instead of existing silicon-based chips, the chip size can be reduced, thus avoiding an increase in the size of the power module while setting higher output power. Attached Figure Description

[0073] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with the present invention and, together with the description, serve to explain the principles of the present invention.

[0074] To more clearly illustrate the technical solutions in the embodiments of this utility model or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, for those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0075] One or more embodiments are illustrated by way of example with reference numerals in the accompanying drawings. These illustrations do not constitute a limitation on the embodiments. Elements with the same reference numerals in the drawings are denoted as similar elements. Unless otherwise stated, the figures in the drawings are not to be limited by scale.

[0076] Figure 1 This is a schematic diagram of the structure of a power module according to an embodiment of the present invention;

[0077] Figure 2 This is a circuit structure diagram of the power circuit in the power module of this utility model;

[0078] Figure 3 This is a pin diagram illustrating the structure of another embodiment of the power module of this utility model;

[0079] Figure 4 This is a pin diagram of the power module of this utility model;

[0080] Figure 5 This is a schematic diagram of the bonding wire lead-out in the power module of this utility model;

[0081] Figure 6 This is a schematic diagram of the lead frame of the power module of this utility model;

[0082] Figure 7 This is a schematic diagram of the power module of this utility model.

[0083] Explanation of icon numbers:

[0084]

[0085] Detailed Implementation

[0086] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0087] The following disclosure provides numerous different embodiments or examples for implementing various structures of the present invention. To simplify the disclosure, specific examples of components and arrangements are described below. These are merely examples and are not intended to limit the scope of the invention. Furthermore, reference numerals and / or letters may be repeated in different examples. Such repetition is for simplification and clarity and does not in itself indicate a relationship between the various embodiments and / or arrangements discussed.

[0088] It should be understood that the specific embodiments described herein are merely illustrative of the present invention and are not intended to limit the present invention. To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present application, and not all of them. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of this application.

[0089] This utility model provides a power module, referring to... Figure 1 , Figure 1 This is a schematic diagram of the structure of a power module according to an embodiment of the present invention; the power module includes a substrate 100 and a power circuit 200 disposed on the substrate 100, the power circuit 200 including a Vienna rectifier circuit 210 and a three-phase full-bridge circuit 220, the output terminal of the Vienna rectifier circuit 210 being connected to the input terminal of the three-phase full-bridge circuit 220; wherein:

[0090] The power devices in the Vienna rectifier circuit 210 and the three-phase full-bridge circuit 220 are composed of several functionally corresponding power chips 230, and the power chips 230 are silicon carbide power chips 230.

[0091] The Vienna rectifier circuit 210 is used to rectify the three-phase AC power input to the power module to output DC power to the three-phase full-bridge circuit 220, which is used to drive the three-phase motor PMSM.

[0092] Understandably, compared to existing power conversion circuits, power modules using Vienna rectifiers have a higher power factor and lower total harmonic distortion, thus significantly improving power performance.

[0093] It is understood that the power chip 230 in the Vienna rectifier circuit 210 and the three-phase full-bridge circuit 220 includes, but is not limited to, diodes, MOSFETs, and IGBTs. Specifically, the diode can be an SBD (Schottky barrier diode).

[0094] Compared to silicon-based (Si) chips, silicon carbide (SiC) chips have the advantage of smaller size, as well as advantages such as high bandgap, high thermal conductivity, low on-resistance, low switching loss, high switching speed, low reverse recovery loss, high voltage resistance, high temperature resistance, excellent heat dissipation, and high reliability.

[0095] At the same output power, silicon carbide-based chips have a smaller size. Therefore, at the same size, silicon carbide-based chips can output higher power. Thus, in this embodiment, the effect of increasing output power while keeping the module size unchanged is achieved.

[0096] In this embodiment, the power devices are configured by connecting several corresponding power chips 230 in parallel, enabling the multiple power chips 230 to share current in parallel, thereby improving the current rating of the power module and meeting the application scenarios of the entire power range. Specifically, if the power device is a silicon carbide MOSFET, two silicon carbide MOSFET chips can be connected in parallel, that is, short-circuiting the gate, source, and drain of two silicon carbide MOSFET chips to form a single silicon carbide MOSFET. Similarly, if the power device is a silicon carbide diode, two silicon carbide diode chips can be connected in parallel, that is, short-circuiting the anode and cathode of two silicon carbide diode chips to form a single silicon carbide diode. The above is only for illustrative purposes; in specific applications, parallel connection between power chips 230 is achieved by short-circuiting the same electrodes, and the number of power chips 230 connected in parallel can be set according to actual needs.

[0097] This embodiment improves the power factor of the power module by using a Vienna rectifier circuit 210, and increases the output current of the power module by using several power chips 230, thereby increasing the output power. Furthermore, it uses silicon carbide-based chips to replace existing silicon-based chips, which reduces the chip size and avoids increasing the size of the power module while setting higher output power.

[0098] Furthermore, the power module also includes a lead frame and several pins P; the power devices of the Vienna rectifier circuit 210 include a first silicon carbide diode D1, a second silicon carbide diode D2, a third silicon carbide diode D3, a fourth silicon carbide diode D4, a fifth silicon carbide diode D5, and a sixth silicon carbide diode D6 forming a three-phase rectifier circuit, and a first silicon carbide MOSFET S1, a second silicon carbide MOSFET S2, a third silicon carbide MOSFET S3, a fourth silicon carbide MOSFET S4, a fifth silicon carbide MOSFET S5, and a sixth silicon carbide MOSFET S6 forming a bidirectional switching circuit; the power devices of the three-phase full-bridge circuit 220 include a seventh silicon carbide MOSFET S7, an eighth silicon carbide MOSFET S8, a ninth silicon carbide MOSFET S9, a tenth silicon carbide MOSFET S10, an eleventh silicon carbide MOSFET S11, and a twelfth silicon carbide MOSFET S12; wherein:

[0099] The electrodes of the silicon carbide diode and the silicon carbide MOS transistor are led out to pin P through the lead frame.

[0100] Pin P is used to connect the power module to external circuits. The power module integrates multiple chips, and the chips transmit electrical signals to the external circuits through pin P.

[0101] The leadframe, as the chip carrier of integrated circuits, uses bonding materials to achieve electrical connections between chips and between chips and external leads. The specific type of bonding material can be set according to actual needs, such as gold wire, aluminum wire, or copper wire.

[0102] The Vienna rectifier circuit 210 includes a rectifier unit corresponding to three phases, a first bus capacitor, and a second bus capacitor. Each phase rectifier unit includes an inductor, two silicon carbide diodes, and two silicon carbide MOSFETs. The bus capacitors and inductors are located outside the power module, and the silicon carbide diodes and silicon carbide MOSFETs are electrically connected to the corresponding bus capacitors and inductors through pin P.

[0103] For clarity, see [link to documentation]. Figure 2 The first silicon carbide diode D1, the fourth silicon carbide diode D4, the first silicon carbide MOSFET S1, and the fourth silicon carbide MOSFET S4 are used as the U-phase rectifier unit; the second silicon carbide diode D2, the fifth silicon carbide diode D5, the second silicon carbide MOSFET S2, and the fifth silicon carbide MOSFET S5 are used as the V-phase rectifier unit; and the third silicon carbide diode D3, the sixth silicon carbide diode D6, the third silicon carbide MOSFET S3, and the sixth silicon carbide MOSFET S6 are used as the W-phase rectifier unit.

[0104] Similarly, the three-phase full-bridge circuit 220 also corresponds to three-phase bridge arms. For ease of explanation, the seventh silicon carbide MOSFET S7 and the tenth silicon carbide MOSFET S10 are taken as the U-phase bridge arm; the eighth silicon carbide MOSFET S8 and the eleventh silicon carbide MOSFET S11 are taken as the V-phase bridge arm; and the ninth silicon carbide MOSFET S9 and the twelfth silicon carbide MOSFET S12 are taken as the W-phase bridge arm.

[0105] Further, see Figure 3 Each silicon carbide diode in the Vienna rectifier circuit 210 is obtained by connecting two silicon carbide diode chips in parallel, and each silicon carbide MOSFET in the Vienna rectifier circuit 210 is obtained by connecting three silicon carbide MOSFET chips in parallel.

[0106] Each silicon carbide MOS transistor in the three-phase full-bridge circuit 220 is obtained by connecting three silicon carbide MOS transistor chips in parallel.

[0107] The highest power rating of existing power modules is 1200V 35A. In this embodiment, each silicon carbide diode in the Vienna rectifier circuit 210 is configured as two silicon carbide diode chips connected in parallel, and the silicon carbide MOSFETs in the Vienna rectifier circuit 210 and the three-phase full-bridge circuit 220 are configured as three silicon carbide MOSFET chips connected in parallel, thereby achieving a current rating of 70A and improving the output power of the power module.

[0108] Further, see Figure 1 Each silicon carbide diode in the Vienna rectifier circuit 210 is composed of a silicon carbide diode chip, and each silicon carbide MOSFET in the Vienna rectifier circuit 210 is obtained by connecting two silicon carbide MOSFET chips in parallel.

[0109] Each silicon carbide MOS transistor in the three-phase full-bridge circuit 220 is obtained by connecting two silicon carbide MOS transistor chips in parallel.

[0110] In this embodiment, the silicon carbide MOSFETs in the Vienna rectifier circuit 210 and the three-phase full-bridge circuit 220 are configured as two silicon carbide MOSFET chips connected in parallel, thereby achieving a current level of 50A and improving the output power of the power module.

[0111] It should be noted that the number of power chips 230 connected in parallel for each power module can be set based on actual needs. The more chips there are, the higher the current level can be achieved, but it will require more space and incur more costs. Therefore, the number of power chips 230 connected in parallel can be determined based on the actual application scenario.

[0112] Further, see Figure 4The anode electrodes of the first silicon carbide diode D1, the second silicon carbide diode D2, and the third silicon carbide diode D3 are led out to the first pin P through the lead frame;

[0113] The cathode electrode of the first silicon carbide diode D1, the anode electrode of the fourth silicon carbide diode D4, and the drain electrode of the first silicon carbide MOS transistor S1 are led out to the second pin P through the lead frame.

[0114] The cathode electrode of the second silicon carbide diode D2, the anode electrode of the fifth silicon carbide diode D5, and the drain electrode of the second silicon carbide MOS transistor S2 are led out to the third pin P through the lead frame.

[0115] The cathode electrode of the third silicon carbide diode D3, the anode electrode of the sixth silicon carbide diode D6, and the drain electrode of the third silicon carbide MOS transistor S3 are led out to the fourth pin P through the lead frame.

[0116] The cathode electrodes of the fourth silicon carbide diode D4, the fifth silicon carbide diode D5, and the sixth silicon carbide diode D6 are led out to the twenty-ninth pin P through the lead frame;

[0117] The drain electrode of the seventh silicon carbide MOS transistor S7, the drain electrode of the eighth silicon carbide MOS transistor S8, and the drain electrode of the ninth silicon carbide MOS transistor S9 are led out to the fifth pin P through the lead frame.

[0118] The source electrode of the seventh silicon carbide MOS transistor S7 and the drain electrode of the tenth silicon carbide MOS transistor S10 are led out to the sixth pin P through the lead frame;

[0119] The gate electrode of the seventh silicon carbide MOS transistor S7 is led out to the seventh pin P through the lead frame;

[0120] The source electrode of the eighth silicon carbide MOS transistor S8 and the drain electrode of the eleventh silicon carbide MOS transistor S11 are led out to the eighth pin P through the lead frame.

[0121] The gate electrode of the eighth silicon carbide MOS transistor S8 is led out to the ninth pin P through the lead frame;

[0122] The source electrode of the ninth silicon carbide MOS transistor S9 and the drain electrode of the twelfth silicon carbide MOS transistor S12 are led out to the tenth pin P through the lead frame.

[0123] The gate electrode of the ninth silicon carbide MOS transistor S9 is led out to the eleventh pin P through the lead frame;

[0124] The source electrode of the twelfth silicon carbide MOS transistor S12 is led out to the fourteenth pin P through the lead frame;

[0125] The gate electrode of the twelfth silicon carbide MOS transistor S12 is led out to the fifteenth pin P through the lead frame;

[0126] The source electrode of the eleventh silicon carbide MOS transistor S11 is led out to the sixteenth pin P through the lead frame;

[0127] The gate electrode of the eleventh silicon carbide MOS transistor S11 is led out to the seventeenth pin P through the lead frame;

[0128] The source electrode of the tenth silicon carbide MOS transistor S10 is led out to the eighteenth pin P through the lead frame;

[0129] The gate electrode of the tenth silicon carbide MOS transistor S10 is led out to the nineteenth pin P through the lead frame;

[0130] The gate electrode of the third silicon carbide MOS transistor S3 is led out to the twentieth pin P through the lead frame;

[0131] The source electrode of the third silicon carbide MOS transistor S3 and the source electrode of the sixth silicon carbide MOS transistor S6 are led out to the twenty-first pin P through the lead frame;

[0132] The gate electrode of the sixth silicon carbide MOS transistor S6 is led out to the twenty-second pin P through the lead frame;

[0133] The gate electrode of the fifth silicon carbide MOS transistor S5 is led out to the twenty-third pin P through the lead frame;

[0134] The source electrode of the second silicon carbide MOS transistor S2 and the source electrode of the fifth silicon carbide MOS transistor S5 are led out to the twenty-fourth pin P through the lead frame;

[0135] The gate electrode of the second silicon carbide MOS transistor S2 is led out to the twenty-fifth pin P through the lead frame;

[0136] The gate electrode of the first silicon carbide MOS transistor S1 is led out to the twenty-sixth pin P through the lead frame;

[0137] The source electrode of the first silicon carbide MOS transistor S1 and the source electrode of the fourth silicon carbide MOS transistor S4 are led out to the twenty-seventh pin P through the lead frame;

[0138] The gate electrode of the fourth silicon carbide MOS transistor S4 is led out to the twenty-eighth pin P through the lead frame;

[0139] The drain electrodes of the fourth silicon carbide MOS transistor S4, the fifth silicon carbide MOS transistor S5, and the sixth silicon carbide MOS transistor S6 are led out to the thirtieth pin P through the lead frame.

[0140] The power module also includes a thermistor, whose two ends are connected to pin 12 P and pin 13 P respectively via bonding material.

[0141] In this embodiment, the first pin P is connected to the cathode of the three-phase rectifier bridge, the second pin P is connected to the U-phase inductor, the third pin P is connected to the V-phase inductor, the fourth pin P is connected to the W-phase inductor, the fifth pin P is connected to the positive input of the three-phase full-bridge circuit 220, and the sixth pin P is connected to the U-phase output.

[0142] Pin 7 P is connected to the gate control of the seventh silicon carbide MOSFET S7, pin 8 P is connected to the V phase output, pin 9 P is connected to the gate control of the eighth silicon carbide MOSFET S8, pin 10 P is connected to the W phase output, and pin 11 P is connected to the gate control of the ninth silicon carbide MOSFET S9.

[0143] Pin 12 is connected to the first terminal of the thermistor, and pin 13 is connected to the second terminal of the thermistor.

[0144] Pin 14 (P) is connected to the source input of the 12th silicon carbide MOSFET S12; pin 15 (P) is connected to the gate control of the 12th silicon carbide MOSFET S12; pin 16 (P) is connected to the source input of the 11th silicon carbide MOSFET S11; pin 17 (P) is connected to the gate control of the 11th silicon carbide MOSFET S11; pin 18 (P) is connected to the source input of the 10th silicon carbide MOSFET S10; and pin 19 (P) is connected to the gate control of the 10th silicon carbide MOSFET S10.

[0145] Pin 20 (P) is connected to the gate control of the third silicon carbide MOSFET S3; pin 21 (P) is connected to the W phase voltage detection; pin 22 (P) is connected to the gate control of the sixth silicon carbide MOSFET S6; pin 23 (P) is connected to the gate control of the fifth silicon carbide MOSFET S5; pin 24 (P) is connected to the V phase voltage detection; pin 25 (P) is connected to the gate control of the second silicon carbide MOSFET S2; pin 26 (P) is connected to the gate control of the first silicon carbide MOSFET S1; pin 27 (P) is connected to the U phase voltage detection; and pin 28 (P) is connected to the gate control of the fourth silicon carbide MOSFET S4.

[0146] Pin 29 (P) is connected to the cathode of the three-phase rectifier bridge, and pin 30 (P) is connected to the zero point.

[0147] It is understood that the existing PIM2 package contains one pin P. This application avoids increasing the size of the power module. Therefore, the size and shape of the power module can be maintained the same as the existing PIM2 package. At the same time, in this application, the electrodes of the power circuit and the three-phase full-bridge circuit 220 are correspondingly set to one pin P, and the definition of each pin P is the same as the corresponding pin P definition in the existing PIM2. Therefore, it can be directly compatible with the customer driver of the existing power module using the PIM2 package without the need for secondary development of the customer driver.

[0148] Further, see Figure 5 The lead frame includes multiple lead frame mounting frames and multiple lead frame connecting frames; wherein:

[0149] The set lead frame is provided with a plurality of power devices, the drain of the silicon carbide MOS transistor is soldered on the set lead frame, and the set lead frame leads the set power devices to the same pin P, the same set lead frame or the electrode of the same power device;

[0150] The connection lead frame is connected to the drain or source of the silicon carbide MOS transistor via bonding wire 400, and the drain or source of the silicon carbide MOS transistor is led out to the corresponding pin P.

[0151] The power chip 230 is not installed on the connecting lead frame; it simply serves as a bridge for electrical connection.

[0152] It is understandable that the height of the pin of pin P is higher than the surface of the power chip 230. Therefore, if the electrode of the power chip 230 is directly bonded to the corresponding pin P, it will result in excessive arcing, which can easily damage the bonding solder joint and the power chip 230. To avoid this problem, this embodiment sets up a connecting lead frame, and first bonds the electrode of the power chip 230 to the connecting lead frame, and then bonds it from the connecting lead frame to the corresponding pin P. This avoids arcing damage to the bonding solder joint and the power chip 230, and ensures the reliability of the power module.

[0153] Specifically, some electrodes of the silicon carbide diode and the drain electrode of the silicon carbide MOSFET can be led out to the corresponding pin P through a soldered lead frame, and some electrodes of the silicon carbide diode, the gate electrode and the source electrode of the silicon carbide MOSFET can be led out to the corresponding pin P through a corresponding connection lead frame.

[0154] Further, see Figure 6The lead frame includes a first lead frame 211, a second lead frame 212, a third lead frame 213, a fourth lead frame 214, a fifth lead frame 215, and a sixth lead frame 216. The first lead frame 211 houses the first silicon carbide diode D1 and the first silicon carbide MOSFET S1; the second lead frame 212 houses the second silicon carbide diode D2 and the second silicon carbide MOSFET S2; the third lead frame 213 houses the fourth silicon carbide diode D4; the fourth lead frame 214 houses the fifth silicon carbide diode D5 and the sixth silicon carbide diode D6; the fifth lead frame 215 houses the fourth silicon carbide MOSFET S4, the fifth silicon carbide MOSFET S5, and the sixth silicon carbide MOSFET S6; and the sixth lead frame 216 houses the third silicon carbide diode D3.

[0155] The first lead frame 211 and the second lead frame 212 are tripod-shaped frames, wherein the two ends of the tripod-shaped frame are provided with platforms for welding power devices, and the middle of the tripod-shaped frame sinks to the bottom;

[0156] The fifth lead frame 215 is a mountain-shaped frame, wherein the mountain-shaped frame has three protruding platforms for welding power devices on the bottom edge, and each platform corresponds to a silicon carbide MOS transistor.

[0157] in:

[0158] The bottom of the first lead frame 211 is positioned opposite to the bottom of the second lead frame 212;

[0159] The third lead frame 213 is disposed on the lower side of the first lead frame 211, and the fourth lead frame 214 is disposed on the lower side of the second lead frame 212.

[0160] The third lead frame 213 and the fourth lead frame 214 are connected across the bottom of the first lead frame 211 and the second lead frame 212 by a bonding wire 400.

[0161] The first lead frame 211 is used to set one end of the first silicon carbide MOS transistor S1, and the second lead frame 212 is used to set one end of the second silicon carbide MOS transistor S2. The two platforms of the mountain-shaped frame are located between the first silicon carbide MOS transistor S1 and the second silicon carbide MOS transistor S2. The platform where the fourth silicon carbide MOS transistor S4 is located is opposite to the first silicon carbide MOS transistor S1, and the platform where the fifth silicon carbide MOS transistor S5 is located is opposite to the second silicon carbide MOS transistor S2.

[0162] The sixth lead frame 216 is disposed between the fourth lead frame 214 and the corresponding pin P.

[0163] The bottoms of the first lead frame 211 and the second lead frame 212 are positioned opposite each other. Meanwhile, the third lead frame 213 and the fourth lead frame 214 are respectively positioned at the recessed positions of the first lead frame 211 and the second lead frame 212. This results in the third lead frame 213 and the fourth lead frame 214 being separated only by the recessed bottoms of the first lead frame 211 and the second lead frame 212, which greatly shortens the length of the bonding wire 400 between the third lead frame 213 and the fourth lead frame 214, thereby reducing parasitic resistance and parasitic inductance.

[0164] The fifth setting allows the silicon carbide diodes on each platform of the lead frame 215 to be positioned opposite each other with silicon carbide diodes of the same phase. This shortens the connection distance between silicon carbide diodes of the same phase, i.e., shortens the length of the bonding wire 400 between silicon carbide diodes of the same phase, thereby reducing parasitic resistance and parasitic inductance.

[0165] The sixth setting lead frame 216 is set between the fourth setting lead frame 214 and the corresponding pin P. The fourth setting lead frame 214 can be connected to the sixth setting lead frame 216 through the bonding wire 400. The drain of the sixth silicon carbide diode D6 set on the fourth setting lead frame 214 is led out to the fourth pin P through the sixth setting lead frame 216. This can also shorten the length of the bonding wire 400 and reduce parasitic resistance and parasitic inductance.

[0166] Further, the lead frame configuration further includes a seventh lead frame 217, an eighth lead frame 218, a ninth lead frame 219, a tenth lead frame 21A, and an eleventh lead frame 21B; the third silicon carbide MOSFET S3 is disposed on the seventh lead frame 217, and the sixth lead frame 216 is connected to the seventh lead frame 217 via a bonding wire 400; the tenth silicon carbide MOSFET S10 is disposed on the eighth lead frame 218, the eleventh silicon carbide MOSFET S11 is disposed on the ninth lead frame 219, and the twelfth silicon carbide MOSFET S12 is disposed on the tenth lead frame 21A; the seventh silicon carbide MOSFET S7, the eighth silicon carbide MOSFET S8, and the ninth silicon carbide MOSFET S9 are disposed on the eleventh lead frame 21B; wherein:

[0167] The eighth lead frame 218, the ninth lead frame 219, and the tenth lead frame 21A are tripod-shaped frames, wherein one end of the tripod-shaped frame is provided with a platform for welding power devices, and the middle of the tripod-shaped frame sinks to the bottom.

[0168] The eleventh setting of the lead frame 21B is a mountain-shaped frame, wherein the mountain-shaped frame has three protruding platforms for welding power devices on the bottom edge, and each platform is corresponding to a silicon carbide MOS transistor.

[0169] in:

[0170] The seventh setting of the lead frame 217 is relative to the pin P corresponding to the third silicon carbide MOS transistor S3;

[0171] The platform of the eighth lead frame 218 is positioned relative to the pin P of the tenth silicon carbide MOS transistor S10. The other end of the eighth lead frame 218 is positioned between the two platforms of the eleventh lead frame 21B, where the seventh silicon carbide MOS transistor S7 and the eighth silicon carbide MOS transistor S8 are located.

[0172] The platform of the ninth setting lead frame 219 is set relative to the pin P corresponding to the eleventh silicon carbide MOS transistor S11. The other end of the ninth setting lead frame 219 is set between the two platforms of the eleventh setting lead frame 21B where the eighth silicon carbide MOS transistor S8 and the ninth silicon carbide MOS transistor S9 are located.

[0173] The platform of the tenth setting lead frame 21A is set relative to the pin P corresponding to the eleventh silicon carbide MOS transistor S11, and the other end of the ninth setting lead frame 219 is set relative to the platform where the ninth silicon carbide MOS transistor S9 is located in the eleventh setting lead frame 21B.

[0174] in:

[0175] The first lead frame 211 is connected to the anode electrode of the fourth silicon carbide diode D4 via a bonding wire 400, the second lead frame 212 is connected to the anode electrode of the fifth silicon carbide diode D5 via a bonding wire 400, and the sixth lead frame 216 is connected to the anode electrode of the sixth silicon carbide diode D6 via a bonding wire 400.

[0176] The eighth lead frame 218 is connected to the source electrode of the seventh silicon carbide MOS transistor S7 via a bonding wire 400 and led out to the corresponding pin P.

[0177] The ninth lead frame 219 is connected to the source electrode of the eighth silicon carbide MOS transistor S8 via a bonding wire 400 and led out to the corresponding pin P.

[0178] The tenth lead frame 21A is connected to the source electrode of the ninth silicon carbide MOS transistor S9 via a bonding wire 400 and led out to the corresponding pin P.

[0179] The platforms of the eighth lead frame 218, the ninth lead frame 219, and the tenth lead frame 21A, where silicon carbide MOSFETs are located, are all positioned close to the corresponding pin P, thereby reducing the length of the bonding wire 400 leading to pin P. Simultaneously, the ends of the silicon carbide MOSFETs not located on the eighth lead frame 218, the ninth lead frame 219, and the tenth lead frame 21A are positioned between the two platforms of the eleventh lead frame 21B, i.e., between the two protrusions of the mountain-shaped frame. This allows the source of the silicon carbide MOSFET on the mountain-shaped frame to be connected to the drain of the silicon carbide MOSFET in the same-direction bridge arm via the bonding wire 400, and then led out to the corresponding pin P. This shortens the length of the bonding wire 400, reducing parasitic resistance and parasitic inductance.

[0180] In this embodiment, the cathode electrode and part of the anode electrode of the silicon carbide diode, the drain electrode and part of the source electrode of the silicon carbide MOS transistor are led out to the corresponding pin P by a lead frame.

[0181] Specifically, the cathode electrode of the first silicon carbide diode D1 and the drain electrode of the first silicon carbide MOSFET S1 are welded to the first lead frame 211 and led out to the pin P.

[0182] The cathode electrode of the second silicon carbide diode D2 and the drain electrode of the second silicon carbide MOSFET S2 are welded to the second lead frame 212 and led out to the pin P.

[0183] The cathode electrode of the fourth silicon carbide diode D4 is soldered to the third lead frame 213 and led out to pin P.

[0184] The cathode electrodes of the fifth silicon carbide diode D5 and the sixth silicon carbide diode D6 are soldered to the third lead frame 213, and are first bonded to the third lead frame 213 and then led out to the pin P; while the anode of the fifth silicon carbide diode D5 is first bonded to the second lead frame 212 and then led out to the pin P; the anode of the sixth silicon carbide diode D6 is first bonded to the sixth lead frame 216 and then led out to the pin P.

[0185] The drain electrode of the fourth silicon carbide MOSFET S4, the drain electrode of the fifth silicon carbide MOSFET S5, and the drain electrode of the sixth silicon carbide MOSFET S6 are soldered onto the fifth lead frame 215 and led out to pin P.

[0186] The cathode electrode of the third silicon carbide diode D3 is soldered to the sixth lead frame 216 and led out from there to pin P;

[0187] The drain electrode of the third silicon carbide MOSFET S3 is soldered to the seventh setting lead frame 217. The seventh setting lead frame 217 is first bonded to the sixth setting lead frame 216 and then led out to the pin P.

[0188] The drain electrode of the tenth silicon carbide MOSFET S10 is soldered to the eighth lead frame 218 and led out to pin P.

[0189] The drain electrode of the eleventh silicon carbide MOSFET S11 is soldered to the ninth lead frame 219 and led out to pin P.

[0190] The drain electrode of the twelfth silicon carbide MOSFET S12 is soldered to the tenth lead frame 21A and led out to pin P.

[0191] The drains of the seventh silicon carbide MOSFET S7, the eighth silicon carbide MOSFET S8, and the ninth silicon carbide MOSFET S9 are soldered to the eleventh lead frame 21BB and led out to pin P.

[0192] The source of the seventh silicon carbide MOSFET S7 is first bonded to the eighth lead frame 218, and then led out to pin P;

[0193] The source of the eighth silicon carbide MOSFET S8 is first bonded to the ninth lead frame 219, and then led out to pin P;

[0194] The source of the ninth silicon carbide MOSFET S9 is first bonded to the tenth lead frame 21A, and then led out to pin P.

[0195] Furthermore, the connecting lead frame includes six first connecting lead frames 221, three second connecting lead frames 222, one third connecting lead frame 223, six fourth connecting lead frames 224, and three fifth connecting lead frames 225; wherein:

[0196] The first connecting lead frame 221 is connected to the gate electrode of the silicon carbide MOS transistor in the Vienna rectifier circuit 210 via bonding wire 400, and led out to the corresponding pin P;

[0197] The second connecting lead frame 222 is connected to the source electrodes of two silicon carbide MOS transistors in the same phase of the Vienna rectifier circuit 210 via bonding wires 400, and led out to the corresponding pin P. The second connecting lead frame 222 is disposed between the lead frames where the two silicon carbide MOS transistors are located.

[0198] The third connecting lead frame 223 is connected to the cathode electrodes of the first silicon carbide diode D1, the second silicon carbide diode D2 and the third silicon carbide diode D3 respectively through bonding wires 400, and led out to the corresponding pin P. The third connecting lead frame 223 is disposed between the lead frame where the corresponding silicon carbide diode is located and the corresponding pin P.

[0199] The fourth connection lead frame 224 is connected to the gate electrode of the silicon carbide MOS transistor in the three-phase full-bridge circuit 220 through the bonding wire 400, and led out to the corresponding pin P. The fourth connection lead frame 224 is disposed between the lead frame where the corresponding silicon carbide MOS transistor is located and the corresponding pin P.

[0200] The fifth connection lead frame 225 is connected to the source electrodes of the tenth silicon carbide MOS transistor S10, the eleventh silicon carbide MOS transistor S11, and the twelfth silicon carbide MOS transistor S12 one by one via bonding wires 400, and is led out to the corresponding pin P. The fifth connection lead frame 225 is disposed between the lead frame of the corresponding silicon carbide MOS transistor and the corresponding pin P.

[0201] Specifically, the anode electrode of part of the first silicon carbide diode D1, the source electrode and the gate electrode of the first silicon carbide MOSFET S1 are led out to the corresponding pin P through a connecting lead frame.

[0202] Specifically, the anode electrodes of the first silicon carbide diode D1 chip, the second silicon carbide diode D2 chip, and the third silicon carbide diode D3 chip are led out to pin P1 through a third connection lead frame 223;

[0203] The source electrodes of the first silicon carbide MOSFET S1 and the fourth silicon carbide MOSFET S4 are led out to pin P27 through a second connection lead frame 222; the source electrodes of the second silicon carbide MOSFET S2 and the fifth silicon carbide MOSFET S5 are led out to pin P24 through a second connection lead frame 222; the source electrodes of the third silicon carbide MOSFET S3 and the sixth silicon carbide MOSFET S6 are led out to pin P21 through a second connection lead frame 222.

[0204] The gate levels of the first to sixth silicon carbide MOSFETs S6 are led out to pins P26, 25, 20, 28, 23, and 22 respectively through the corresponding first connection lead frame 221; the gate levels of the seventh to twelfth silicon carbide MOSFETs S12 are led out to pins P7, 9, 11, 19, 17, and 15 respectively through the corresponding fourth connection lead frame 224.

[0205] The source electrodes of the tenth to twelfth silicon carbide MOSFETs S12 are led out to pins P18, 16, and 14 respectively through the corresponding fifth connection lead frame 225.

[0206] Further, the liner 100 includes a first liner 100 and a second liner 100; wherein:

[0207] The first liner 100 is provided with the first to sixth lead wire frames 211 to 216 and the third connecting lead wire frame 223;

[0208] The second liner 100 is provided with the seventh to eleventh lead wire frames 217 to 21B and the fourth to fifth connecting lead wire frames 225;

[0209] A first connecting lead frame 221 corresponding to the first silicon carbide MOSFET S1, the second silicon carbide MOSFET S2, the fourth silicon carbide MOSFET S4, the fifth silicon carbide MOSFET S5, and the sixth silicon carbide MOSFET S6 is disposed on the first substrate 100.

[0210] The first connection lead frame 221 corresponding to the third silicon carbide MOSFET S3 is disposed on the second substrate 100;

[0211] A second connecting lead frame 222 corresponding to the first silicon carbide MOSFET S1, the second silicon carbide MOSFET S2, the fourth silicon carbide MOSFET S4, and the fifth silicon carbide MOSFET S5 is disposed on the first substrate 100.

[0212] The second connecting lead frame 222 corresponding to the third silicon carbide MOSFET S3 and the sixth silicon carbide MOSFET S6 is disposed on the second substrate 100.

[0213] In this embodiment, the Vienna rectifier circuit 210 and the three-phase full-bridge circuit 220 are topologically integrated on the first substrate 100 and the second substrate 100 with equal areas. Based on this, the lead frame is arranged to achieve compatibility with the existing pin P.

[0214] Furthermore, the liner 100 is a ceramic liner 100.

[0215] In this embodiment, the liner 100 is a ceramic liner 100, which has a three-layer structure: the upper and lower layers are copper-clad layers, and the middle layer is a ceramic layer. Specifically, the ceramic liner 100 can be an AMB (Active Metal Brazing) ceramic liner 100 or a DBC (Direct Bond Copper) ceramic liner 100.

[0216] Further, see Figure 7 The power module further includes a package side frame 500, a substrate 600, and a package cover plate 700; wherein:

[0217] The side of the package side frame 500 is provided with pin P, the substrate 600 is disposed inside the package side frame 500, the liner 100 is disposed on the substrate 600, and the package cover 700 is disposed on the power circuit 200.

[0218] The package side frame 500 is used to set the pin P; the substrate 600 is used to support the substrate 100 and the power circuit 200 on the substrate 100; the package side frame 500, the substrate 600 and the package cover 700 together form the package space, and the substrate 100 and the power circuit 200 are disposed in the package space; a rivet ring 800 is also provided on the package side frame 500.

[0219] After the bonding process is completed, the various parts are assembled, and the assembled power module is potted to isolate moisture and improve the reliability of the power module.

[0220] In this utility model, the terms "first", "second", "third", "fourth" and "fifth" are used for descriptive purposes only and should not be construed as indicating or implying relative importance. Those skilled in the art can understand the specific meaning of the above terms in this utility model according to the specific circumstances.

[0221] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the present invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0222] Although embodiments of the present invention have been shown and described above, the scope of protection of the present invention is not limited thereto. It is understood that the above embodiments are exemplary and should not be construed as limiting the present invention. Those skilled in the art can make changes, modifications, and substitutions to the above embodiments within the scope of the present invention, and such changes, modifications, and substitutions should all be covered within the protection scope of the present invention. Therefore, the protection scope of the present invention should be determined by the scope of the claims.

Claims

1. A power module, characterized in that, The power module includes a substrate and a power circuit disposed on the substrate. The power circuit includes a Vienna rectifier circuit and a three-phase full-bridge circuit, and the output terminal of the Vienna rectifier circuit is connected to the input terminal of the three-phase full-bridge circuit; wherein: The power devices in the Vienna rectifier circuit and the three-phase full-bridge circuit are composed of several power chips with corresponding functions, and the power chips are silicon carbide power chips.

2. The power module as described in claim 1, characterized in that, The power module also includes a lead frame and several pins; the power devices of the Vienna rectifier circuit include a first silicon carbide diode, a second silicon carbide diode, a third silicon carbide diode, a fourth silicon carbide diode, a fifth silicon carbide diode, and a sixth silicon carbide diode constituting the three-phase rectifier circuit, and a first silicon carbide MOSFET, a second silicon carbide MOSFET, a third silicon carbide MOSFET, a fourth silicon carbide MOSFET, a fifth silicon carbide MOSFET, and a sixth silicon carbide MOSFET constituting the bidirectional switching circuit; the power devices of the three-phase full-bridge circuit include a seventh silicon carbide MOSFET, an eighth silicon carbide MOSFET, a ninth silicon carbide MOSFET, a tenth silicon carbide MOSFET, an eleventh silicon carbide MOSFET, and a twelfth silicon carbide MOSFET; wherein: The electrodes of the silicon carbide diode and the silicon carbide MOS transistor are led out to the pins through the lead frame.

3. The power module as described in claim 2, characterized in that, Each silicon carbide diode in the Vienna rectifier circuit is formed by two silicon carbide diode chips connected in parallel, and each silicon carbide MOSFET in the Vienna rectifier circuit is formed by three silicon carbide MOSFET chips connected in parallel. Each silicon carbide MOSFET in the three-phase full-bridge circuit is obtained by connecting three silicon carbide MOSFET chips in parallel.

4. The power module as described in claim 2, characterized in that, Each silicon carbide diode in the Vienna rectifier circuit is composed of a silicon carbide diode chip, and each silicon carbide MOSFET in the Vienna rectifier circuit is obtained by connecting two silicon carbide MOSFET chips in parallel. Each silicon carbide MOSFET in the three-phase full-bridge circuit is formed by two silicon carbide MOSFET chips connected in parallel.

5. The power module as described in claim 2, characterized in that, The anode electrodes of the first silicon carbide diode, the second silicon carbide diode, and the third silicon carbide diode are led out to the first pin through the lead frame; The cathode electrode of the first silicon carbide diode, the anode electrode of the fourth silicon carbide diode, and the drain electrode of the first silicon carbide MOS transistor are led out to the second pin through the lead frame; The cathode electrode of the second silicon carbide diode, the anode electrode of the fifth silicon carbide diode, and the drain electrode of the second silicon carbide MOS transistor are led out to the third pin through the lead frame; The cathode electrode of the third silicon carbide diode, the anode electrode of the sixth silicon carbide diode, and the drain electrode of the third silicon carbide MOS transistor are led out to the fourth pin through the lead frame; The cathode electrodes of the fourth, fifth, and sixth silicon carbide diodes are led out to the twenty-ninth pin through the lead frame; The drain electrode of the seventh silicon carbide MOS transistor, the drain electrode of the eighth silicon carbide MOS transistor, and the drain electrode of the ninth silicon carbide MOS transistor are led out to the fifth pin through the lead frame; The source electrode of the seventh silicon carbide MOS transistor and the drain electrode of the tenth silicon carbide MOS transistor are led out to the sixth pin through the lead frame; The gate electrode of the seventh silicon carbide MOS transistor is led out to the seventh pin through the lead frame; The source electrode of the eighth silicon carbide MOS transistor and the drain electrode of the eleventh silicon carbide MOS transistor are led out to the eighth pin through the lead frame; The gate electrode of the eighth silicon carbide MOS transistor is led out to the ninth pin through the lead frame; The source electrode of the ninth silicon carbide MOS transistor and the drain electrode of the twelfth silicon carbide MOS transistor are led out to the tenth pin through the lead frame; The gate electrode of the ninth silicon carbide MOS transistor is led out to the eleventh pin through the lead frame; The source electrode of the twelfth silicon carbide MOS transistor is led out to the fourteenth pin through the lead frame; The gate electrode of the twelfth silicon carbide MOS transistor is led out to the fifteenth pin through the lead frame; The source electrode of the eleventh silicon carbide MOS transistor is led out to the sixteenth pin through the lead frame; The gate electrode of the eleventh silicon carbide MOS transistor is led out to the seventeenth pin through the lead frame; The source electrode of the tenth silicon carbide MOS transistor is led out to the eighteenth pin through the lead frame; The gate electrode of the tenth silicon carbide MOS transistor is led out to the nineteenth pin through the lead frame; The gate electrode of the third silicon carbide MOS transistor is led out to the twentieth pin through the lead frame; The source electrode of the third silicon carbide MOS transistor and the source electrode of the sixth silicon carbide MOS transistor are led out to the twenty-first pin through the lead frame; The gate electrode of the sixth silicon carbide MOS transistor is led out to the twenty-second pin through the lead frame; The gate electrode of the fifth silicon carbide MOS transistor is led out to the twenty-third pin through the lead frame; The source electrode of the second silicon carbide MOS transistor and the source electrode of the fifth silicon carbide MOS transistor are led out to the twenty-fourth pin through the lead frame; The gate electrode of the second silicon carbide MOS transistor is led out to the twenty-fifth pin through the lead frame; The gate electrode of the first silicon carbide MOS transistor is led out to the twenty-sixth pin through the lead frame; The source electrode of the first silicon carbide MOS transistor and the source electrode of the fourth silicon carbide MOS transistor are led out to the twenty-seventh pin through the lead frame; The gate electrode of the fourth silicon carbide MOS transistor is led out to the twenty-eighth pin through the lead frame; The drain electrodes of the fourth, fifth, and sixth silicon carbide MOS transistors are led out to the thirtieth pin through the lead frame.

6. The power module as described in claim 2, characterized in that, The lead frame includes multiple lead frame mounting frames and multiple lead connection frames; wherein: The set lead frame is provided with a plurality of power devices, the drain of the silicon carbide MOS transistor is soldered on the set lead frame, and the set lead frame leads the set power devices to the same pin, the same set lead frame or the electrode of the same power device; The connection lead frame is connected to the drain or source of the silicon carbide MOS transistor via bonding wires, and the drain or source of the silicon carbide MOS transistor is led out to the corresponding pin.

7. The power module as described in claim 6, characterized in that, The lead frame includes a first lead frame, a second lead frame, a third lead frame, a fourth lead frame, a fifth lead frame, and a sixth lead frame; the first lead frame has a first silicon carbide diode and a first silicon carbide MOSFET disposed thereon; the second lead frame has a second silicon carbide diode and a second silicon carbide MOSFET disposed thereon; the third lead frame has a fourth silicon carbide diode disposed thereon; the fourth lead frame has a fifth silicon carbide diode and a sixth silicon carbide diode disposed thereon; the fifth lead frame has a fourth silicon carbide MOSFET, a fifth silicon carbide MOSFET, and a sixth silicon carbide MOSFET disposed thereon; and the sixth lead frame has a third silicon carbide diode disposed thereon; wherein: The first lead frame and the second lead frame are tripod-shaped frames, wherein the tripod-shaped frames have platforms at both ends for welding power devices, and the middle of the tripod-shaped frames sinks to the bottom; The fifth setting of the lead frame is a mountain-shaped frame, wherein the mountain-shaped frame has three protruding platforms for welding power devices on the bottom edge, and each platform is corresponding to a silicon carbide MOSFET. in: The bottom of the first lead frame is positioned opposite to the bottom of the second lead frame; The third lead frame is disposed on the lower side of the first lead frame, and the fourth lead frame is disposed on the lower side of the second lead frame. The third and fourth lead frames are connected by bonding wires across the bottom of the first and second lead frames. The first lead frame sets one end of the first silicon carbide MOS transistor and the second lead frame sets one end of the second silicon carbide MOS transistor, which are located between the two platforms of the mountain-shaped frame. The platform where the fourth silicon carbide MOS transistor is located is opposite to the first silicon carbide MOS transistor, and the platform where the fifth silicon carbide MOS transistor is located is opposite to the second silicon carbide MOS transistor. The sixth lead frame is disposed between the fourth lead frame and the corresponding pin.

8. The power module as described in claim 7, characterized in that, The lead frame further includes a seventh lead frame, an eighth lead frame, a ninth lead frame, a tenth lead frame, and an eleventh lead frame; the third silicon carbide MOSFET is disposed on the seventh lead frame, and the sixth lead frame is connected to the seventh lead frame via bonding wires; the tenth silicon carbide MOSFET is disposed on the eighth lead frame, the eleventh silicon carbide MOSFET is disposed on the ninth lead frame, and the twelfth silicon carbide MOSFET is disposed on the tenth lead frame; the seventh, eighth, and ninth silicon carbide MOSFETs are disposed on the eleventh lead frame; wherein: The eighth, ninth, and tenth lead frame sets are tripod-shaped frames, wherein one end of the tripod-shaped frame is provided with a platform for welding power devices, and the middle of the tripod-shaped frame sinks to the bottom. The eleventh setting is a mountain-shaped lead frame, wherein the mountain-shaped frame has three protruding platforms for welding power devices on the bottom edge, and each platform corresponds to a silicon carbide MOS transistor. in: The seventh setting is the pin configuration relative to the third silicon carbide MOS transistor; The platform of the eighth lead frame is positioned relative to the pin of the tenth silicon carbide MOS transistor, and the other end of the eighth lead frame is positioned between the two platforms of the eleventh lead frame where the seventh silicon carbide MOS transistor and the eighth silicon carbide MOS transistor are located. The platform of the ninth lead frame is positioned relative to the pin of the eleventh silicon carbide MOS transistor, and the other end of the ninth lead frame is positioned between the two platforms of the eleventh lead frame containing the eighth silicon carbide MOS transistor and the ninth silicon carbide MOS transistor. The platform of the tenth lead frame is positioned relative to the pin corresponding to the eleventh silicon carbide MOS transistor, and the other end of the ninth lead frame is positioned relative to the platform of the ninth silicon carbide MOS transistor located in the eleventh lead frame. in: The first lead frame is connected to the anode electrode of the fourth silicon carbide diode via a bonding wire; the second lead frame is connected to the anode electrode of the fifth silicon carbide diode via a bonding wire; and the sixth lead frame is connected to the anode electrode of the sixth silicon carbide diode via a bonding wire. The eighth lead frame is connected to the source electrode of the seventh silicon carbide MOS transistor via a bonding wire and led out to the corresponding pin; The ninth configuration provides a lead frame that is connected to the source electrode of the eighth silicon carbide MOS transistor via a bonding wire and leads out to the corresponding pin; The tenth lead frame is connected to the source electrode of the ninth silicon carbide MOS transistor via a bonding wire and led out to the corresponding pin.

9. The power module as described in claim 6, characterized in that, The connecting lead frame includes six first connecting lead frames, three second connecting lead frames, one third connecting lead frame, six fourth connecting lead frames, and three fifth connecting lead frames; wherein: The first connection lead frame is connected to the gate electrode of the silicon carbide MOS transistor in the Vienna rectifier circuit via bonding wires and led out to the corresponding pin; The second connecting lead frame is connected to the source electrodes of two silicon carbide MOS transistors in the same phase of the Vienna rectifier circuit via bonding wires, and led out to the corresponding pins. The second connecting lead frame is disposed between the lead frames of the two silicon carbide MOS transistors. The third connecting lead frame is connected to the cathode electrodes of the first silicon carbide diode, the second silicon carbide diode, and the third silicon carbide diode respectively via bonding wires, and led out to the corresponding pins. The third connecting lead frame is disposed between the lead frame and the corresponding pin of the corresponding silicon carbide diode. The fourth connection lead frame is connected to the gate electrode of the silicon carbide MOS transistor in the three-phase full-bridge circuit through bonding wires, and led out to the corresponding pin. The fourth connection lead frame is disposed between the lead frame of the corresponding silicon carbide MOS transistor and the corresponding pin. The fifth connection lead frame is connected to the source electrodes of the tenth silicon carbide MOS transistor, the eleventh silicon carbide MOS transistor, and the twelfth silicon carbide MOS transistor one by one via bonding wires, and led out to the corresponding pins. The fifth connection lead frame is disposed between the lead frame of the corresponding silicon carbide MOS transistor and the corresponding pin.

10. The power module as described in claim 1, characterized in that, The liner is a ceramic liner.

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