Packaging structure
By performing single-sided encapsulation on the substrate and utilizing the stress distribution of the thermosetting resin dielectric layer, the wiring density and warpage problems in existing packaging structures are solved, achieving higher wiring density and cost reduction.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- VANCHIP TIANJIN TECH
- Filing Date
- 2025-05-28
- Publication Date
- 2026-05-08
AI Technical Summary
In existing fan-out wafer-level packaging structures, the wiring density is limited, the substrate support is poor, and it is prone to warping, resulting in high packaging costs.
The method employs single-sided encapsulation on a substrate, utilizes a thermosetting resin dielectric layer to redistribute stress during thermosetting, adds a dielectric layer to increase wiring density, and achieves multi-layer electrical connection through conductive pillars.
It increases wiring density, reduces packaging difficulty and cost, and reduces the risk of warpage.
Smart Images
Figure CN224218811U_ABST
Abstract
Description
Technical Field
[0001] This utility model relates to the field of semiconductor technology, and in particular to a packaging structure. Background Technology
[0002] With the rapid development of 5G / 6G communication, fan-out wafer-level package (FOWLP) packaging structures are widely used in the semiconductor industry. Generally, a single chip is cut from a wafer and then flip-packaged onto a carrier wafer. Its main advantages are high-density integration, small package size, superior product performance, and high signal transmission frequency. Fan-out technology primarily enables multi-pin output and smaller pin spacing. Conventional double-sided or fan-out packaging structures mainly form the packaging structure on both sides of the same substrate. Because the same substrate is used for molding, the substrate wiring density is limited, making it impossible to achieve higher wiring density requirements. Furthermore, because packaging is done on both sides of a single substrate, the substrate support is poor, and processing one side before processing the other can easily lead to warping issues. Utility Model Content
[0003] The purpose of this invention is to provide a packaging structure that improves wiring density, reduces packaging processes, increases the number of chips stacked, and ultimately reduces the risk of warpage and packaging costs.
[0004] To solve the above-mentioned technical problems, this utility model provides a packaging structure, including:
[0005] The first substrate has a first surface and a second surface disposed opposite to each other;
[0006] A first metal layer is disposed on the first surface of the first substrate;
[0007] A first encapsulation layer is disposed on the first metal layer and includes at least one first chip embedded therein, wherein the first chip and the first metal layer have a first gap.
[0008] A second metal layer is disposed on the first packaging layer and has a second gap between it and the first chip;
[0009] The first dielectric layer is disposed on the second metal layer.
[0010] Optionally, the packaging structure may further include:
[0011] A third metal layer is disposed on the second surface of the first substrate;
[0012] The second dielectric layer is disposed on the third metal layer.
[0013] Optionally, the packaging structure may further include:
[0014] A fourth metal layer is disposed on the first dielectric layer;
[0015] The second encapsulation layer is located on the fourth metal layer.
[0016] Optionally, the packaging structure may further include:
[0017] At least one first conductive post is located within the first substrate and passes through the first substrate to directly contact the first metal layer and / or the third metal layer on the first substrate.
[0018] Optionally, the packaging structure may further include:
[0019] At least one second conductive post is located within the first encapsulation layer on at least one side of the first chip and passes through the first encapsulation layer to directly contact the first metal layer and the second metal layer.
[0020] Optionally, the packaging structure may further include:
[0021] At least one solder ball is located within the first package layer on at least one side of the first chip and passes through the first package layer to directly contact the first metal layer and the second metal layer.
[0022] Optionally, the packaging structure may further include:
[0023] At least one third conductive post is disposed in the first dielectric layer and / or the second dielectric layer, and passes through the first dielectric layer and / or the second dielectric layer to directly contact the second metal layer, the fourth metal layer and / or the third metal layer.
[0024] Optionally, the packaging structure may further include:
[0025] Multiple bumps or multiple solder joints are located in the first gap or the second gap to mount the first chip within the first encapsulation layer.
[0026] The material of the first dielectric layer and / or the second dielectric layer includes a thermosetting resin.
[0027] Optionally, the packaging structure may further include:
[0028] The second chip is disposed within the second packaging layer.
[0029] As described above, in the packaging structure provided by this utility model, single-sided packaging can be performed on the first substrate first. For example, a first packaging layer with a first chip disposed inside can be formed on the first surface of the first substrate. Then, at least one dielectric layer, such as a first dielectric layer, is laminated on the first packaging layer. An unexpected effect is that since the first chip has been pre-mounted, pressure can be applied to the first packaging layer during the lamination of the first dielectric layer, which prevents the first chip from being damaged and reduces packaging difficulty and cost. Furthermore, while the first dielectric layer is laminated on the first packaging layer, a second dielectric layer can be laminated on the second surface of the first substrate (the surface where the first packaging layer is not formed). An unexpected effect is that by utilizing the characteristic that the first and second dielectric layers, which are made of thermosetting resin, can be cured under uniform pressure, stress redistribution can be achieved, i.e., stress can be offset, thereby improving warpage. Secondly, the addition of a first dielectric layer or a second dielectric layer can also be used to increase wiring density. Attached Figure Description
[0030] The accompanying drawings are provided to further illustrate the present application and form part of the specification. They are used together with the following detailed description to explain the present application, but do not constitute a limitation thereof. In the drawings:
[0031] Figure 1 This is a cross-sectional schematic diagram of an example of the packaging structure in the first embodiment of this utility model.
[0032] Figure 2 This is a schematic diagram illustrating an evolution of the first chip packaging method in the first embodiment of this utility model.
[0033] Figure 3 This is a schematic diagram illustrating another evolution of the first chip packaging method in the first embodiment of this utility model.
[0034] Figure 4 This is a schematic diagram illustrating an evolution of the shape and structure of the first conductive pillar in the first embodiment of this utility model.
[0035] Figure 5 This is a schematic diagram illustrating another evolution of the shape and structure of the first conductive pillar in the first embodiment of this utility model.
[0036] Figure 6 This is a cross-sectional schematic diagram of an example of the packaging structure in the second embodiment of the present invention.
[0037] Figures 7-11 In response to Figure 1 The diagram shows the structural schematic corresponding to the steps of the packaging method of the packaging structure provided in the first embodiment of this utility model.
[0038] The reference numerals in the attached figures are explained as follows:
[0039] 100 - First substrate, 100a - First surface, 100b - Second surface, 111 - First metal layer, 112 - First encapsulation layer, 113 - First chip, 113a - Bump, 113b - Solder joint, 114 - Second metal layer, 115 - First dielectric layer, 116 - Fourth metal layer, 117 - Second encapsulation layer, 118 - First conductive pillar, 119 - Second conductive pillar, 119a - Solder ball, 120 - Third conductive pillar, 131 - Third metal layer, 132 - Second dielectric layer, 133 - Fifth metal layer.
[0040] In the accompanying drawings, the same parts are referred to by the same reference numerals, and the drawings are not drawn to scale. Detailed Implementation
[0041] The packaging structure proposed by this utility model will be further described in detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of this utility model will become clearer from the following description. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of this utility model. Many specific details are set forth in the following description to provide a full understanding of this utility model; however, this utility model can also be implemented in other ways different from those described herein, and therefore this utility model is not limited to the specific embodiments disclosed below.
[0042] It should be noted that the accompanying drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the purpose of illustrating the embodiments of this utility model. It is understood that the meanings of "on," "above," and "above" in this utility model should be interpreted in the broadest sense, so that "on" not only means "on" something without any intervening features or layers (i.e., directly on something), but also includes the meaning of "on" something with intervening features or layers. In the embodiments of this utility model, the terms "first," "second," etc., are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. Furthermore, the technical solutions described in the embodiments of this utility model can be arbitrarily combined without conflict.
[0043] Please refer to Figure 1The illustration shows a cross-sectional view of an example of the packaging structure in the first embodiment of this utility model. The packaging structure of this utility model can be used to prepare a fan-out double-sided packaging structure. Without departing from the spirit of this utility model, this utility model can also be applied to other types of packaging structures or double-sided packaging structures, such as PLP (Panel Level Packaging) packaging structures. Furthermore, features in the embodiments of this utility model can be combined with each other without conflict.
[0044] like Figure 1 As shown, the packaging structure in the first embodiment of this utility model may include: a first substrate 100, a first metal layer 111, a first encapsulation layer 112, a first chip 113, a second metal layer 114, a first dielectric layer 115, a fourth metal layer 116, a second encapsulation layer 117, a third metal layer 131, a second dielectric layer 132, and a fifth metal layer 133. The first substrate 100 may be formed of or include at least one of insulating materials. For example, the first substrate 100 may include photosensitive epoxy resin or PP fiberglass cloth. More specifically, the first substrate 100 may include a photoimaging dielectric (PID), but is not limited thereto. The first substrate 100 may include two back-to-back surfaces, such as a first surface 100a facing the first dielectric layer 115 and a second surface 100b facing the second dielectric layer 132, but is not limited thereto. The first metal layer 111 covers the first surface 100a of the first substrate 100, while the third metal layer 131 covers the second surface 100b of the first substrate 100, forming a separable substrate structure. In one embodiment, the material of the first metal layer 111 and the third metal layer 131 may be copper, and the thickness is preferably 15μm to 35μm (more preferably 20μm or 30μm), but not limited thereto; and at least one first conductive post 118 is also provided in the first substrate 100, so that the first metal layer 111 and the third metal layer 131 covering the first surface 100a and the second surface 100b of the first substrate 100 are respectively connected through the ends of the first conductive post 118, thereby realizing the electrical connection (physical contact) between multiple film layers in the packaging structure. Preferably, the number of the first conductive posts 118 provided in the first substrate 100 can be determined based on the number of chips packaged in the packaging structure, such as the first chip 113, thereby realizing the partitioning and shielding of multiple chips. For example, in the first embodiment of this utility model... Figure 1This example only illustrates a first chip 113, and thus only two first conductive pillars 118 are provided within the first substrate 100, but is not limited thereto. Exemplarily, the first conductive pillar 118 is an elongated strip extending along a direction perpendicular to the first surface 100a of the first substrate 100 (hereinafter referred to as the vertical direction). In other embodiments, the shape of the first conductive pillar 118 may also be other irregular shapes (not shown), such as trapezoids, and is not limited thereto.
[0045] The first encapsulation layer 112 covers the first metal layer 111, and at least one first chip 113 is embedded inside the first encapsulation layer 112; such as Figure 1 As shown, the first chip 113 can be mounted within the first encapsulation layer 112 with multiple bumps 113a facing upwards, and the bottoms of the multiple bumps 113a are in direct contact with the first metal layer 111; in other optional examples, such as Figure 2 As shown, the first chip 113 can also be flip-mounted within the first packaging layer 112 with the front side facing down via multiple bumps 113a, or, as... Figure 3 As shown, the chip 120 is encapsulated within the first encapsulation layer 112 with multiple solder joints 113b facing upwards or downwards. In one embodiment, the material of the first encapsulation layer 112 can be a molding compound, such as a thermoplastic molding compound containing inorganic fillers, but is not limited thereto. The first chip 120 can also be a WB chip or an FC chip, but is not limited thereto. A second metal layer 114 covers the first encapsulation layer 112. Due to the height of the bumps 113a or the solder joints 113b, there is a gap between the front or back of the first chip 113 and the first metal layer 111 on the first substrate 100 or the second metal layer 114 on the first encapsulation layer 112, i.e., a first gap with the first metal layer 111, or a second gap with the second metal layer 114. The material of the second metal layer 114 can be the same as the material of the first metal layer 111 and / or the third metal layer 131, such as copper, to serve as a carrier connecting the first encapsulation layer 112 and the first dielectric layer 115, but is not limited thereto.
[0046] Furthermore, at least one conductive post, such as a second conductive post 119, may also be provided within the first encapsulation layer 112. The second conductive post 119 may be located within the first encapsulation layer 112 on different sides of the first chip 113, and its end may be in direct contact with the first metal layer 111 and the second metal layer 114 located on the two side surfaces of the first encapsulation layer 112, respectively. Figures 1 to 3 As shown, in the first embodiment of this utility model, the second conductive post 119 can be a long strip extending in the vertical direction. In other optional examples, the second conductive post 119 can also be other irregular shapes, such as... Figure 4 The irregular polygonal closed structure shown consists of an inverted trapezoidal portion near the second metal layer 114 and a rectangular (similar to the strip shape) portion near the first metal layer 111. It is sufficient that the upper and lower ends (or end faces) of the irregularly shaped second conductive post 119 are in contact with the second metal layer 114 and the first metal layer 111 respectively.
[0047] Furthermore, in other embodiments, the first encapsulation layer 112 may not necessarily contain conductive pillars to achieve physical connections between multiple film layers; instead, it may contain multiple solder balls, for example... Figure 5 The solder ball 119a is shown. Since the solder ball 119a has the same function as the second conductive post 119, the setting position of the solder ball 119a is also the same as the setting position of the second conductive post 119. For example, it is located in the first packaging layer 112 on at least one side of the first chip 113, and passes through the first packaging layer 112 to directly contact the first metal layer 111 and the second metal layer 114.
[0048] Continue to refer to Figure 1 ,or Figures 2 to 5In the first embodiment of this utility model, the first dielectric layer 115 is specifically disposed on the front side of the first encapsulation layer 112, so as to be physically connected (electrically connected) through the second metal layer 114 located between the first dielectric layer 115 and the first encapsulation layer 112, and physically connected to the second encapsulation layer 117 through the fourth metal layer 116 located on its top surface; while the second dielectric layer 132 can be located on the second surface 100b of the first substrate 100, so as to add a dielectric layer on both sides of the structure encapsulating the first chip 113; and at least one conductive pillar, such as a third conductive pillar 120, can also be disposed in the first dielectric layer 115 and the second dielectric layer 132; specifically, at least one of the third conductive pillars 120 can pass through the first dielectric layer 115 or the second dielectric layer 132 to directly contact (physically connect) the second metal layer 114 and the fourth metal layer 116, or directly contact the third metal layer 131. It should be understood that the first conductive post 118, the second conductive post 119, and the third conductive post 120 in the embodiments of this utility model may be projected to coincide in the vertical direction, or it may be understood that the first conductive post 118, the second conductive post 119, and the third conductive post 120 are aligned in the vertical direction to realize the electrical connection between multiple module layers in the packaging structure of this utility model, but this is not a limitation. In one embodiment, the materials of the first dielectric layer 115 and the second dielectric layer 132 can be thermosetting resins. Since the first chip 113 has been pre-mounted, pressure can be applied to the first encapsulation layer 112 during the lamination of the first dielectric layer 115, thus preventing damage to the first chip 112 and reducing packaging difficulty and cost. Secondly, since the materials of the first dielectric layer 115 and the second dielectric layer 132 in this embodiment are thermosetting resins, which have the characteristic of being able to cure under uniform pressure, stress redistribution can be achieved during the formation of the first dielectric layer 115 and the second dielectric layer 132, thereby offsetting stress and improving warpage. Furthermore, the double-sided addition of dielectric layers can increase wiring density.
[0049] Furthermore, since the first encapsulation layer 112 in the first embodiment of the present invention has a first dielectric layer 115 on one side and a first substrate 100 on the other side, and the material of the first encapsulation layer 112 is a molding compound, the first molding compound 112 can also be used as a dielectric layer between the first substrate 100 and the first dielectric layer 115, thereby achieving the purpose of increasing wiring density.
[0050] Continue to refer to Figure 1 ,or Figures 2 to 5In the first embodiment of the present invention, after the first dielectric layer 115 and the second dielectric layer 132 are formed simultaneously, a second encapsulation layer 117 can be conformally formed on the fourth metal layer 116 on the surface of the first dielectric layer 115. The second encapsulation layer 117 also encapsulates other chips, such as a second chip (not shown), to achieve single-sided multilayer stacked encapsulation, but is not limited thereto. It should be understood that in the encapsulation structure of the first embodiment of the present invention, a metal layer, such as a fifth metal layer 133, can be further disposed on the other surface of the second dielectric layer 132 away from the first substrate 100. The material of the fifth metal layer 133 can also be the same as the materials of the aforementioned first to fourth metal layers, such as copper, but is not limited thereto.
[0051] Those skilled in the art will readily understand that, to meet actual product requirements, the packaging structure of this utility model may have other forms and is not limited to those described above. The following will further describe other embodiments or variations of the packaging structure of this utility model. For the sake of simplicity, identical components in each embodiment of this utility model are designated with the same reference numerals to facilitate comparison between embodiments.
[0052] Please refer to Figure 6 The illustration shown is a cross-sectional schematic diagram of an example of the packaging structure in the second embodiment of this utility model. Figure 6As shown, the packaging structure in the second embodiment of this utility model is largely the same as that in the first embodiment, including the first substrate 100, the first metal layer 111, the first encapsulation layer 112, the first chip 113, the second metal layer 114, the first dielectric layer 115, the fourth metal layer 116, the second encapsulation layer 117, and the third metal layer 131. At least one first conductive post 118 may also be provided in the first substrate 100, so that the first metal layer 111 and the third metal layer 131 covering the first surface 100a and the second surface 100b of the first substrate 100 are respectively connected through the end of the first conductive post 118, thereby realizing the electrical connection (physical contact) between multiple film layers in the packaging structure. At least one second conductive post 119 may also be provided in the first encapsulation layer 112, and at least one third conductive post 120 may be provided in the first dielectric layer 115, etc. The similarities will not be repeated here. The main difference between the packaging structure of the second embodiment of this utility model and the first embodiment is that the second surface 100b of the first substrate 100 is not provided with a second dielectric layer 132. That is, only one dielectric layer is provided in the second embodiment of this utility model. For example, a first dielectric layer 115 is formed only on the second metal layer 114 on the first packaging layer 112. However, since the material of the first dielectric layer 115 is still thermosetting resin, the second embodiment of this utility model can still apply pressure to the first packaging layer 112 when the first dielectric layer 115 is laminated, thereby preventing the first chip 112 from being damaged. It can also reduce the packaging difficulty and packaging cost, as well as achieve stress redistribution, stress relief, warpage reduction and increased wiring density.
[0053] It should be understood that "common shape" in the embodiments of this utility model refers to the construction of a continuous structural shape by utilizing the morphological similarity and correlation between two or more shapes.
[0054] To enable those skilled in the art to easily understand the packaging structures in the first to sixth embodiments of this utility model, this utility model also provides a packaging method for the packaging structure, which will be described below. Figure 1 Taking the aforementioned packaging structure as an example, and combining it with the structural schematic diagrams of the packaging method during the preparation process, the packaging method of the packaging structure proposed in this utility model will be further explained.
[0055] in, Figures 7-11 In response to Figure 1 The diagram shows the structural schematic corresponding to the steps of the packaging method of the packaging structure provided in the first embodiment of this utility model.
[0056] Please refer to Figure 7First, a first substrate 100 is provided. The first substrate 100 may contain circuit structures, such as a piezoelectric layer (not shown), an interdigital transducer (not shown), a substrate (not shown), a trap layer (not shown), and one or more dielectric layers (not shown), and is not limited thereto. Specifically, the first substrate 100 may be formed of or include at least one of insulating materials. For example, the first substrate 100 may include photosensitive epoxy resin or PP fiberglass cloth. More specifically, the first substrate 100 may include photoimaging dielectric (PID), and is not limited thereto. Other components and / or devices may be disposed within the first substrate 100, such as circuit structures like piezoelectric layers (not shown), and wiring layers for electrically connecting different circuit structures, and is not limited thereto. Then, a first metal layer 111 and a third metal layer 132 can be formed on the first surface 100a and the second surface 100b opposite to the first substrate 100 using deposition (e.g., sputtering, printing, electroplating, electroless plating, CVD, etc.), photolithography, etching (dry etching or wet etching), respectively, and at least one first conductive pillar 118 is formed in the first substrate 100. In one embodiment, the materials of the first metal layer 111 and the third metal layer 132 can be the same, for example, including but not limited to metal materials, such as copper, titanium, nickel, gold, and combinations or alloys thereof, preferably metallic copper, and the material of the first conductive pillar 118 can also be the same as the material of the first metal layer 111 and / or the third metal layer 132, but is not limited thereto.
[0057] Please refer to Figure 8 and Figure 9 Next, on the first metal layer 111 on the first surface 100a side of the first substrate 100, at least one first chip 113 with bumps 113a on its front or back side is attached to the first metal layer 111 of the first substrate 100 by means of flip-chip bonding or the like. Then, a first encapsulation layer 112 is formed to encapsulate or embed the first chip 113 using a C-mold process. Next, multiple second conductive pillars 119 are formed on both sides of the first chip 113 within the first encapsulation layer 112 using processes such as etching, sputtering, printing, electroplating, electroless plating, and CVD. A second metal layer 114 is formed on the top surface of the first encapsulation layer 112. In one embodiment, the material of the second metal layer 114 may be the same as the material of the first metal layer 111, and the material of the first encapsulation layer 112 may be a thermoplastic molding compound, but is not limited thereto.
[0058] Please refer to Figure 10 and Figure 11A first dielectric layer 115 and a second dielectric layer 132, made of thermosetting resin, can be simultaneously formed on the surface of the second metal layer 114 on the first encapsulation layer 112 and on the third metal layer 131 on the second surface 100b of the first substrate 100, respectively, using a thermosetting method. Subsequently, a fourth metal layer 116 and a fifth metal layer 133 are formed on the first dielectric layer 115 and the second dielectric layer 132, respectively, using the same method as forming the first metal layer 111 or the second metal layer 114. Finally, a second encapsulation layer 117 is formed on the top surface of the fourth metal layer 114, wherein at least one other chip, such as a second chip, can be encapsulated within the second encapsulation layer 117, but is not limited thereto. Furthermore, the materials of the fourth metal layer 116 and the fifth metal layer 133 can be the same as the material of the first metal layer 111, but are not limited thereto.
[0059] In summary, in the packaging structure provided by this utility model, single-sided packaging can be performed on the first substrate first. For example, a first packaging layer containing a first chip can be formed on the first surface of the first substrate. Then, at least one dielectric layer, such as a first dielectric layer, is laminated on the first packaging layer. An unexpected effect is that since the first chip has been pre-mounted, pressure can be applied to the first packaging layer during the lamination of the first dielectric layer, which prevents damage to the first chip and reduces packaging difficulty and cost. Furthermore, while laminating the first dielectric layer on the first packaging layer, a second dielectric layer can be laminated on the second surface of the first substrate (the surface where the first packaging layer is not formed). An unexpected effect is that by utilizing the characteristic that the first and second dielectric layers, made of thermosetting resin, can be cured under uniform pressure, stress redistribution can be achieved, i.e., stress relief can be achieved, thereby improving warpage. Secondly, the addition of a first or second dielectric layer can also increase the wiring density.
[0060] In this application, references to "one embodiment" or "some embodiments" mean that a feature, structure, or characteristic described in connection with that embodiment is included in at least one embodiment or at least some embodiments of this application. Therefore, the appearance of the phrases "in one embodiment" or "in some embodiments" throughout this application does not necessarily refer to the same or the same embodiments. Furthermore, in one or more embodiments, features, structures, or characteristics can be combined in any suitable combination and / or sub-combination.
[0061] While specific embodiments of this application have been described in detail by way of examples, those skilled in the art should understand that the above examples are for illustrative purposes only and not for limiting the scope of this application. The embodiments of this application can be combined in any way without departing from the spirit and scope of this application. Those skilled in the art should also understand that various modifications can be made to the embodiments without departing from the scope and spirit of this application. The scope of this application is defined by the appended claims.
Claims
1. A packaging structure, characterized in that, include: The first substrate has a first surface and a second surface disposed opposite to each other; A first metal layer is disposed on the first surface of the first substrate; A first encapsulation layer is disposed on the first metal layer and includes at least one first chip embedded therein, wherein the first chip and the first metal layer have a first gap. A second metal layer is disposed on the first packaging layer and has a second gap between it and the first chip; A first dielectric layer is disposed on the second metal layer; A third metal layer is disposed on the second surface of the first substrate.
2. The packaging structure as described in claim 1, characterized in that, Also includes: The second dielectric layer is disposed on the third metal layer.
3. The packaging structure as described in claim 2, characterized in that, Also includes: A fourth metal layer is disposed on the first dielectric layer; The second encapsulation layer is located on the fourth metal layer.
4. The packaging structure as described in claim 2, characterized in that, Also includes: At least one first conductive post is located within the first substrate and passes through the first substrate to directly contact the first metal layer and / or the third metal layer on the first substrate.
5. The packaging structure as described in claim 1, characterized in that, Also includes: At least one second conductive post is located within the first encapsulation layer on at least one side of the first chip and passes through the first encapsulation layer to directly contact the first metal layer and the second metal layer.
6. The packaging structure as described in claim 1, characterized in that, Also includes: At least one solder ball is located within the first package layer on at least one side of the first chip and passes through the first package layer to directly contact the first metal layer and the second metal layer.
7. The packaging structure as described in claim 3, characterized in that, Also includes: At least one third conductive post is disposed in the first dielectric layer and / or the second dielectric layer, and passes through the first dielectric layer and / or the second dielectric layer to directly contact the second metal layer, the fourth metal layer and / or the third metal layer.
8. The packaging structure as described in claim 1, characterized in that, Also includes: Multiple bumps or multiple solder joints are located in the first gap or the second gap to mount the first chip within the first encapsulation layer.
9. The packaging structure as described in claim 2, characterized in that, The material of the first dielectric layer and / or the second dielectric layer includes a thermosetting resin.
10. The packaging structure as described in claim 3, characterized in that, Also includes: The second chip is disposed within the second packaging layer.