Fault monitoring circuit, chip and vehicle

Abstract

The utility model is suitable for the technical field of fault monitoring, and provides a fault monitoring circuit, a chip and a vehicle. The fault monitoring circuit comprises a monitoring module, a first logic module, a second logic module, a first time delay module and a second time delay module, the second time delay module is electrically connected with the first logic module and the second logic module, and the first logic module is used for being electrically connected with the output end of the procore. The input end of the monitoring module is electrically connected with the input end of the procore through the first delay module, and the output end of the monitoring module is electrically connected with the second logic module. The fault monitoring circuit provided by the embodiment of the utility model can monitor the procore, and if the second logic module outputs the logic monitoring signal, it is indicated that the monitoring signal is different from the initial signal, and it is represented that nuclear inspection is abnormal. When fault monitoring is carried out on the original core, the fault monitoring circuit can quickly determine that the core check is abnormal through the logic monitoring signal, and the monitoring response speed when the CPU core breaks down is remarkably improved.

Description

Technical Field

[0001] This application belongs to the field of fault monitoring technology, and in particular relates to a fault monitoring circuit, chip and vehicle. Background Technology

[0002] With the development of integrated circuit technology, the CPU (Central Processing Unit) core inside a chip plays a crucial role in various electronic devices. The CPU core is the core component of a chip, responsible for performing computational and control tasks. However, due to manufacturing defects, environmental factors, and aging caused by long-term use, CPU cores may experience various failures, such as logic errors, timing errors, and power fluctuations. These failures not only affect the normal operation of the system but may also lead to data loss, system crashes, and even security risks. Therefore, real-time monitoring of the CPU core and timely detection and handling of failures are crucial for improving the reliability and stability of chips and systems. However, existing CPU core monitoring typically uses a watchdog timer, which monitors the CPU core's operating status by setting a time threshold. If the CPU core does not reset the watchdog timer within the specified time, it indicates a possible failure. However, using a watchdog timer requires a certain amount of time to trigger the reset signal, resulting in a slow response speed when a CPU core failure occurs. Utility Model Content

[0003] This application provides a fault monitoring circuit, chip, and vehicle, which can solve the problem that existing fault monitoring methods typically use monitoring timers, resulting in slow response speeds when a CPU core malfunctions.

[0004] In a first aspect, embodiments of this application provide a fault monitoring circuit, including a monitoring module, a first logic module, a second logic module, a first delay module, and a second delay module. The second delay module is electrically connected to both the first logic module and the second logic module. The first logic module is electrically connected to the output terminal of the original core. The input terminal of the monitoring module is electrically connected to the input terminal of the original core through the first delay module. The output terminal of the monitoring module is electrically connected to the second logic module.

[0005] The first delay module is used to delay the input signal for a preset time before transmitting it to the monitoring module. The monitoring module is used to output a monitoring signal to the second logic module according to the input signal. The first logic module is used to output a first logic signal according to an initial signal, where the initial signal is the signal output by the original kernel according to the input signal. The second delay module is used to delay the first logic signal for the preset time to obtain a second delayed signal, and transmit the second delayed signal to the second logic module. The second logic module is used to output a logic monitoring signal according to the monitoring signal and the second delayed signal.

[0006] In one possible implementation of the first aspect, the monitoring module includes a monitoring core, which is electrically connected to the first delay module and the second logic module respectively.

[0007] In one possible implementation of the first aspect, the first logic module includes a NOT gate, the input of which is electrically connected to the original core, and the output of which is electrically connected to the second delay module.

[0008] In one possible implementation of the first aspect, the second logic module includes an XOR gate, the first input of which is electrically connected to the second delay module, the second input of which is electrically connected to the monitoring module, and the output of which is used to output the logic monitoring signal.

[0009] In one possible implementation of the first aspect, the first delay module includes a first delay unit, the input of which is used to receive the input signal, and the output of which is electrically connected to the monitoring module.

[0010] In one possible implementation of the first aspect, the second delay module includes a second delayer, the input of which is electrically connected to the first logic module, and the output of which is electrically connected to the second logic module.

[0011] In one possible implementation of the first aspect, the fault monitoring circuit further includes a third logic module and a fourth logic module, wherein the third logic module is electrically connected to the original core and the first logic module respectively, and the fourth logic module is electrically connected to the monitoring module and the second logic module respectively;

[0012] The third logic module is used to output a third logic signal to the first logic module according to the initial signal, and the fourth logic module is used to output a fourth logic signal to the second logic module according to the monitoring signal.

[0013] In one possible implementation of the first aspect, the fault monitoring circuit further includes a storage module electrically connected to the second logic module, the storage module being used to store the logic monitoring signal.

[0014] Secondly, embodiments of this application provide a chip including the fault monitoring circuit described in any one of the first aspects.

[0015] Thirdly, embodiments of this application provide a vehicle that includes the chip described in the second aspect.

[0016] The beneficial effects of the embodiments in this application compared with the prior art are:

[0017] The fault monitoring circuit provided in this application includes a monitoring module, a first logic module, a second logic module, a first delay module, and a second delay module. The first delay module can delay the input signal for a preset time before transmitting it to the monitoring module. The monitoring module outputs a monitoring signal to the second logic module based on the input signal. The first logic module outputs a first logic signal based on the initial signal output by the original core. The second delay module can delay the first logic signal for a preset time to obtain a second delayed signal, and then transmits the second delayed signal to the second logic module. The second logic module is used to output a logic monitoring signal based on the monitoring signal and the second delayed signal. Therefore, the fault monitoring circuit provided in this application achieves comprehensive monitoring of the CPU core through the coordinated action of the monitoring module, the first logic module, the second logic module, the first delay module, and the second delay module. If the second logic module outputs a logic monitoring signal, it indicates that the monitoring signal is different from the initial signal, signifying an anomaly in the core check. Therefore, when monitoring the original core for faults, the fault monitoring circuit can quickly determine an anomaly in the core check through the logic monitoring signal output by the second logic module, significantly improving the monitoring response speed when a CPU core fault occurs compared to traditional monitoring timers. Attached Figure Description

[0018] To more clearly illustrate the technical solutions in the embodiments of this application, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0019] Figure 1 This is a schematic block diagram of a fault monitoring circuit provided in one embodiment of this application;

[0020] Figure 2 This is a schematic block diagram of the circuit connection of a fault monitoring circuit provided in an embodiment of this application;

[0021] Figure 3 This is a schematic block diagram of a fault monitoring circuit provided in another embodiment of this application;

[0022] Figure 4 This is a circuit connection diagram of an encoding module provided in an embodiment of this application.

[0023] In the diagram, 10 is the fault monitoring circuit; 101 is the monitoring module; 102 is the first logic module; 103 is the second logic module; 104 is the first delay module; 105 is the second delay module; 106 is the third logic module; 107 is the fourth logic module; 108 is the storage module; and 109 is the encoding module. Detailed Implementation

[0024] In the following description, specific details such as particular system architectures and techniques are set forth for illustrative purposes and not for limitation, in order to provide a thorough understanding of the embodiments of this application. However, those skilled in the art will understand that this application may also be implemented in other embodiments without these specific details. In other instances, detailed descriptions of well-known systems, apparatuses, circuits, and methods have been omitted so as not to obscure the description of this application with unnecessary detail.

[0025] It should be understood that, when used in this application specification and the appended claims, the term "comprising" indicates the presence of the described features, integrals, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components and / or a collection thereof.

[0026] It should also be understood that the term “and / or” as used in this application specification and the appended claims means any combination of one or more of the associated listed items and all possible combinations, and includes such combinations.

[0027] As used in this application specification and the appended claims, the term "if" may be interpreted, depending on the context, as "when," "once," "in response to determination," or "in response to detection." Similarly, the phrase "if determined" or "if [the described condition or event] is detected" may be interpreted, depending on the context, as "once determined," "in response to determination," "once [the described condition or event] is detected," or "in response to detection of [the described condition or event]."

[0028] Furthermore, in the description of this application and the appended claims, the terms "first," "second," "third," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0029] References to "one embodiment" or "some embodiments" as described in this specification mean that one or more embodiments of this application include a specific feature, structure, or characteristic described in connection with that embodiment. Therefore, the phrases "in one embodiment," "in some embodiments," "in other embodiments," "in still other embodiments," etc., appearing in different parts of this specification do not necessarily refer to the same embodiment, but rather mean "one or more, but not all, embodiments," unless otherwise specifically emphasized. The terms "comprising," "including," "having," and variations thereof mean "including but not limited to," unless otherwise specifically emphasized.

[0030] Current methods for monitoring CPU cores typically use a watchdog timer, which monitors the CPU core's operating status by setting a time threshold. If the CPU core does not reset the watchdog timer within the specified time, it indicates a potential malfunction. However, using a watchdog timer requires a certain amount of time to trigger the reset signal, resulting in a slow response time when a CPU core malfunctions.

[0031] To address the aforementioned issues, this application provides a fault monitoring circuit designed around the working characteristics of the CPU core, aiming to monitor the CPU core's operating status more accurately and quickly. The fault monitoring circuit includes a monitoring module, a first logic module, a second logic module, a first delay module, and a second delay module. The first delay module receives input signals from the CPU core during operation and transmits them to the monitoring module after a preset delay. These input signals can be various status signals or data signals generated when the CPU core executes instructions; the delay processing captures the dynamic changes in these signals. The monitoring module, based on the received input signals and the signal patterns observed during normal CPU core operation, outputs a monitoring signal to the second logic module. The first logic module is directly connected to the CPU core's original core, performing logical operations based on the initial signal output by the original core and outputting a first logic signal. The initial signal output by the original core reflects the real-time status of the CPU core's internal instruction processing, data processing, and other core operations, serving as a key basis for determining whether the CPU core is operating normally. The second delay module delays the first logic signal for a preset time before transmitting the second delayed signal to the second logic module. The second logic module, as the core judgment unit of the entire fault monitoring circuit, is used to output a logic monitoring signal based on the monitoring signal and the second delay signal. The fault monitoring circuit provided in this application, through the coordinated action of the monitoring module, the first logic module, the second logic module, the first delay module, and the second delay module, achieves comprehensive monitoring of the CPU core. If the second logic module outputs a logic monitoring signal, it indicates that the monitoring signal is different from the initial signal, signifying an anomaly in the core check. Therefore, when monitoring the original core for faults, the fault monitoring circuit can quickly determine an anomaly in the core check through the logic monitoring signal output by the second logic module, significantly improving the monitoring response speed when a CPU core fault occurs compared to traditional monitoring timers.

[0032] To illustrate the technical solution described in this application, specific embodiments are provided below.

[0033] Figure 1 A schematic block diagram of a fault monitoring circuit 10 according to an embodiment of this application is shown. See also... Figure 1 As shown, the fault monitoring circuit 10 includes a monitoring module 101, a first logic module 102, a second logic module 103, a first delay module 104, and a second delay module 105. The second delay module 105 is electrically connected to the first logic module 102 and the second logic module 103, respectively. The first logic module 102 is used to be electrically connected to the output terminal of the original core 20. The input terminal of the monitoring module 101 is electrically connected to the input terminal of the original core 20 through the first delay module 104. The output terminal of the monitoring module 101 is electrically connected to the second logic module 103.

[0034] Specifically, the first delay module 101 receives input signals from the CPU core during operation and transmits them to the monitoring module 101 after a preset delay. These input signals can be various status signals or data signals generated when the CPU core executes instructions. Through delay processing, the dynamic characteristics of the signals can be captured. The monitoring module 101 then outputs a monitoring signal b[i] to the second logic module 103 based on the received input signals and the signal patterns during normal CPU core operation. The first logic module 102 is directly connected to the original core 20 of the CPU core. It performs logical operations based on the initial signal a[i] output by the original core 20 and outputs a first logic signal. The initial signal a[i] output by the original core 20 reflects the real-time state of the CPU core's internal instruction processing, data processing, and other core operations, and is a key basis for determining whether the CPU core is working normally. After the second delay module 105 delays the first logic signal for a preset time, it transmits the second delayed signal x[i] to the second logic module 103. The second logic module 103, as the core judgment unit of the entire fault monitoring circuit, is used to output a logic monitoring signal cmp[i] based on the monitoring signal b[i] and the second delay signal x[i]. The fault monitoring circuit 10 provided in this embodiment achieves comprehensive monitoring of the original core 20 through the coordinated action of the monitoring module 101, the first logic module 102, the second logic module 103, the first delay module 104, and the second delay module 105. If the second logic module 103 outputs the logic monitoring signal cmp[i], it indicates that the monitoring signal b[i] and the initial signal a[i] are different, signifying an anomaly in the core check. Therefore, when monitoring the original core 20 for faults, the fault monitoring circuit 10 can quickly determine an anomaly in the core check through the logic monitoring signal cmp[i] output by the second logic module 103, significantly improving the monitoring response speed when a CPU core malfunctions compared to traditional monitoring timers.

[0035] It should be noted that the purpose of setting the first delay module 104 at the input end of the monitoring module 101 to delay the input signal is to prevent common-cause failure. Common-cause failure refers to the situation where two or more system components fail simultaneously due to the same cause. In this application, setting the first delay module 104 can serve as a defensive measure, increasing the system's resistance to common-cause failure and reducing its impact on the system.

[0036] It should be noted that the first delay module 104 delays the input signal by a preset time, and the second delay module 105 delays the first logic signal by a preset time. These two preset times can be set to the same value to ensure the accuracy of the logic monitoring signal cmp[i] output by the second logic module 103. The preset time can be fixed or configurable, depending on the system requirements and design, and is not limited here. For example, the preset time can be the number of clock cycles.

[0037] It should be noted that the monitoring module 101, the first logic module 102, the second logic module 103, the first delay module 104, and the second delay module 105 are all located inside the chip.

[0038] For example, the original core 20 can be a CPU core, and the input signal can be CPU core instructions or core data. The fault monitoring circuit 10 in this application can monitor the CPU core instructions or core data.

[0039] In one embodiment of this application, such as Figure 2 As shown, the monitoring module 101 includes a monitoring core, which is electrically connected to the first delay module 104 and the second logic module 103.

[0040] Specifically, the monitoring core is used to compare with the output of the original core 20 and outputs a logic monitoring signal cmp[i] through the second logic module 103. If the second logic module 103 outputs the logic monitoring signal cmp[i], it indicates that the monitoring signal b[i] output by the monitoring core is different from the initial signal a[i]. At this time, the characterization core check shows an anomaly. Meanwhile, the monitoring core is the same as the original core 20. Setting the monitoring core to be the same as the original core 20 ensures that the monitoring core can accurately reflect the state of the original core 20. If the hardware configuration and operating environment of the monitoring core are different from those of the original core 20, it may not be able to completely and accurately replicate the operating state of the original core 20, resulting in the output of an incorrect monitoring signal b[i]. Therefore, in order to ensure that the monitoring core can effectively detect errors in the original core 20, the monitoring core needs to be set to be the same as the original core 20.

[0041] In one embodiment of this application, such as Figure 2 As shown, the first delay module 104 includes a first delay unit. The input terminal of the first delay unit is used to receive input signals, and the output terminal of the first delay unit is electrically connected to the monitoring module 101.

[0042] Specifically, the first delay unit is used to delay the input signal for a preset time, thereby preventing common-cause failure and reducing the possibility of multiple signals being interfered with simultaneously by introducing a time delay. At the same time, the first delay unit can also act as a filter to smooth the input signal and reduce the impact of noise on the system.

[0043] In one embodiment of this application, such as Figure 2 As shown, the first logic module 102 includes a NOT gate, the input of which is electrically connected to the original core 20, and the output of which is electrically connected to the second delay module 105.

[0044] Specifically, the NOT gate's operation logic is as follows: when the NOT gate's input receives a high-level signal, its output will output a low-level signal. When the NOT gate's input receives a low-level signal, its output will output a high-level signal. Therefore, if the initial signal a[i] output by the original core 20 is a high-level signal, after the NOT gate's logic operation, the first logic signal output at the NOT gate's output will be a low-level signal. If the initial signal a[i] output by the original core 20 is a low-level signal, after the NOT gate's logic operation, the first logic signal output at the NOT gate's output will be a high-level signal. Furthermore, in digital circuits, the NOT gate can also be used to synchronize signals, that is, by delaying the signal by a certain period of time, the signal edges are aligned.

[0045] In one embodiment of this application, such as Figure 2 As shown, the second delay module 105 includes a second delay unit. The input terminal of the second delay unit is electrically connected to the first logic module 102, and the output terminal of the second delay unit is electrically connected to the second logic module 103.

[0046] Specifically, since a first delayer is introduced at the input of the monitoring core to delay the input signal, a second delayer also needs to be introduced at the output of the original core 20 to delay the first logic signal for a preset time, maintaining the synchronization of the monitoring signal b[i] and the initial signal a[i], so as to achieve accurate core checking and ensure the accuracy of the logic monitoring signal cmp[i] output by the second logic module 103.

[0047] In one embodiment of this application, such as Figure 2 As shown, the second logic module 103 includes an XOR gate. The first input terminal of the XOR gate is electrically connected to the second delay module 105, the second input terminal of the XOR gate is electrically connected to the monitoring module 101, and the output terminal of the XOR gate is used to output the logic monitoring signal cmp[i].

[0048] Specifically, the XOR gate's operational logic is as follows: when the two input signals received by the XOR gate are the same, the XOR gate outputs a high-level signal; when the two input signals received by the XOR gate are different, the XOR gate outputs a low-level signal. That is, if both the second delay signal x[i] and the monitoring signal b[i] are high-level signals or both are low-level signals, it indicates that the monitoring signal b[i] and the initial signal a[i] are different. In this case, the logic monitoring signal cmp[i] output by the XOR gate is a high-level signal, and the core check shows an anomaly. If one of the signals between the second delay signal x[i] and the monitoring signal b[i] is a low-level signal and the other is a high-level signal, it indicates that the monitoring signal b[i] and the initial signal a[i] are the same. In this case, the XOR gate outputs a low-level signal, and the core check is normal.

[0049] In one embodiment of this application, such as Figure 3 As shown, the fault monitoring circuit 10 also includes a third logic module 106 and a fourth logic module 107. The third logic module 106 is electrically connected to the original core 20 and the first logic module 102, respectively, and the fourth logic module 107 is electrically connected to the monitoring module 101 and the second logic module 103, respectively.

[0050] Specifically, the third logic module 106 is used to output a third logic signal to the first logic module 102 based on the initial signal a[i], and the fourth logic module 107 is used to output a fourth logic signal y[i] to the second logic module 103 based on the monitoring signal b[i]. Simultaneously, the third logic module 106 can perform logical operations on the initial signal a[i], and the fourth logic module 107 can perform logical operations on the monitoring signal b[i]. The logical operations performed by the third logic module 106 and the fourth logic module 107 are identical to maintain the synchronization between the monitoring signal b[i] and the initial signal a[i], thereby achieving accurate kernel checking and ensuring the accuracy of the logical monitoring signal cmp[i] output by the second logic module 103.

[0051] For example, both the third logic module 106 and the fourth logic module 107 may include NOT gates. The third logic module 106 performs NOT operation on the initial signal a[i], and the fourth logic module 107 performs NOT operation on the monitoring signal b[i].

[0052] It should be noted that both the third logic module 106 and the fourth logic module 107 can perform compression encoding operations to compress and encode the initial signal a[i] and the monitoring signal b[i], thereby reducing the computational load of the second logic module 103.

[0053] In one embodiment of this application, such as Figure 3 As shown, the fault monitoring circuit 10 also includes a storage module 108, which is electrically connected to the second logic module 103.

[0054] Specifically, the storage module 108 is used to store the logic monitoring signal cmp[i]. By reading the logic monitoring signal cmp[i] in the storage module 108, the abnormality of the core check can be quickly determined, which significantly improves the monitoring response speed when the CPU core fails.

[0055] It should be noted that the storage module 108 can store the logic monitoring signal cmp[i] to ensure that engineers can analyze the cause of the fault and provide data basis for fault diagnosis.

[0056] For example, storage module 108 can use SRAM (Static Random Access Memory) as its hardware fault tracing storage area. SRAM has the characteristic of no storage latency and can perform data read and write operations at high frequency, ensuring that data can be written and read quickly without causing delay to the real-time monitoring and response of the fault monitoring system.

[0057] In one embodiment of this application, such as Figure 3 As shown, the fault monitoring circuit 10 also includes an encoding module 109. The input terminal of the encoding module 109 is electrically connected to the second logic module 103, and the output terminal of the encoding module 109 is electrically connected to the storage module 108.

[0058] Specifically, the encoding module 109 receives the logic monitoring signal cmp[i] output by the second logic module 103, compresses and encodes the logic monitoring signal cmp[i], and transmits the compressed and encoded signal to the storage module 108. This design can improve the processing efficiency of fault monitoring data and the utilization rate of storage space. By compressing and encoding the logic monitoring signal cmp[i] (one or more logic monitoring signals cmp[i]) by the encoding module 109, data redundancy and duplication can be reduced, thereby reducing the storage space required by the storage module 108. At the same time, the encoded signal is easier for subsequent data analysis and processing, which helps to quickly and accurately diagnose and locate faults. In addition, compression encoding also helps to reduce the bandwidth requirements for data transmission, improve the overall performance and response speed of the system.

[0059] In one embodiment of this application, the encoding module 109 includes M AND gates and N OR gates. The inputs of the M AND gates are electrically connected to the second logic module 103, and the outputs of the M AND gates are correspondingly electrically connected to the inputs of the N OR gates. The outputs of the N OR gates are all electrically connected to the storage module 108. Here, M and N are both positive integers, where M > N.

[0060] Specifically, the AND gate's operation logic is as follows: the AND gate will only output a high-level signal when all of its input signals are high-level signals. If one input of the AND gate is a positive input and the remaining inputs are inverting inputs (the AND gate has inverters at its inputs), when the input signal is transmitted to the positive input, the AND gate receives the original input signal. When the input signal is transmitted to the inverting input, the AND gate receives the signal inverted by the inverter, that is, the original signal after level flipping. The OR gate's operation logic is as follows: when one of the multiple input signals received by the OR gate is a high-level signal, the OR gate will output a high-level signal.

[0061] For example, with Figure 4For example, M is 8 and N is 3. The encoding module 109 includes eight AND gates and three OR gates, that is, there are eight input signals (I0~I7) and three output signals (O0~O2). If one fault monitoring circuit 10 monitors the core instructions and another fault monitoring circuit 10 monitors the core data, then the two second logic modules 103 in the two fault monitoring circuits 10 will output two logic monitoring signals cmp[i] (first logic monitoring signal cmp1[i] and second logic monitoring signal cmp2[i]), where the I0 input signal is the first logic monitoring signal cmp1[i], the I1 input signal is the second logic monitoring signal cmp2[i], and the I2~I8 input signals are monitoring signals output by other modules. If the core data is abnormal, the second logic monitoring signal cmp2[i] is 1 and the first logic monitoring signal cmp1[i] is 0, that is, the I0 input signal is 0 and the I1 input signal is 1. At this time, the three output signals are 001 in sequence.

[0062] It should be noted that the logic monitoring signal cmp[i] can also be set to other values. In this case, the eight input signals include the logic monitoring signal cmp[i] output by the fault monitoring circuit 10 and the monitoring signals output by other modules, thus forming a multi-channel compression encoder. Therefore, by compressing and encoding the eight input signals, three output signals are finally output. This design can reduce data redundancy and duplication, thereby reducing the storage space required by the storage module 108.

[0063] It should be noted that if the I0 input signal is 1 and the remaining seven input signals are all 0, then the three output signals will be 000. If the I0 input signal is 0, the I1 input signal is 1, and the remaining six input signals can take any value, then the three output signals will be 001. If the I0 input signal is 0, the I1 input signal is 0, the I2 input signal is 1, and the remaining five input signals can take any value, then the three output signals will be 010. Therefore, to prevent multiple alarm signals from being valid simultaneously, it is stipulated that only the alarm signal with the lowest sequence number is output. Designers can set the corresponding position of the monitoring signals according to the importance of the voltage detection within the chip, that is, the more important the monitoring signal, the earlier its position.

[0064] It should be noted that the following is combined with Figures 1 to 4 The overall working principle of the fault monitoring circuit 10 described above is described.

[0065] The first delay unit delays the input signal for a preset time and transmits the delayed signal to the monitoring core. The monitoring core outputs a monitoring signal b[i] based on the delayed signal. The third logic module 106 outputs a third logic signal to the NOT gate based on the initial signal a[i]. The NOT gate inverts the third logic signal, i.e., outputs a first logic signal to the second delay unit. The second delay unit outputs a second delayed signal x[i] based on the first logic signal. The fourth logic module 107 outputs a fourth logic signal y[i] to the XOR gate based on the monitoring signal b[i]. The XOR gate performs an XOR operation on the second delayed signal x[i] and the fourth logic signal y[i], and transmits the output logic monitoring signal cmp[i] to any input terminal of the encoding module 109. After the logical operations of the AND and OR gates in the encoding module 109, the corresponding compressed encoded signal is output at the output terminal. The storage module 108 stores the compressed encoded signal.

[0066] This application also discloses a chip including the above-mentioned fault monitoring circuit 10. When monitoring the original core 20 for faults, the fault monitoring circuit 10 can quickly output a logic monitoring signal to determine that the core check has an abnormality, which significantly improves the monitoring response speed when the CPU core has a fault.

[0067] This application also discloses a vehicle that includes the aforementioned chip. When the vehicle's electronic system malfunctions, the fault monitoring circuit within the chip can quickly locate the source of the fault, thereby improving the efficiency and accuracy of fault diagnosis.

[0068] Since the processing and functions implemented by the chip in this embodiment are basically the same as the embodiments, principles and examples of the aforementioned fault monitoring circuit, any details not covered in this embodiment can be found in the relevant descriptions in the aforementioned embodiments, and will not be repeated here.

[0069] The above-described embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application, and should all be included within the protection scope of this application.

Claims

1. A fault monitoring circuit, characterized in that, It includes a monitoring module, a first logic module, a second logic module, a first delay module, and a second delay module. The second delay module is electrically connected to both the first logic module and the second logic module. The first logic module is electrically connected to the output terminal of the original core. The input terminal of the monitoring module is electrically connected to the input terminal of the original core through the first delay module. The output terminal of the monitoring module is electrically connected to the second logic module. The first delay module is used to delay the input signal for a preset time before transmitting it to the monitoring module. The monitoring module is used to output a monitoring signal to the second logic module according to the input signal. The first logic module is used to output a first logic signal according to an initial signal, where the initial signal is the signal output by the original kernel according to the input signal. The second delay module is used to delay the first logic signal for the preset time to obtain a second delayed signal, and transmit the second delayed signal to the second logic module. The second logic module is used to output a logic monitoring signal according to the monitoring signal and the second delayed signal.

2. The fault monitoring circuit according to claim 1, characterized in that, The monitoring module includes a monitoring core, which is electrically connected to the first delay module and the second logic module respectively.

3. The fault monitoring circuit according to claim 1, characterized in that, The first logic module includes a NOT gate, the input of which is electrically connected to the output of the original core, and the output of which is electrically connected to the second delay module.

4. The fault monitoring circuit according to claim 1, characterized in that, The second logic module includes an XOR gate, the first input of which is electrically connected to the second delay module, the second input of which is electrically connected to the monitoring module, and the output of which is used to output the logic monitoring signal.

5. The fault monitoring circuit according to claim 1, characterized in that, The first delay module includes a first delay unit, the input terminal of which is used to receive the input signal, and the output terminal of which is electrically connected to the monitoring module.

6. The fault monitoring circuit according to claim 1, characterized in that, The second delay module includes a second delay unit, the input of which is electrically connected to the first logic module, and the output of which is electrically connected to the second logic module.

7. The fault monitoring circuit according to any one of claims 1-6, characterized in that, The fault monitoring circuit further includes a third logic module and a fourth logic module. The third logic module is electrically connected to the original core and the first logic module, respectively, and the fourth logic module is electrically connected to the monitoring module and the second logic module, respectively. The third logic module is used to output a third logic signal to the first logic module according to the initial signal, and the fourth logic module is used to output a fourth logic signal to the second logic module according to the monitoring signal.

8. The fault monitoring circuit according to any one of claims 1-6, characterized in that, The fault monitoring circuit further includes a storage module, which is electrically connected to the second logic module and is used to store the logic monitoring signal.

9. A chip, characterized in that, Includes the fault monitoring circuit as described in any one of claims 1-8.

10. A vehicle, characterized in that, Includes the chip described in claim 9.

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