KGD high-temperature test system

Abstract

The application discloses a KGD high temperature test system comprising a test socket, the test socket is connected in parallel with a test loop and a discharge loop, and the test loop and the discharge loop are connected to the test socket through a relay. The relay controls the test socket to be connected with the test loop or the discharge loop. By adding a discharge loop and carrying out current limiting setting, short-circuit current can be completely limited, so that the test socket is better protected; the problems that a traditional test loop is large in stray inductance, the test loop is not subjected to current limiting optimization, thermal breakdown of a chip is caused by testing, and a test socket is damaged are solved, the test efficiency and the reliability of chip testing are improved, and the maintenance cost of the test socket is reduced.

Description

Technical Field

[0001] This application belongs to the field of semiconductor testing, and specifically relates to a high-temperature testing system suitable for SiC_KGD. Background Technology

[0002] KGD (Known Good Die) testing refers to the functional and performance testing of bare dies before chip packaging to ensure their yield before packaging. With the continuous advancement of semiconductor technology, especially the widespread application of third-generation semiconductor materials (such as SiC and GaN), the importance of KGD testing is increasingly prominent. However, most existing KGD testing schemes follow the finished product testing methods of traditional silicon-based chips, which has revealed some problems when testing chips made of new materials.

[0003] First, during dynamic testing, the system failed to provide a self-discharge loop for the chip when switching test circuits. This prevents the effective release of accumulated charge during testing, affecting the accuracy of test results and potentially damaging the chip. This charge accumulation problem is particularly severe in high-voltage, high-frequency applications, easily leading to gate oxide breakdown during self-oscillation.

[0004] Secondly, existing test systems have insufficient protection response time during short-circuit testing. Because third-generation semiconductor materials have higher switching speeds and lower on-resistance, the short-circuit current rises extremely rapidly. However, the protection mechanisms of traditional test systems have long response times and cannot cut off the current in time, leading to damage to the chip and test socket due to overcurrent during testing. This problem is particularly prominent in high-power-density applications, severely impacting test reliability and chip yield.

[0005] Therefore, a high-temperature KGD testing system is needed for third-generation semiconductors. Utility Model Content

[0006] To address the shortcomings of the prior art, this application provides a KGD high-temperature testing system and method, which solves the problems of low yield and test socket burnout in high-current chip KGD testing when performing high-temperature tests on chips (e.g., 150°C, 175°C).

[0007] The technical effect to be achieved in this application is accomplished through the following solution:

[0008] According to a first aspect of this application, a KGD high-temperature testing system is provided, including a test socket, a test loop and a discharge circuit connected in parallel on the test socket, the test loop and the discharge circuit being connected to the test socket via a relay, the relay controlling the test socket to be connected to the test loop or to the discharge circuit respectively.

[0009] Preferably, the chip to be tested is mounted upside down onto the test socket.

[0010] Preferably, the discharge circuit includes a monitoring module and a switching module. The monitoring module is used to detect the voltage and current parameters of the discharge circuit, and the switching module is used to open and close the circuit according to the values ​​of the voltage or current parameters to protect the chip.

[0011] Preferably, the monitoring module includes a DW01 chip, which is used to shut down the discharge circuit when the voltage in the discharge circuit exceeds a maximum voltage threshold or falls below a minimum voltage threshold; and to shut down the discharge circuit when the current in the discharge circuit exceeds a maximum current threshold.

[0012] Preferably, the switching module includes an AO4407 chip, used to control the AO4407 chip to open the discharge circuit to achieve normal discharge when the voltage in the discharge circuit is between the highest voltage threshold and the lowest voltage threshold, and when the current in the discharge circuit is lower than the highest current threshold.

[0013] Preferably, pin 1 of the DW01 chip is connected to pin 4 of the AO4407 chip via an AO3401 chip; pin 2 of the DW01 chip is connected to pins 1, 2, and 3 of the AO4407 chip via another AO3401 chip, and pin 2 of the DW01 chip is connected to a relay via resistor R10; pin 5 of the DW01 chip is connected to Vin; pins 5, 6, 7, and 8 of the AO4407 chip are all connected to Vout.

[0014] Preferably, pins 1, 2, and 3 of the AO4407 chip are connected to Vin.

[0015] According to one embodiment of this application, the beneficial effects of using this KGD high-temperature testing system are as follows: by adding a discharge circuit and setting a current limit, the short-circuit current can be completely limited, thereby better protecting the test socket; it solves the problems of large noise in the traditional test loop, lack of current limiting optimization in the test loop, which leads to thermal breakdown of the chip and damage to the test socket, thereby improving testing efficiency and chip testing reliability, and reducing the repair cost of the test socket. Attached Figure Description

[0016] To more clearly illustrate the embodiments of this application or the existing technical solutions, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0017] Figure 1 This is a schematic diagram of the structure of a KGD high-temperature testing system according to one embodiment of this application;

[0018] Figure 2 for Figure 1 Circuit diagram of the discharge circuit;

[0019] Figure 3 This is a performance curve graph of a traditional testing system.

[0020] Figure 4 This is a performance curve of the KGD high-temperature testing system during testing. Detailed Implementation

[0021] To make the objectives, technical solutions, and advantages of this application clearer, the technical solutions of this application will be clearly and completely described below in conjunction with specific embodiments and corresponding drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0022] like Figure 1 As shown, in one embodiment of this application, the KGD high-temperature testing system includes a test socket, on which a test loop and a discharge circuit are connected in parallel. The test loop and the discharge circuit are connected to the test socket via a relay, and the relay controls the test socket to be connected to the test loop or the discharge circuit respectively.

[0023] Traditional test loops have high noise levels and lack current-limiting optimization. This means that defective chips cannot be protected in advance, leading to thermal breakdown and damage to the test socket. By adding a discharge circuit and current-limiting settings, short-circuit current is completely limited, thus providing better protection for the test socket.

[0024] In one embodiment of this application, the chip is mounted upside down, allowing the drain (G) and source (S) terminals of the chip to directly contact each other via the ping pin. This minimizes the gate-source distance, reducing inductance loops. It also prevents the device from concentrating in a high electric field, which could lead to gate-drain tunneling. This solves the gate-source interconnection problem caused by traditional parallel pin-connection methods.

[0025] like Figure 2 As shown, the discharge circuit in this embodiment includes a monitoring module and a switching module. The monitoring module is used to detect the voltage and current parameters of the discharge circuit, and the switching module is used to open and close the circuit according to the values ​​of the voltage or current parameters to protect the chip.

[0026] The monitoring module includes a DW01 chip. When the voltage in the discharge circuit exceeds the maximum voltage threshold or falls below the minimum voltage threshold, the DW01 chip shuts off the discharge circuit; when the current in the discharge circuit exceeds the maximum current threshold, the DW01 chip shuts off the discharge circuit.

[0027] The switching module includes an AO4407 chip, which controls the AO4407 chip to open the discharge circuit to achieve normal discharge when the voltage in the discharge circuit is between the highest voltage threshold and the lowest voltage threshold, and when the current in the discharge circuit is lower than the highest current threshold.

[0028] Pin 1 of the DW01 chip is connected to pin 4 of the AO4407 chip via an AO3401 chip; pin 2 of the DW01 chip is connected to pins 1, 2, and 3 of the AO4407 chip via another AO3401 chip, and pin 2 of the DW01 chip is connected to a relay via resistor R10; pin 5 of the DW01 chip is connected to Vin; pins 5, 6, 7, and 8 of the AO4407 chip are all connected to Vout.

[0029] Pins 1, 2, and 3 of the AO4407 chip are connected to Vin.

[0030] In actual use, for example, when the cell voltage of the DW01 chip is between 2.5V and 4.3V, its relevant pins output a high level, which makes the switching transistor in the AO4407 in the conducting state. At this time, the negative terminal of the chip is directly connected to the output terminal of the protection board. The current can flow from the drain of the chip through the load and the switching transistor inside the protection chip back to the negative terminal of the chip source, so as to achieve normal discharge.

[0031] like Figure 3 As shown, under test conditions of 550V, short-circuit time of 2µs, and drive voltage of 13V, a short-circuit current test was performed, and the maximum current measured was 955A; Figure 4As shown, a short-circuit current test was conducted at 600V, with a short-circuit time of 2µs, a drive voltage of 13V, and a protection setting of 200A. The maximum current value measured was 940A.

[0032] Experiments show that the short-circuit protection of this system can reach 1000A and 650ns, which can guarantee the lifespan of the socket and ensure the reliability of the chip after KGD testing.

[0033] According to a second aspect of this application, a KGD high-temperature testing method using the above-described KGD high-temperature testing system is provided, comprising the following steps:

[0034] Step 1: Fix the chip to the test socket and control the relay to connect the test socket to the test loop for testing; the chip is flipped upside down in the test socket for testing, so that the drain (G) and source (S) of the chip are in direct contact through the ping pin, thereby reducing the distance between the gate and source to the shortest distance and reducing the interference loop.

[0035] Step 2: After the test is completed, the control relay will switch the test socket to the discharge circuit;

[0036] Step 3: The discharge circuit detects the voltage and current parameters. When the voltage and current parameters are within the threshold range, the discharge is activated.

[0037] According to one embodiment of this application, the beneficial effects of using this KGD high-temperature testing system are as follows: by adding a discharge circuit and setting a current limit, the short-circuit current can be completely limited, thereby better protecting the test socket; it solves the problems of large noise in the traditional test loop, lack of current limiting optimization in the test loop, which leads to thermal breakdown of the chip and damage to the test socket, thereby improving testing efficiency and chip testing reliability, and reducing the repair cost of the test socket.

[0038] It should be noted that the above detailed descriptions are exemplary and intended to provide further explanation of this application. Unless otherwise specified, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains.

[0039] It should be noted that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the exemplary embodiments according to this application. As used herein, the singular form is intended to include the plural form as well, unless the context clearly indicates otherwise. Furthermore, it should be understood that when the terms "comprising" and / or "including" are used in this specification, they indicate the presence of features, steps, operations, devices, components, and / or combinations thereof.

[0040] It should be noted that the terms "first," "second," etc., used in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such terms can be used interchangeably where appropriate so that the embodiments of this application described herein can be implemented in sequences other than those illustrated or described herein.

[0041] Furthermore, the terms “comprising” and “having”, and any variations thereof, are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or apparatus that includes a series of steps or units is not necessarily limited to those steps or units that are explicitly listed, but may include other steps or units that are not explicitly listed or that are inherent to such process, method, product, or apparatus.

[0042] For ease of description, spatial relative terms such as "above," "on top of," "on the upper surface of," "above," etc., are used herein to describe the spatial positional relationship of a device or feature as shown in the figures to other devices or features. It should be understood that spatial relative terms are intended to encompass different orientations in use or operation beyond the orientation of the device as described in the figures. For example, if the device in the figures were inverted, a device described as "above" or "on top of" other devices or structures would subsequently be positioned as "below" or "under" other devices or structures. Thus, the exemplary term "above" can include both "above" and "below." The device may also be positioned in other different ways, such as rotated 90 degrees or in other orientations, and the spatial relative descriptions used herein will be interpreted accordingly.

[0043] In the detailed description above, reference has been made to the accompanying drawings, which form part of this document. In the drawings, similar symbols typically identify similar parts unless the context otherwise indicates otherwise. The illustrated embodiments described in the detailed specification, drawings, and claims are not intended to be limiting. Other embodiments may be used and other changes may be made without departing from the spirit or scope of the subject matter presented herein.

[0044] The above are merely preferred embodiments of this utility model and are not intended to limit the scope of this utility model. Various modifications and variations can be made to this utility model by those skilled in the art. Any modifications, equivalent substitutions, or improvements made within the spirit and principles of this utility model should be included within the protection scope of this utility model.

Claims

1. A KGD high-temperature testing system, characterized in that, The device includes a test socket, on which a test loop and a discharge circuit are connected in parallel. The test loop and the discharge circuit are connected to the test socket via a relay, which controls the test socket to be connected to the test loop or the discharge circuit, respectively.

2. The KGD high-temperature testing system according to claim 1, characterized in that, The chip to be tested is installed upside down onto the test socket.

3. The KGD high-temperature testing system according to claim 1, characterized in that, The discharge circuit includes a monitoring module and a switching module. The monitoring module is used to detect the voltage and current parameters of the discharge circuit, and the switching module is used to open and close the circuit according to the values ​​of the voltage or current parameters to protect the chip.

4. The KGD high-temperature testing system according to claim 3, characterized in that, The monitoring module includes a DW01 chip, which is used to shut down the discharge circuit when the voltage in the discharge circuit exceeds the maximum voltage threshold or falls below the minimum voltage threshold; and to shut down the discharge circuit when the current in the discharge circuit exceeds the maximum current threshold.

5. The KGD high-temperature testing system according to claim 4, characterized in that, The switching module includes an AO4407 chip, which is used to control the AO4407 chip to open the discharge circuit to achieve normal discharge when the voltage in the discharge circuit is between the highest voltage threshold and the lowest voltage threshold, and when the current in the discharge circuit is lower than the highest current threshold.

6. The KGD high-temperature testing system according to claim 5, characterized in that, Pin 1 of the DW01 chip is connected to pin 4 of the AO4407 chip via an AO3401 chip; pin 2 of the DW01 chip is connected to pins 1, 2, and 3 of the AO4407 chip via another AO3401 chip, and pin 2 of the DW01 chip is connected to a relay via resistor R10; pin 5 of the DW01 chip is connected to Vin; pins 5, 6, 7, and 8 of the AO4407 chip are all connected to Vout.

7. The KGD high-temperature testing system according to claim 6, characterized in that, Pins 1, 2, and 3 of the AO4407 chip are connected to Vin.

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