Apparatus for synchronizing data input signal and clock input signal

Abstract

An apparatus for synchronizing a data input signal and a clock input signal is provided. The device comprises a receiving circuit, a processing circuit and a transmission circuit. The receiving circuit generates a clock input signal and includes a plurality of receivers, each receiving a data input signal and generating a first data output signal. Each receiver includes a delay line that does not include a duty cycle corrector (DCC), has a predetermined number of delay elements, and introduces a propagation delay to the data input signal by a fixed amount that substantially matches the propagation delay of the clock input signal. The processing circuit processes the first data output signal and generates a second data output signal. And the transmission circuit sends the second data output signal to a data signal receiving device.

Description

Technical Field

[0001] This disclosure relates to an apparatus, and more particularly to an apparatus for synchronizing data input signals and clock input signals. Background Technology

[0002] The device is typically configured to receive a data input signal from a data signal generating device and a clock input signal from a clock signal generating device, process the data input signal to generate a data output signal, and transmit the data output signal to a data signal receiving device. Synchronization within the device is generally crucial for the proper functioning of such devices. Utility Model Content

[0003] In one embodiment of this disclosure, the apparatus for synchronizing a data input signal and a clock input signal includes a receiving circuit, a processing circuit, and a transmitting circuit. The receiving circuit generates a clock input signal. The receiving circuit includes a plurality of receivers, each configured to receive the data input signal and generate a first data output signal. Each receiver includes a first delay line. The first delay line does not include a duty cycle corrector, has a predetermined number of delay components, and introduces a propagation delay to the data input signal by a fixed amount. The fixed amount substantially matches the propagation delay of the clock input signal. The processing circuit processes the first data output signal and generates a second data output signal. The transmitting circuit transmits the second data output signal to the data signal receiving apparatus.

[0004] In one embodiment of this disclosure, the apparatus for synchronizing a data input signal and a clock input signal includes a receiving circuit, a processing circuit, and a transmitting circuit. The receiving circuit includes a receiver. The receiver receives the data input signal and generates a clock input signal and a first data output signal. The receiver includes a delay line. The delay line is configured to receive a control input signal and introduce a propagation delay to the data input signal through a variation. The variation varies with the control input signal and substantially matches the propagation delay of the clock input signal. The processing circuit processes the first data output signal and generates a second data output signal. The transmitting circuit transmits the second data output signal to the data signal receiving apparatus. Attached Figure Description

[0005] All aspects of this disclosure can be best understood by referring to the accompanying drawings and the following detailed description:

[0006] Figure 1A This is a block diagram of an exemplary embodiment of a device according to one embodiment of the present disclosure;

[0007] Figure 1B This is a timing diagram illustrating an exemplary embodiment of the relationship between a data input signal and a clock input signal according to an embodiment of this disclosure;

[0008] Figure 2A This is a block diagram of a first exemplary embodiment of the receiving circuit of an apparatus according to an embodiment of the present disclosure;

[0009] Figure 2B This is another timing diagram illustrating an exemplary embodiment of the relationship between data input signals and clock input signals according to an embodiment of this disclosure;

[0010] Figure 3 This is a flowchart of a first exemplary embodiment of a method for synchronizing a data input signal and a clock input signal, according to an embodiment of the present disclosure.

[0011] Figure 4 This is a block diagram of a second exemplary embodiment of the receiving circuit of an apparatus according to an embodiment of the present disclosure;

[0012] Figure 5 This is a flowchart of a second exemplary embodiment of a method for synchronizing data input signals and clock input signals, according to one embodiment of the present disclosure;

[0013] Figure 6 This is a block diagram of a third exemplary embodiment of the receiving circuit of an apparatus according to an embodiment of the present disclosure;

[0014] Figure 7 This is a flowchart of a third exemplary embodiment of a method for synchronizing data input signals and clock input signals, according to an embodiment of the present disclosure;

[0015] Figure 8 This is a block diagram of a fourth exemplary embodiment of the receiving circuit of an apparatus according to an embodiment of the present disclosure;

[0016] Figure 9 This is a flowchart of a fourth exemplary embodiment of a method for synchronizing a data input signal and a clock input signal, according to an embodiment of the present disclosure;

[0017] Figure 10 This is a block diagram of a fifth exemplary embodiment of the receiving circuit of a device according to an embodiment of the present disclosure; and

[0018] Figure 11 This is a flowchart of a fifth exemplary embodiment of a method for synchronizing data input signals and clock input signals, according to an embodiment of the present disclosure.

[0019] Explanation of reference numerals in the attached figures

[0020] 100: Device

[0021] 110: Receiving circuit

[0022] 120: Processing circuit

[0023] 130: Transmission circuit

[0024] 210: Clock Tree

[0025] 220: Receiver

[0026] 230: Amplifier

[0027] 240: Correction circuit

[0028] 250: Distribution Network

[0029] 260: Amplifier

[0030] 270: Delay circuit

[0031] 280: Data Input / Output (I / O) Circuit

[0032] 270a, 290a: First delay line

[0033] 270b, 290b: Second delay line

[0034] 290: Control signal generation circuit

[0035] 290c: Phase detector

[0036] 290d: Controller

[0037] 300, 500, 700, 900, 1100: Method

[0038] 310~380, 510~560, 710~770, 910~970, 1110~1160: Operation

[0039] clkin, clkin', clkin", clkin[0]-clkin[n]: Clock input signals

[0040] ctrlin: Control input signal

[0041] Din, Din[0]-Din[n]: Data input signals

[0042] Dout, Dout[0]-Dout[n]: Data output signals

[0043] Dout': Data output signal

[0044] pdout: Phase difference Detailed Implementation

[0045] The following disclosure provides numerous different embodiments or examples for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, the formation of a first feature on or above a second feature may include embodiments where the first and second features are in direct contact, and may also include embodiments where an additional feature is formed between the first and second features such that the first and second features may not be in direct contact. Furthermore, reference numerals and / or letters may be repeated throughout the disclosure in various examples. Repetition for simplicity and clarity does not, in itself, indicate a relationship between the various embodiments and / or configurations.

[0046] The apparatus includes a receiving circuit that receives a data input signal and a clock input signal. In one embodiment, the receiving circuit generates high-level and low-level portions of a data input signal, which serve as a data output signal, at the rising and falling edges of the clock input signal. In some implementations, the alignment between the high-level and low-level portions of the data input signal and the rising and falling edges of the clock input signal occurs undesirably only after a significant synchronization delay. Specifically, the receiving circuit receives the data input signal such that the clock input signal is in its inactive (or low) state, or the rising (or falling) edge of the clock input signal is aligned with the transition (rising or falling) edge of the data input signal. Therefore, the high-level and low-level portions of the data input signal gradually align or synchronize with the rising and falling edges of the clock input signal. This delayed alignment or synchronization leads to inaccurate operation of subsequent processing of the data output signal.

[0047] The methods disclosed herein provide apparatus and methods for aligning the high and low portions of a data input signal with the rising and falling edges of a clock input signal without significant synchronization delay, for example, between about 0.2 picoseconds (ps) and about 1.2 picoseconds. For example, the apparatus and methods herein ensure that the alignment or synchronization between the high and low portions of the data input signal and the rising and falling edges of the clock input signal begins immediately upon receipt of the data input signal, i.e., from the first high or low portion of the data input signal.

[0048] In some exemplary embodiments, the apparatus and method include a receiving circuit, for example... Figure 1AThe receiving circuit 110 receives a data input signal (Din) and a clock input signal (clkin), and generates high-level and low-level portions of the data input signal (Din) during the rising and falling edges of the clock input signal (clkin) to serve as a data output signal (Dout). The receiving circuit 110 facilitates alignment between the high-level and low-level portions of the data input signal (Din) and the rising and falling edges of the clock input signal (clkin) without introducing significant synchronization delay. For example, the receiving circuit 110 includes a delay circuit, such as... Figure 2A The delay circuit 270 introduces a propagation delay to the data input signal (Din), which is substantially matched to the propagation delay of the clock input signal (clkin), in a manner described below.

[0049] Figure 1A This is a block diagram of an exemplary embodiment of the apparatus 100 according to the present disclosure. Figure 1B This is a timing diagram illustrating an exemplary embodiment of the relationship between a data input signal (Din) and a clock input signal (clkin) according to embodiments of this disclosure. Figure 1A As shown, device 100 includes a receiving circuit 110, a processing circuit 120, and a transmission circuit 130. The receiving circuit 110 receives a data input signal (Din), which includes multiple data input signals (Din[0]-Din[n]), received, for example, from a data signal generating device external to device 100. Simultaneously, the receiving circuit 110 receives a clock input signal (clkin), which includes multiple clock input signals (clkin[0]-clkin[n]), received, for example, from a clock signal generating device external to device 100. To ensure synchronization, the receiving circuit 110 substantially matches the propagation delay of the data input signal (Din) with the propagation delay of the clock input signal (clkin). Subsequently, the receiving circuit 110 generates the high and low levels of the data input signal (Din) at the rising and falling edges of the clock input signal (clkin) as a data output signal (Dout). Because the propagation delay of the data input signal (Din) is substantially matched with the propagation delay of the clock input signal (clkin), further reference... Figure 1BTherefore, the receiving circuit 110 aligns the high and low levels of the data input signal (Din) with the rising and falling edges of the clock input signal (clkin) without significant synchronization delay. That is, the alignment or synchronization between the high and low levels of the data input signal (Din) and the rising and falling edges of the clock input signal (clkin) begins immediately after the receiving circuit 110 receives the data input signal (Din), i.e., from the first high or low level portion of the data input signal (Din). The processing circuit 120 processes the data output signal (Dout) and generates a data output signal (Dout'). The transmission circuit 130 transmits the data output signal (Dout') to, for example, a data signal receiving device external to device 100.

[0050] In one embodiment, the device 100 omits at least one of the processing circuit 120 and the transmission circuit 130. In this embodiment, at least one of the processing circuit 120 and the transmission circuit 130 is located outside the device 100.

[0051] Figure 1A The circuitry shown can take many forms. For example, in some exemplary embodiments, the receiving circuitry 110 conforms to specifications for inter-chip interconnects (and serial buses), such as the Universal Chipset Interconnect Fast (UCIE) standard. Examples of the processing circuitry 120 include a microprocessor, a graphics processing unit (GPU), a digital signal processor (DSP), memory devices (RAM and ROM), and an application-specific integrated circuit (ASIC).

[0052] Figure 2A This is a block diagram of an embodiment of the receiving circuit 110 of the apparatus 100 according to the present disclosure. Figure 2A As shown, the receiving circuit 110 includes a clock tree 210 and a plurality of receivers 220. In another embodiment, the clock tree 210 is omitted from the receiving circuit 110. The clock tree 210 includes an amplifier 230, a correction circuit 240, a distribution network 250, and a control signal generation circuit 290. The amplifier 230 receives a clock input signal (clkin), for example, from a clock signal generation device external to device 100, and generates an amplified version of the clock input signal (clkin).

[0053] The correction circuit 240 adjusts the amplified version of the clock input signal (clkin) and generates a clock input signal (clkin'). For example, the correction circuit 240 may include a duty cycle corrector (DCC) that corrects the duty cycle of the amplified version of the clock input signal (clkin) and generates a clock input signal (clkin') with approximately 50% duty cycle.

[0054] Distribution network 250 includes a trunk, multiple branches, multiple clock leaf nodes, and multiple buffers. The trunk receives a clock input signal (clkin'). The multiple branches extend from the trunk and generate multiple clock input signals (clkin") based on the clock input signal (clkin'). The multiple clock leaf nodes generate multiple clock input signals (clkin[0]-clkin[n]). Each of the multiple buffers is connected between a corresponding node in the multiple branches and a corresponding node in the multiple clock leaf nodes, and amplifies a corresponding node in the multiple clock input signals (clkin"). Each amplified clock input signal (clkin") serves as a corresponding node in the multiple clock input signals (clkin[0]-clkin[n]).

[0055] In an alternative embodiment, the correction circuit 240 generates a pair of clock input signals (clkin'). In this alternative embodiment, the correction circuit 240 includes a phase error corrector, such as a quadrature error corrector (QEC), which corrects for the phase error between the clock input signals (clkin').

[0056] Reference Figure 2B This is a timing diagram illustrating another exemplary embodiment of the relationship between a data input signal and a clock input signal, according to one embodiment of the present disclosure. The control signal generation circuit 290 aligns or synchronizes the rising edge of the clock input signal (clkin) with the transition (rising or falling) edge of the data input signal (Din). For example, as... Figure 2A As shown, the control signal generation circuit 290 includes a first delay line 290a and a second delay line 290b, a phase detector 290c, and a controller 290d. The first delay line 290a introduces a fixed amount of propagation delay to the amplified version of the clock input signal (clkin). In some embodiments, the first delay line 290a includes a predetermined number of delay components (e.g., buffers and inverters). In these embodiments, the first delay lines 290a of at least two receivers 220 have the same number of delay components. In other embodiments, the first delay lines 290a of at least two receivers 220 have different numbers of delay components.

[0057] The second delay line 290b mitigates process, voltage, and temperature (PVT) related issues. For example, the second delay line 290b fine-tunes the propagation delay of the first delay line 290a. In this exemplary embodiment, the second delay line 290b receives a control input signal (ctrlin) and introduces a propagation delay through a variation that changes with the control input signal (ctrlin). In some embodiments, the second delay line 290b includes a digitally-controlled delay line (DCDL).

[0058] A phase detector 290c is connected between the clock tree leaf of the distribution network 250 and the output of the second delay line 290b, compares the phase of an amplified version of the clock input signal (clkin) with the phase of an amplified version of the clock input signal (clkin), and generates a phase difference (pdout) based on the comparison result. A controller 290d is connected to the phase detector 290c and generates a control input signal (ctrlin) based on the phase difference (pdout). For example, the controller 290d includes a finite state machine (FSM). The systems and methods described herein consider various other configurations of the clock tree 210. For example, in another embodiment, at least one of the amplifier 230, correction circuitry 240, distribution network, and control signal generation circuitry 290 is omitted from the clock tree 210.

[0059] like Figure 2A As shown, each receiver 220 receives its own data input signals (Din[0]-Din[n]), such as data signal generating devices outside the device 100, and its own clock input signals (clkin[0]-clkin[n]) from the clock tree 210, and generates multiple data output signals (Dout[0]-Dout[n]), each corresponding to its own data input signal (Din[0]-Din[n]). Since the receivers 220 are identical or similar in structure and operation, only one of the receivers 220 will be described below.

[0060] Receiver 220 includes amplifier 260, delay circuit 270 and data input / output (I / O) circuit 280. Amplifier 260 receives data input signal (Din[0]) and generates an amplified version of data input signal (Din[0]).

[0061] The delay circuit 270 essentially matches the propagation delay of the data input signal (Din[0]) to the propagation delay of the clock input signal (clkin[0]). For example, the delay circuit 270 includes a first delay line 270a and a second delay line 270b. The first delay line 270a introduces a fixed amount of propagation delay to the amplified version of the data input signal (Din[0]). In some embodiments, the first delay line 270a includes a predetermined number of delay components (e.g., buffers and inverters). In these embodiments, the first delay lines 270a of at least two receivers 220 have the same number of delay components. In other embodiments, the first delay lines 270a of at least two receivers 220 have different numbers of delay components.

[0062] The second delay line 270b mitigates problems associated with PVT. For example, the second delay line 270b fine-tunes the propagation delay of the first delay line 270a. In this exemplary embodiment, the second delay line 270b receives a control input signal (ctrlin) and introduces a propagation delay through a variation that changes with the control input signal (ctrlin). In a particular embodiment, the second delay line 270b includes a DCDL.

[0063] The data input / output circuit 280 receives an amplified version of the data input signal (Din[0]) and a clock input signal (clkin[0]), and generates the high-level and low-level portions of the data input signal (Din[0]) as the data output signal (Dout[0]) at the rising and falling edges of the clock input signal (clkin[0]). The propagation delay of the data input signal (Din[0]) is substantially matched to the propagation delay of the clock input signal (clkin[0]) by the delay circuit 270, and the data input / output circuit 280 aligns the high-level and low-level portions of the data input signal (Din[0]) with the rising and falling edges of the clock input signal (clkin[0]) without significant synchronization delay. That is, this alignment or synchronization begins immediately when the data input / output circuit 280 receives the amplified version of the data input signal (Din[0]), i.e., from the first high-level or low-level portion of the data input signal (Din[0]).

[0064] In some embodiments, the data input / output circuit 280 includes a sense amplifier. In other embodiments, the data input / output circuit 280 includes a de-serializer. In these other embodiments, the data input signal (Din[0]) is in sequential form, and the de-serializer converts the data input signal (Din[0]) into parallel form.

[0065] Processing circuit 120 processes the data output signal (Dout[0]) and generates a data output signal (Dout'). Transmission circuit 130 transmits the data output signal (Dout') to a data signal receiving device, for example, located outside the device 100.

[0066] In one embodiment, the receiver 220 omits at least one of the amplifier 260, the delay circuit 270, and the data input / output circuit 280.

[0067] Figure 3 This is a flowchart illustrating an embodiment of a method 300 for aligning or synchronizing the low-level and high-level portions of a data input signal with the rising and falling edges of a clock input signal, according to the present disclosure. For ease of understanding, please refer to... Figure 1A , Figure 1B , Figure 2A and Figure 2B Example method 300 is described further. It should be understood that method 300 is applicable to... Figure 1A , Figure 1B , Figure 2A and Figure 2B Other than the structure. Furthermore, it should be understood that in another embodiment of method 300, additional operations may be provided before, during, and after method 300, and some of the operations described below may be replaced or eliminated.

[0068] In operation 310, clock tree 210 receives a clock input signal (clkin), such as from a clock signal generating device external to device 100, and generates multiple clock input signals (clkin[0]-clkin[n]). In this exemplary embodiment, operation 310 includes: amplifier 230 amplifying the clock input signal (clkin); correction circuit 240 adjusting the duty cycle of the amplified clock input signal (clkin) and generating a clock input signal (clkin') having approximately 50% of the duty cycle; distribution network 250 generating multiple clock input signals (clkin[0]-clkin[n]) based on the clock input signal (clkin'); and control signal generation circuit 290 aligning or synchronizing the rising edge of the clock input signal (clkin[0]) to the transition (rising or falling) edge of the data input signal (Din[0]). In another embodiment, operation 310 further includes correction circuit 240 minimizing or eliminating phase error between a pair of clock input signals (clkin').

[0069] In operation 320, amplifier 260 receives a data input signal (Din[0]), for example, from a data signal generating device outside device 100, and generates an amplified version of the data input signal (Din[0]).

[0070] In operation 330, the first delay line 270a introduces a fixed or predetermined amount of propagation delay to the amplified version of the data input signal (Din[0]).

[0071] In operation 340, the control signal generation circuit 290 generates a control input signal (ctrlin).

[0072] In operation 350, the second delay line 270b receives the control input signal (ctrlin) and fine-tunes the propagation delay of the first delay line 270a according to the change in the control input signal (ctrlin).

[0073] In operation 360, the data input / output circuit 280 receives an amplified version of the data input signal (Din[0]) and a clock input signal (clkin[0]), and generates the high-level and low-level portions of the data input signal (Din[0]) as the data output signal (Dout[0]) during the rising and falling edges of the clock input signal (clkin[0]). The propagation delay of the data input signal (Din[0]) is substantially matched with the propagation delay of the clock input signal (clkin[0]) by the delay circuit 270, and the data input / output circuit 280 aligns the high-level and low-level portions of the data input signal (Din[0]) with the rising and falling edges of the clock input signal (clkin[0]) without significant synchronization delay. In other words, the data input / output circuit 280 generates a data output signal (Dout) such that the alignment or synchronization between the high-level and low-level portions of the data input signal (Din[0]) and the rising and falling edges of the clock input signal (clkin[0]) occurs immediately when the data input / output circuit 280 receives the data input signal (Din[0]), i.e., starting from the first high-level or low-level portion of the data input signal (Din[0]).

[0074] In operation 370, processing circuit 120 processes the data output signal (Dout[0]) and generates a data output signal (Dout'). In operation 380, transmission circuit 130 transmits the data output signal (Dout') to, for example, a data signal receiving device outside of device 100.

[0075] Figure 4 This is a block diagram of a further exemplary embodiment of the receiving circuit 410 of the apparatus 100 according to the present disclosure. Figure 4 As shown, the exemplary receiving circuit 410 and Figure 2AThe exemplary receiving circuit 110 differs from the receiving circuit 410 in that the delay circuit 270 of at least one receiver 220 of the receiving circuit 410 is implemented with a first delay line 270a and the second delay line 270b is omitted. The clock tree 210 omits the control signal generation circuit 290. In this exemplary embodiment, as with the receiving circuit 110, the first delay line 270a of the receiving circuit 410 introduces a fixed or predetermined amount of propagation delay to the amplified version of the data input signal (Din[0]). However, unlike the receiving circuit 110, the receiving circuit 410 does not fine-tune the propagation delay of the first delay line 270a.

[0076] In some embodiments, the first delay line 270a includes a predetermined number of delay components (e.g., buffers and inverters). In these embodiments, the first delay lines 270a of at least two receivers 220 have different numbers of delay components. In other embodiments, the first delay lines 270a of at least two receivers 220 have the same number of delay components.

[0077] Figure 5 This is a flowchart illustrating a further exemplary embodiment of a method 500 for aligning or synchronizing the low-level and high-level portions of a data input signal to the rising and falling edges of a clock input signal, according to this disclosure. For ease of understanding, refer to... Figure 1A , Figure 1B , Figure 2B and Figure 4 Example method 500 is described further. It should be understood that method 500 is applicable to... Figure 1A , Figure 1B , Figure 2B and Figure 4 Other than the structure. Furthermore, it should be understood that in another embodiment of method 500, additional operations may be provided before, during, and after method 500, and some of the operations described below may be replaced or eliminated.

[0078] In operation 510, clock tree 210 receives a clock input signal (clkin), such as from a clock signal generating device external to device 100, and generates multiple clock input signals (clkin[0]-clkin[n]). In this exemplary embodiment, operation 510 includes: amplifier 230 amplifying the clock input signal (clkin); correction circuit 240 adjusting the duty cycle of the amplified clock input signal (clkin) and generating a clock input signal (clkin') having approximately 50% of the duty cycle; and distribution network 250 generating multiple clock input signals (clkin[0]-clkin[n]) based on the clock input signal (clkin'). In another embodiment, operation 510 further includes correction circuit 240 minimizing or eliminating phase error between a pair of clock input signals (clkin').

[0079] In operation 520, amplifier 260 receives a data input signal (Din[0]), for example, from a data signal generating device outside device 100, and generates an amplified version of the data input signal (Din[0]).

[0080] In operation 530, the first delay line 270a introduces a fixed or predetermined amount of propagation delay to the amplified version of the data input signal (Din[0]).

[0081] In operation 540, the data input / output circuit 280 receives an amplified version of the data input signal (Din[0]) and a clock input signal (clkin[0]), and generates the high-level and low-level portions of the data input signal (Din[0]) as the data output signal (Dout[0]) at the rising and falling edges of the clock input signal (clkin[0]). The propagation delay of the data input signal (Din[0]) is substantially matched with the propagation delay of the clock input signal (clkin[0]) by the delay circuit 270, and the data input / output circuit 280 aligns the high-level and low-level portions of the data input signal (Din[0]) with the rising and falling edges of the clock input signal (clkin[0]) without significant synchronization delay. In other words, the data input / output circuit 280 generates a data output signal (Dout) such that the alignment or synchronization between the high-level and low-level portions of the data input signal (Din[0]) and the rising and falling edges of the clock input signal occurs immediately when the data input / output circuit 280 receives the data input signal (Din[0]), i.e., starting from the first high-level or low-level portion of the data input signal (Din[0]).

[0082] In operation 550, processing circuit 120 processes the data output signal (Dout[0]) and generates a data output signal (Dout'). In operation 560, transmission circuit 130 transmits the data output signal (Dout') to, for example, a data signal receiving device outside of device 100.

[0083] Figure 6 This is a block diagram of a further exemplary embodiment of the receiving circuit 610 of the apparatus 100 according to the present disclosure. Figure 6 As shown, the exemplary receiving circuit 610 and Figure 2AThe exemplary receiving circuit 110 differs in that the delay circuit 270 of at least one receiver 220 of the receiving circuit 610 is implemented with a second delay line 270b, and the first delay line 270a is omitted. In this exemplary embodiment, the second delay line 270b of the receiving circuit 610 introduces a propagation delay to the amplified version of the data input signal (DSin[0]) by a variation that varies with the control input signal (ctrlin). Unlike the receiving circuit 110, the receiving circuit 610 does not introduce a fixed or predetermined amount of propagation delay to the amplified version of the data input signal (Din[0]).

[0084] Figure 7 This is a flowchart of a further exemplary embodiment of a method 700 for aligning or synchronizing the low-level and high-level portions of a data input signal with the rising and falling edges of a clock input signal according to the present disclosure. For ease of understanding, refer to... Figure 1A , Figure 1B , Figure 2B and Figure 6 Example method 700 is described further. It should be understood that method 700 is applicable to... Figure 1A , Figure 1B , Figure 2B and Figure 6 Other than the structure. Furthermore, it should be understood that in alternative embodiments of method 700, additional operations may be provided before, during, and after method 700, and some of the operations described below may be replaced or eliminated.

[0085] In operation 710, clock tree 210 receives clock input signals (clkin), such as those from a clock signal generating device external to device 100, and generates multiple clock input signals (clkin[0]-clkin[n-1]). In this exemplary embodiment, operation 710 includes: amplifier 230 amplifying the clock input signal (clkin); correction circuit 240 adjusting the duty cycle of the amplified clock input signal (clkin) and generating a clock input signal (clkin') with approximately 50% duty cycle; distribution network 250 generating multiple clock input signals (clkin[0]-clkin[n]) based on the clock input signal (clkin'); and control signal generation circuit 290 aligning or synchronizing the rising edge of the clock input signal (clkin[0]) with the transition (rising or falling) edge of the data input signal (Din[0]). In another embodiment, operation 710 further includes correction circuit 240 minimizing or eliminating phase error between a pair of clock input signals (clkin').

[0086] In operation 720, amplifier 260 receives a data input signal (Din[0]), for example, from a data signal generating device outside device 100, and generates an amplified version of the data input signal (Din[0]).

[0087] In operation 730, the control signal generation circuit 290 generates a control input signal (ctrlin).

[0088] In operation 740, the second delay line 270b receives the control input signal (ctrlin) and introduces a propagation delay through a variable amount of an amplified version of the data input signal (Din[0]), the variable amount of which varies with the control input signal (ctrlin).

[0089] In operation 750, the data input / output circuit 280 receives an amplified version of the data input signal (Din[0]) and a clock input signal (clkin[0]), and generates the high-level and low-level portions of the data input signal (Din[0]) as the data output signal (Dout[0]) at the rising and falling edges of the clock input signal (clkin[0]). The propagation delay of the data input signal (Din[0]) is substantially matched with the propagation delay of the clock input signal (clkin[0]) by the delay circuit 270, and the data input / output circuit 280 aligns the high-level and low-level portions of the data input signal (Din[0]) with the rising and falling edges of the clock input signal (clkin[0]) without significant synchronization delay. In other words, the data input / output circuit 280 generates a data output signal (Dout) such that the alignment or synchronization between the high-level and low-level portions of the data input signal (Din[0]) and the rising and falling edges of the clock input signal occurs immediately when the data input / output circuit 280 receives the data input signal (Din[0]), i.e., starting from the first high-level or low-level portion of the data input signal (Din[0]).

[0090] In operation 760, processing circuit 120 processes the data output signal (Dout[0]) and generates a data output signal (Dout'). In operation 770, transmission circuit 130 transmits the data output signal (Dout') to, for example, a data signal receiving device located outside device 100.

[0091] Figure 8 This is a block diagram of a further exemplary embodiment of the receiving circuit 810 of the apparatus 100 according to the present disclosure. Figure 8 As shown, the exemplary receiving circuit 810 and Figure 2AThe exemplary receiving circuit 110 differs from the clock tree 210 in that it is not equipped with a control signal generation circuit 290. In this exemplary embodiment, similar to the receiving circuit 110, the receiving circuit 810 introduces a fixed or predetermined propagation delay into an amplified version of the data input signal (Din[0]) and fine-tunes the propagation delay of the first delay line 270a according to the amount of change in the control input signal (ctrlin). Unlike the receiving circuit 110, the receiving circuit 810 receives the control input signal (ctrlin) from a control signal generation device external to the device 100.

[0092] Figure 9 This is a flowchart of a further exemplary embodiment of a method 900 for aligning or synchronizing the low-level and high-level portions of a data input signal to the rising and falling edges of a clock input signal according to the present disclosure. For ease of understanding, exemplary method 900 refers to... Figure 1A , Figure 1B , Figure 2B and Figure 8 Further description. It should be understood that Method 900 applies to... Figure 1A , Figure 1B , Figure 2B and Figure 8 Other than the structure. Furthermore, it should be understood that in another embodiment of method 900, additional operations may be provided before, during, and after method 900, and some of the operations described below may be replaced or eliminated.

[0093] In operation 910, clock tree 210 receives clock input signals (clkin), such as those from a clock signal generating device external to device 100, and generates multiple clock input signals (clkin[0]-clkin[n-1]). In this exemplary embodiment, operation 910 includes: amplifier 230 amplifying the clock input signals (clkin); correction circuit 240 adjusting the duty cycle of the amplified clock input signals (clkin) and generating clock input signals (clkin') with approximately 50% duty cycle; and distribution network 250 generating multiple clock input signals (clkin[0]-clkin[n]) based on the clock input signals (clkin'). In another embodiment, operation 910 further includes correction circuit 240 minimizing or eliminating phase errors between pairs of clock input signals (clkin').

[0094] In operation 920, amplifier 260 receives a data input signal (Din[0]), for example, from a data signal generating device outside device 100, and generates an amplified version of the data input signal (Din[0]).

[0095] In operation 930, the first delay line 270a introduces a fixed or predetermined amount of propagation delay to the amplified version of the data input signal (Din[0]).

[0096] In operation 940, the second delay line 270b receives the control input signal (ctrlin) and fine-tunes the propagation delay of the first delay line 270a according to the change in the control input signal (ctrlin).

[0097] In operation 950, the data input / output circuit 280 receives an amplified version of the data input signal (Din[0]) and a clock input signal (clkin[0]), and generates the high-level and low-level portions of the data input signal (Din[0]) as the data output signal (Dout[0]) during the rising and falling edges of the clock input signal (clkin[0]). The propagation delay of the data input signal (Din[0]) is substantially matched with the propagation delay of the clock input signal (clkin[0]) by the delay circuit 270, and the data input / output circuit 280 aligns the high-level and low-level portions of the data input signal (Din[0]) with the rising and falling edges of the clock input signal (clkin[0]) without significant synchronization delay. In other words, the data input / output circuit 280 generates a data output signal (Dout) such that the alignment or synchronization between the high-level and low-level portions of the data input signal (Din[0]) and the rising and falling edges of the clock input signal occurs immediately when the data input / output circuit 280 receives the data input signal (Din[0]), i.e., starting from the first high-level or low-level portion of the data input signal (Din[0]).

[0098] In operation 960, processing circuit 120 processes the data output signal (Dout[0]) and generates a data output signal (Dout'). In operation 970, transmission circuit 130 transmits the data output signal (Dout') to a signal receiving device, for example, located outside device 100.

[0099] Figure 10 This is a block diagram of a further exemplary embodiment of the receiving circuit 1010 of the apparatus 100 according to the present disclosure. Figure 10 As shown, the exemplary receiving circuit 1010 and Figure 2AThe exemplary receiving circuit 110 differs from the standard receiving circuit 1010 in that the delay circuit 270 of at least one receiver 220 of the receiving circuit 1010 is implemented with a second delay line 270b, and the first delay line 270a is omitted. The clock tree 210 omits the control signal generation circuit 290. In this exemplary embodiment, the receiving circuit 1010 introduces a propagation delay to the amplified version of the data input signal (Din[0]) by a variation that varies with the control input signal (ctrlin). Unlike the receiving circuit 110, the receiving circuit 1010 does not introduce a fixed or predetermined propagation delay to the amplified version of the data input signal (Din[0]) and receives the control input signal (ctrlin) from a control signal generation device outside the device 100.

[0100] Figure 11 This is a flowchart of a further exemplary embodiment of a method 1100 for aligning or synchronizing the low-level and high-level portions of a data input signal with the rising and falling edges of a clock input signal according to the present disclosure. For ease of understanding, reference will now be made to... Figure 1A , Figure 1B , Figure 2B and Figure 10 The exemplary method 1100 will be further described. It should be understood that method 1100 is applicable to... Figure 1A , Figure 1B , Figure 2B and Figure 10 Other than the structure. Furthermore, it should be understood that in alternative embodiments of method 1100, additional operations may be provided before, during, and after method 1100, and some of the operations described below may be replaced or eliminated.

[0101] In operation 1110, clock tree 210 receives clock input signals (clkin), for example, from a clock signal generating device external to device 100, and generates multiple clock input signals (clkin[0]-clkin[n-1]). In this exemplary embodiment, operation 1110 includes: amplifier 230 amplifying the clock input signal (clkin); correction circuit 240 adjusting the duty cycle of the amplified clock input signal (clkin) and generating a clock input signal (clkin') having approximately 50% of the duty cycle; and distribution network 250 generating multiple clock input signals (clkin[0]-clkin[n]) based on the clock input signal (clkin'). In an alternative embodiment, operation 1110 further includes correction circuit 240 minimizing or eliminating phase error between a pair of clock input signals (clkin').

[0102] In operation 1120, amplifier 260 receives a data input signal (Din[0]), for example, from a data signal generating device outside device 100, and generates an amplified version of the data input signal (Din[0]).

[0103] In operation 1130, the second delay line 270b receives the control input signal (ctrlin) and introduces a propagation delay into an amplified version of the data input signal (Din[0]), the amount of which varies with the control input signal (ctrlin).

[0104] In operation 1140, the data input / output circuit 280 receives an amplified version of the data input signal (Din[0]) and a clock input signal (clkin[0]), and generates the high-level and low-level portions of the data input signal (Din[0]) as the data output signal (Dout[0]) at the rising and falling edges of the clock input signal (clkin[0]). The propagation delay of the data input signal (Din[0]) is substantially matched with the propagation delay of the clock input signal (clkin[0]) by the delay circuit 270, and the data input / output circuit 280 aligns the high-level and low-level portions of the data input signal (Din[0]) with the rising and falling edges of the clock input signal (clkin[0]) without significant synchronization delay. In other words, the data input / output circuit 280 generates a data output signal (Dout) such that the alignment or synchronization between the high-level and low-level portions of the data input signal (Din[0]) and the rising and falling edges of the clock input signal occurs immediately when the data input / output circuit 280 receives the data input signal (Din[0]), i.e., starting from the first high-level or low-level portion of the data input signal (Din[0]).

[0105] In operation 1150, processing circuit 120 processes the data output signal (Dout[0]) and generates a data output signal (Dout'). In operation 1160, transmission circuit 130 transmits the data output signal (Dout') to a data signal receiving device, for example, located outside device 100.

[0106] The systems and methods described herein include several embodiments. In one embodiment, the disclosed apparatus includes a receiver that receives a data input signal and a clock input signal, and generates a high-level portion and a low-level portion of the data input signal during the rising and falling edges of the clock input signal. The receiver includes a delay circuit that ensures that the high-level and low-level portions of the data input signal are aligned with the rising and falling edges of the clock input signal without introducing a significant synchronization delay. This structure optimizes the performance, power consumption, and area (PPA) of the apparatus.

[0107] In one embodiment, the apparatus includes a receiving circuit, a processing circuit, and a transmitting circuit. The receiving circuit generates a clock input signal and includes a plurality of receivers, each of which receives a data input signal and generates a first data output signal. Each receiver includes a delay line, which does not include a duty cycle corrector (DCC), has a predetermined number of delay components, and introduces a propagation delay to the data input signal by a fixed amount, the fixed amount approximately matching the propagation delay of the clock input signal. The processing circuit processes the first data output signal and generates a second data output signal. The transmitting circuit transmits the second data output signal to the data signal receiving device.

[0108] In one embodiment, the first delay lines of at least two receivers have different numbers of delay components.

[0109] In one embodiment, the device further includes a data input / output circuit. The data input / output circuit receives a data input signal and a clock input signal, and generates a high-level portion and a low-level portion of the data input signal at the rising and falling edges of the clock input signal.

[0110] In one embodiment, the apparatus further includes a second delay line. The second delay line fine-tunes the propagation delay of the first delay line.

[0111] In one embodiment, the second delay line is configured to receive a control input signal and introduce a propagation delay that varies with the control input signal.

[0112] In one embodiment, the apparatus further includes a clock tree. The clock tree includes a correction circuit, a distribution network, and a control signal generation circuit. The correction circuit corrects the duty cycle of a first clock input signal and generates a second clock input signal having approximately 50% of the duty cycle. The distribution network generates a plurality of third clock input signals based on the second clock input signal. The control signal generation circuit generates control input signals.

[0113] In one embodiment, the control signal generation circuit includes a first delay line, a second delay line, a phase detector, and a controller. The first delay line introduces a propagation delay to the first clock input signal. The second delay line fine-tunes the propagation delay of the first delay line. The phase detector compares the phases of the first and second clock input signals and generates a phase difference based on the comparison result. The controller generates a control input signal based on the phase difference.

[0114] In one embodiment, the receiving circuit conforms to the specifications of the Universal Chipplet Interconnection Express (UCIE) standard.

[0115] In another embodiment, the apparatus includes a receiving circuit, a processing circuit, and a transmitting circuit. The receiving circuit includes a receiver that receives a data input signal and generates a clock input signal and a first data output signal. The receiver includes a delay line that receives a control input signal and introduces a propagation delay into the data input signal, the amount of which varies with the control input signal and substantially matches the propagation delay of the clock input signal. The processing circuit processes the first data output signal and generates a second data output signal. The transmitting circuit transmits the second data output signal to the data signal receiving device.

[0116] In one embodiment, the apparatus further includes a clock tree. The clock tree receives a first clock input signal and generates a second clock input signal, and includes control signal generation circuitry configured to generate a control input signal based on the first clock input signal and the second clock input signal.

[0117] In one embodiment, the control signal generation circuit includes a phase detector and a controller. The phase detector compares a data input signal and a clock input signal, and generates a phase difference based on the comparison result. The controller generates a control input signal based on the phase difference.

[0118] In one embodiment, the device further includes a data input / output circuit. The data input / output circuit receives a data input signal and a clock input signal, and generates a high-level portion and a low-level portion of the data input signal as a first data output signal on the rising and falling edges of the clock input signal.

[0119] In one embodiment, the apparatus further includes a clock tree. The clock tree includes a correction circuit and a distribution network. The correction circuit corrects the duty cycle of a first clock input signal and generates a second clock input signal having approximately 50% of the duty cycle. The distribution network generates a plurality of third clock input signals based on the second clock input signal.

[0120] In one embodiment, the apparatus further includes a clock tree. The clock tree includes a correction circuit and a distribution network. The correction circuit corrects a phase error between a first clock input signal and a second clock input signal. The distribution network generates a plurality of third clock input signals based on the first and second clock input signals.

[0121] A method for synchronizing a data input signal and a clock input signal includes: receiving a clock input signal and a data input signal; introducing a predetermined amount of first propagation delay into the data input signal by a first delay line; fine-tuning the first propagation delay by a second delay line; generating a first data output signal based on the data input signal after introducing and fine-tuning the first propagation delay; processing the first data output signal by a processing circuit and generating a second data output signal; and transmitting the second data output signal to a data signal receiving device.

[0122] In one embodiment, generating the first data output signal includes generating a high-level portion and a low-level portion of the data input signal during the rising and falling edges of the clock input signal.

[0123] In one embodiment, fine-tuning the first propagation delay includes receiving a control input signal and introducing a second propagation delay by a change that varies with the control input signal.

[0124] In one embodiment, the method further includes: correcting the duty cycle of a first clock input signal and generating a second clock input signal having approximately 50% of the duty cycle; and generating a plurality of third clock input signals based on the second clock input signal.

[0125] In one embodiment, the method further includes: correcting the phase error between the first clock input signal and the second clock input signal; and generating a plurality of third clock input signals based on the first clock input signal and the second clock input signal.

[0126] In one embodiment, the data input signal is in serial form. Generating the first data output signal includes converting the data input signal into parallel form.

[0127] The foregoing has outlined features of several embodiments to enable those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art should understand that they can readily use this disclosure as a basis to design or modify other processes and structures to achieve the same objectives and / or obtain the same advantages of the embodiments described herein. Those skilled in the art should also recognize that such equivalent structures do not depart from the spirit and scope of this disclosure, and that they can make various changes, substitutions, and modifications without departing from the spirit and scope of this disclosure.

Claims

1. A device for synchronizing data input signals and clock input signals, characterized in that, The device includes: A receiving circuit, configured to generate the clock input signal, includes a plurality of receivers, each receiver configured to receive the data input signal and generate a first data output signal, wherein each of the receivers includes a first delay line, the first delay line excluding a duty cycle corrector, having a predetermined number of delay components, and configured to introduce a propagation delay into the data input signal by a fixed amount, the fixed amount being substantially matched to the propagation delay of the clock input signal. Processing circuitry, configured to process the first data output signal and generate a second data output signal; and The transmission circuit is configured to transmit the second data output signal to the data signal receiving device.

2. The apparatus according to claim 1, characterized in that, The device further includes a data input / output circuit configured to receive the data input signal and the clock input signal, and to generate a high-level portion and a low-level portion of the data input signal at the rising and falling edges of the clock input signal.

3. The apparatus according to claim 1, characterized in that, The device also includes a second delay line configured to fine-tune the propagation delay of the first delay line.

4. The apparatus according to claim 3, characterized in that, The second delay line is configured to receive a control input signal and introduce a propagation delay that varies with the control input signal.

5. The apparatus according to claim 4, characterized in that, The device also includes a clock tree, comprising: The correction circuit is configured to correct the duty cycle of the first clock input signal and generate a second clock input signal with approximately 50% of the duty cycle. The distribution network is configured to generate a plurality of third clock input signals based on the second clock input signal; and A control signal generation circuit is configured to generate the control input signal.

6. The apparatus according to claim 5, characterized in that, The control signal generation circuit includes: A first delay line is configured to introduce a propagation delay to the first clock input signal; The second delay line is configured to fine-tune the propagation delay of the first delay line; A phase detector, configured to compare the phase of the first clock input signal and the phase of the second clock input signal, and generate a phase difference based on the result of the comparison; and The controller is configured to generate a control input signal based on the phase difference.

7. A device for synchronizing data input signals and clock input signals, characterized in that, The device includes: A receiving circuit includes a receiver configured to receive a data input signal and generate the clock input signal and a first data output signal, wherein the receiver includes a delay line configured to receive a control input signal and introduce a propagation delay into the data input signal through a variation that varies with the control input signal and substantially matches the propagation delay of the clock input signal. Processing circuitry, configured to process the first data output signal and generate a second data output signal; and The transmission circuit is configured to transmit the second data output signal to the data signal receiving device.

8. The apparatus according to claim 7, characterized in that, The device further includes a clock tree configured to receive a first clock input signal and generate a second clock input signal, and includes a control signal generation circuit configured to generate the control input signal based on the first clock input signal and the second clock input signal.

9. The apparatus according to claim 7, characterized in that, The device also includes a clock tree, which comprises: A correction circuit, configured to correct the duty cycle of the first clock input signal and generate a second clock input signal having approximately 50% of the duty cycle; and The distribution network is configured to generate multiple third clock input signals based on the second clock input signal.

10. The apparatus according to claim 7, characterized in that, The device also includes a clock tree, which comprises: A correction circuit is configured to correct the phase error between the first clock input signal and the second clock input signal; and The distribution network is configured to generate a plurality of third clock input signals based on the first clock input signal and the second clock input signal.

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