Semiconductor packaging structure

Abstract

The utility model discloses a semiconductor packaging structure. The semiconductor packaging structure comprises a lead frame, a first MOS chip and a second MOS chip. A first electrode is arranged on the front surface of the first MOS chip, and a second electrode and a third electrode are arranged on the back surface of the first MOS chip; the first MOS chip is arranged on the base island, and the first electrode is electrically connected with the base island; a fourth electrode is arranged on the front surface of the second MOS chip, and a fifth electrode and a sixth electrode are arranged on the back surface of the first MOS chip; the second MOS chip is stacked on the first MOS chip, and the fourth electrode is electrically connected with the second electrode; the first connecting pin is electrically connected with a sixth electrode of the second MOS chip; the first connecting pin is electrically connected with the first electrode of the first MOS chip, the second connecting pin is electrically connected with the third electrode of the first MOS chip and the fifth electrode of the second MOS chip, the first MOS chip and the second MOS chip which are connected in series are packaged in an up-down stacking mode, the occupied area of the first MOS chip and the second MOS chip in the semiconductor packaging structure is effectively reduced, and miniaturization of multi-MOS chip packaging can be achieved.

Description

Technical Field

[0001] This utility model relates to the field of semiconductor technology, and in particular to a semiconductor packaging structure. Background Technology

[0002] With the continuous development of the semiconductor industry and the miniaturization and weight reduction of consumer electronics products such as smartphones, tablets, and wearable devices, the demand for high-performance, small-size power semiconductor devices is constantly increasing, often requiring the combination of multiple semiconductor devices. MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistors) are crucial semiconductor devices in these devices, and the market demand for miniaturized MOSFET packages is also increasing. Smart products, compared to previous generations of electronic products, require lighter, thinner, shorter, and smaller designs, especially in portable electronic products, wearable devices such as headsets, wristbands, and watches, where there are higher requirements for component footprint and thickness.

[0003] Currently, most existing technologies for multi-MOSFET packaging adopt a flat approach. When packaging multiple MOSFETs using this structure, the flat approach results in a large space occupation, which does not meet the requirements of miniaturized semiconductor packaging. Utility Model Content

[0004] This utility model provides a semiconductor packaging structure to solve the problem of large size in existing semiconductor packaging structures.

[0005] A semiconductor packaging structure includes a lead frame, a first MOS chip, and a second MOS chip;

[0006] The lead frame includes a base island and a first connection pin, a second connection pin, and a third connection pin disposed around the base island; the third connection pin is electrically connected to the base island.

[0007] The first MOS chip has a first electrode on its front side and a second electrode and a third electrode on its back side; the first MOS chip is disposed on the base island, and the first electrode is electrically connected to the base island;

[0008] The second MOS chip has a fourth electrode on its front side, and the first MOS chip has a fifth electrode and a sixth electrode on its back side; the second MOS chip is stacked on the first MOS chip, and the fourth electrode is electrically connected to the second electrode.

[0009] The first connection pin is electrically connected to the sixth electrode of the second MOS chip; the second connection pin is electrically connected to the third electrode of the first MOS chip and the fifth electrode of the second MOS chip, respectively.

[0010] Furthermore, the semiconductor package structure includes electrical connectors and insulating support components;

[0011] The electrical connector includes a connector body and a first connector portion and a second connector portion extending on both sides along the length direction of the connector body; the first connector portion is disposed on the second electrode of the first MOS chip, and the second connector portion is suspended and held above the base island by the insulating support member.

[0012] The second MOS chip is disposed on the electrical connector, and the fourth electrode of the second MOS chip is electrically connected to the second electrode of the first MOS chip through the electrical connector.

[0013] Furthermore, the first connection portion covers a portion of the back surface of the first MOS chip, and the remaining portion of the back surface of the first MOS chip forms an exposed area, where the third electrode of the first MOS chip is disposed.

[0014] Furthermore, the first connecting portion is L-shaped.

[0015] Furthermore, the first region of the first connecting part is formed into a first deformed part that protrudes to one side by a stamping process. The first deformed part includes a first inclined sidewall and a first top platform that smoothly transition with the connecting body.

[0016] The first deformable part is surrounded by an unstamped first continuous planar region, the thickness of which is the same as the thickness of the connecting body;

[0017] The first top platform is at least partially electrically connected to the second electrode of the first MOS chip.

[0018] Furthermore, the second region of the second connecting part is formed into a second deformed part that protrudes to one side by a stamping process. The second deformed part includes a second inclined sidewall and a second top platform that smoothly transition with the connecting body.

[0019] The second deformed portion is surrounded by an unstamped second continuous planar region, the thickness of which is the same as the thickness of the connecting body;

[0020] One end of the insulating support is fixedly connected to the second top platform, and the other end of the insulating support is fixedly connected to the base island.

[0021] Furthermore, the electrical connector is made of copper.

[0022] Furthermore, the insulating support is made of high-temperature resistant insulating material.

[0023] Furthermore, the sixth electrode of the second MOS chip is electrically connected to the first connection pin via a first wire;

[0024] The third electrode of the first MOS chip is electrically connected to the second connection pin via a second wire; the fifth electrode of the second MOS chip is electrically connected to the second connection pin via a third wire.

[0025] Furthermore, the lead frame also includes a fourth connection pin electrically connected to the first connection pin; the fourth connection pin is disposed adjacent to the first connection pin, and the fourth connection pin is electrically connected to the sixth electrode of the second MOS chip through a fourth wire.

[0026] This utility model provides a semiconductor packaging structure, which includes a leadframe, a first MOS chip, and a second MOS chip. The leadframe includes a base island and a first connection pin, a second connection pin, and a third connection pin disposed around the base island. The third connection pin is electrically connected to the base island. A first electrode is disposed on the front side of the first MOS chip, and a second electrode and a third electrode are disposed on the back side of the first MOS chip. The first MOS chip is disposed on the base island, and the first electrode is electrically connected to the base island. A fourth electrode is disposed on the front side of the second MOS chip, and a fifth electrode and a sixth electrode are disposed on the back side of the first MOS chip. The second MOS chip is stacked on top of the first MOS chip, and the fourth electrode is electrically connected to the second electrode. The first connection pin is electrically connected to the sixth electrode of the second MOS chip. The second connection pin is electrically connected to the third electrode of the first MOS chip and the fifth electrode of the second MOS chip, respectively. Thus, the first MOS chip and the second MOS chip are packaged in series by stacking, which effectively reduces the area occupied by the first MOS chip and the second MOS chip in the semiconductor packaging structure and is conducive to miniaturization of multi-MOS chip packaging. Attached Figure Description

[0027] To more clearly illustrate the technical solutions of the embodiments of this utility model, the drawings used in the description of the embodiments of this utility model will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this utility model. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0028] Figure 1 This is a schematic diagram of a semiconductor packaging structure in one embodiment of the present invention;

[0029] Figure 2 This is another schematic diagram of the semiconductor packaging structure in one embodiment of the present invention;

[0030] Figure 3 This is another schematic diagram of the semiconductor packaging structure in one embodiment of the present invention;

[0031] Figure 4 This is a schematic diagram of an electrical connector in one embodiment of the present invention.

[0032] In the figure: 1. Lead frame; 2. First MOS chip; 3. Second MOS chip; 4. Electrical connector; 41. First connection part; 411. First area; 42. Second connection part; 421. Second area; 5. Insulating support. Detailed Implementation

[0033] The technical solutions of the present utility model will be clearly and completely described below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are only some embodiments of the present utility model, not all embodiments. Based on the embodiments of the present utility model, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present utility model.

[0034] It should be understood that this invention can be embodied in various forms and should not be construed as being limited to the embodiments set forth herein. Rather, providing these embodiments will make the disclosure thorough and complete, and will fully convey the scope of this invention to those skilled in the art. In the drawings, for clarity, the dimensions of layers and regions, as well as their relative dimensions, may be exaggerated. The same reference numerals denote the same elements throughout.

[0035] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this utility model, the first element, component, area, layer, or portion discussed below may be referred to as the second element, component, area, layer, or portion.

[0036] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below,” “under,” or “below” other elements or features will be oriented “above” other elements or features. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0037] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the scope of the invention. When used herein, the singular forms “a,” “an,” and “ / the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising” and / or “comprising,” when used in this specification, identify the presence of features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0038] To fully understand this utility model, detailed structures and steps will be presented in the following description to illustrate the technical solution proposed by this utility model. Preferred embodiments of this utility model are described in detail below; however, in addition to these detailed descriptions, this utility model may have other embodiments.

[0039] This embodiment provides a semiconductor packaging structure, such as Figures 1 to 3 As shown, the device includes a lead frame 1, a first MOS chip 2, and a second MOS chip 3. The lead frame 1 includes a base island and a first connection pin, a second connection pin, and a third connection pin disposed around the base island. The third connection pin is electrically connected to the base island. The first MOS chip 2 has a first electrode on its front side and a second electrode and a third electrode on its back side. The first MOS chip 2 is disposed on the base island, and the first electrode is electrically connected to the base island. The second MOS chip 3 has a fourth electrode on its front side and a fifth electrode and a sixth electrode on its back side. The second MOS chip 3 is stacked on top of the first MOS chip 2, and the fourth electrode is electrically connected to the second electrode. The first connection pin is electrically connected to the sixth electrode of the second MOS chip 3. The second connection pin is electrically connected to the third electrode of the first MOS chip 2 and the fifth electrode of the second MOS chip 3, respectively.

[0040] As an example, the semiconductor package structure employs a DFN (Dual Flat No-lead Package) package. Optionally, the leadframe 1 inside the semiconductor package structure is a six-pin lead frame. Exemplarily, the leadframe 1 includes a base island disposed in the central region and two rows of connection pins arranged side-by-side on both sides of the base island. Each row has three pins spaced apart. Exemplarily, the first row of pins sequentially includes a first connection pin, a fourth connection pin, and a second connection pin; the second row of pins sequentially includes a sixth connection pin, a third connection pin, and a fifth connection pin. The third connection pin is electrically connected to the base island via a half-etch process. The first connection pin is used to electrically connect to the sixth electrode of the second MOS chip 3. The second connection pin is used to electrically connect to the third electrode of the first MOS chip 2 and the fifth electrode of the second MOS chip 3. The fourth connection pin is electrically connected to the first connection pin and is used to connect to the sixth electrode of the second MOS chip 3 to improve overcurrent and heat dissipation capabilities. The fifth and sixth connection pins are left floating. The fourth, fifth, and sixth connection pins are all sampled using a half-etch process to ensure that they are not exposed after molding.

[0041] As an example, the first MOS chip 2 and the second MOS chip 3 are MOS chips of the same type. Exemplarily, both the first MOS chip 2 and the second MOS chip 3 are either N-type or P-type MOS chips. Exemplarily, the first electrode of the first MOS chip 2 is the drain, the second electrode is the source, and the third electrode is the gate. The fourth electrode of the second MOS chip 3 is the drain, the fifth electrode is the source, and the sixth electrode of the first MOS chip 2 is the gate.

[0042] In this embodiment, the semiconductor packaging structure includes a leadframe 1, a first MOS chip 2, and a second MOS chip 3. The leadframe 1 includes a base island and a first connection pin, a second connection pin, and a third connection pin disposed around the base island. The third connection pin is electrically connected to the base island. A first electrode is disposed on the front side of the first MOS chip 2, and a second electrode and a third electrode are disposed on the back side of the first MOS chip 2. The first MOS chip 2 is disposed on the base island, and the first electrode is electrically connected to the base island. A fourth electrode is disposed on the front side of the second MOS chip 3, and a fifth electrode and a sixth electrode are disposed on the back side of the first MOS chip 2. The second MOS chip 3 is stacked on top of the first MOS chip 2, and the fourth electrode is electrically connected to the second electrode. The first connection pin is electrically connected to the sixth electrode of the second MOS chip 3. The second connection pin is electrically connected to the third electrode of the first MOS chip 2 and the fifth electrode of the second MOS chip 3, respectively. Thus, the first MOS chip 2 and the second MOS chip 3 are packaged in series by stacking, which effectively reduces the area occupied by the first MOS chip 2 and the second MOS chip 3 in the semiconductor packaging structure and is beneficial to the miniaturization of multi-MOS chip packaging.

[0043] In one embodiment, the semiconductor package structure includes an electrical connector 4 and an insulating support 5; as Figure 4 As shown, the electrical connector 4 includes a connector body and a first connector 41 and a second connector 42 extending on both sides along the length direction of the connector body; the first connector 41 is disposed on the second electrode of the first MOS chip 2, and the second connector 42 is suspended and held above the base island by an insulating support member 5; the second MOS chip 3 is disposed on the electrical connector 4, and the fourth electrode of the second MOS chip 3 is electrically connected to the second electrode of the first MOS chip 2 through the electrical connector 4.

[0044] As an example, the electrical connector 4 is made of metal. This metal can be a composite copper sheet or a copper sheet. The insulating support 5 is made of a high-temperature resistant insulating material. Preferably, the insulating support 5 is ceramic to prevent excessively high temperatures from affecting the stability of the home support.

[0045] In related technologies, multiple MOS chips are laid out in a semiconductor package structure. The MOS chips inside the semiconductor package structure are electrically connected to the connection pins of the semiconductor package structure through wires. When the semiconductor package structure is used in a PCB board, if multiple MOS chips in the semiconductor package structure need to be connected in series, additional lines need to be added to the PCB board, which requires a larger line area.

[0046] As an example, the electrical connector 4 is held on the first MOS chip 2 by the first connecting portion 41 and on the insulating support 5 by the second connecting portion 42. This allows the electrical connector 4 to stably and reliably support the second MOS chip 3, enabling the first MOS chip 2 and the second MOS chip 3 to achieve common polarity through the electrical connector 4. This reduces the external PCB traces when the first MOS chip 2 and the second MOS chip 3 are connected in series, thereby reducing the trace area on the PCB. Furthermore, due to the presence of the electrical connector 4 and the insulating support 5, a second MOS chip 3 with a larger size than the first MOS chip 2 can be stacked on the electrical connector 4. At the same time, the suspended area between the second connecting portion 42 and the base island can be used for wire bonding, increasing space utilization.

[0047] In one embodiment, the first connection portion 41 covers a portion of the back surface of the first MOS chip 2, and the other portion of the back surface of the first MOS chip 2 forms an exposed area, with the third electrode of the first MOS chip 2 disposed in the exposed area.

[0048] In this embodiment, the first connection portion 41 covers a portion of the back side of the first MOS chip 2, and the other areas on the back side of the first MOS chip 2 form an exposed area. The third electrode of the first MOS chip 2 is disposed in the exposed area to facilitate wire bonding of the third electrode. At the same time, the electrical connector 4 has a sufficiently large area to support the second MOS chip 3.

[0049] In one embodiment, the first connection portion 41 is L-shaped. In this embodiment, the first connection portion 41 is L-shaped, which on the one hand ensures that there is a sufficient exposed area for the third electrode, and on the other hand increases the electrical contact area between the first connection portion 41 and the fourth electrode of the second MOS chip 3 and the second electrode of the first MOS chip 2, thereby increasing the overcurrent capacity.

[0050] In one embodiment, the first region 411 of the first connecting portion 41 is formed by a stamping process to form a first deformable portion protruding to one side. The first deformable portion includes a first inclined sidewall that smoothly transitions with the connecting body and a first top platform. A first continuous planar region that is not stamped is provided around the first deformable portion. The thickness of the first continuous planar region is the same as the thickness of the connecting body. The first top platform is at least partially electrically connected to the second electrode of the first MOS chip 2.

[0051] The shape, area, and location of the first region 411 can be determined based on practical experience and are not restricted here.

[0052] As an example, the first top platform is at least partially electrically connected to the second electrode of the first MOS chip 2. In this example, the electrical connection between the first top platform and the second electrode of the first MOS chip 2 can be achieved by applying solder paste and then curing it in a reflow oven to ensure that the electrical connection has high robustness and current carrying capacity.

[0053] In one embodiment, the second region 421 of the second connecting portion 42 is formed by a stamping process to form a second deformed portion that protrudes to one side. The second deformed portion includes a second inclined sidewall that smoothly transitions with the connecting body and a second top platform. A second continuous planar region that is not stamped is provided around the second deformed portion. The thickness of the second continuous planar region is the same as the thickness of the connecting body. One end of the insulating support member 5 is fixedly connected to the second top platform, and the other end of the insulating support member 5 is fixedly connected to the base island.

[0054] The shape, area, and location of this second zone can be determined based on practical experience and are not restricted here.

[0055] As an example, one end of the insulating support 5 is fixedly connected to the second top platform after curing with glue or solder paste, and the other end of the insulating support 5 is fixedly connected to the base island after curing with glue or solder paste. By having the second top platform contact one end of the insulating support 5, the firmness of the contact surface can be improved.

[0056] Furthermore, the processing method of the electrical connector 4 includes: first, determining multiple processing areas of the electrical connector 4 on the initial copper sheet, and determining a first region 411 of the first connecting part 41 and a second region 421 of the second connecting part 42 on each electrical connector 4; then, stamping the first region 411 and the second region 421 in each processing area; next, attaching an insulating support 5 to the second top platform of each second region 421 with adhesive; finally, cutting each processing area to obtain multiple electrical connectors 4.

[0057] In one embodiment, the sixth electrode of the second MOS chip 3 is electrically connected to the first connection pin via a first wire; the third electrode of the first MOS chip 2 is electrically connected to the second connection pin via a second wire; and the fifth electrode of the second MOS chip 3 is electrically connected to the second connection pin via a third wire.

[0058] As an example, the sixth electrode of the second MOS chip 3 is electrically connected to the first connection pin through the first wire, thereby realizing the electrical connection between the second MOS chip 3 and the first connection pin; the third electrode of the first MOS chip 2 is electrically connected to the second connection pin through the second wire; the fifth electrode of the second MOS chip 3 is electrically connected to the second connection pin through the third wire, thereby enabling the second connection pin to simultaneously control the third electrode of the first MOS chip 2 and the fifth electrode of the second MOS chip 3, reducing the number of lines.

[0059] In one embodiment, the lead frame 1 further includes a fourth connection pin electrically connected to the first connection pin; the fourth connection pin is disposed adjacent to the first connection pin, and the fourth connection pin is electrically connected to the sixth electrode of the second MOS chip 3 through a fourth wire.

[0060] In this embodiment, the sixth electrode is connected to the first connection pin and the fourth connection pin, which are electrically connected to each other, through the first wire and the fourth wire, which can increase the overcurrent capacity at the sixth electrode.

[0061] As an example, the processing flow of the above semiconductor packaging structure includes: S1: preparing a lead frame 1 with six connecting pins, the base island of the lead frame 1 being electrically connected to the third connecting pin; S2: using a die bonder, applying solder or adhesive to the base island of the lead frame 1, placing the first MOS chip 2 in the appropriate position on the base island and curing it; S3: applying solder paste to the second electrode (source) on the back of the first MOS chip 2, placing the electrical connector 4 (composite copper sheet) on the second electrode (source) of the first MOS chip 2, facilitating the bonding of the first MOS chip 2 and the second MOS chip 3 through the electrical connector 4 (composite copper sheet), and providing an insulating support between the electrical connector 4 (composite copper sheet) and the base island. 5. The insulating support 5 is approximately located between the sixth connection pin and the first connection pin, and is cured in a reflow oven; S4. Using a die bonder, tin or glue is applied to the electrical connector 4 (composite copper sheet), solder paste is applied to the fourth electrode (drain) of the second MOS chip 3, the second MOS chip 3 is placed on the electrical connector 4 (composite copper sheet), and cured in a reflow oven; S5. Wire bonding is performed between the third electrode (gate) of the first MOS chip 2 and the second connection pin, between the fifth electrode (gate) of the second MOS chip 3 and the second connection pin, and between the sixth electrode (source) of the second MOS chip 3 and the first and fourth connection pins; S6. Molding and post-curing.

[0062] The above-described embodiments are only used to illustrate the technical solutions of this utility model, and are not intended to limit it. Although this utility model has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this utility model, and should all be included within the protection scope of this utility model.

Claims

1. A semiconductor packaging structure, characterized in that, Includes lead frame, first MOS chip and second MOS chip; The lead frame includes a base island and a first connection pin, a second connection pin, and a third connection pin disposed around the base island; the third connection pin is electrically connected to the base island. The first MOS chip has a first electrode on its front side and a second electrode and a third electrode on its back side; the first MOS chip is disposed on the base island, and the first electrode is electrically connected to the base island; The second MOS chip has a fourth electrode on its front side, and the first MOS chip has a fifth electrode and a sixth electrode on its back side; the second MOS chip is stacked on the first MOS chip, and the fourth electrode is electrically connected to the second electrode. The first connection pin is electrically connected to the sixth electrode of the second MOS chip; the second connection pin is electrically connected to the third electrode of the first MOS chip and the fifth electrode of the second MOS chip, respectively.

2. The semiconductor packaging structure according to claim 1, characterized in that, The semiconductor packaging structure includes electrical connectors and insulating support components; The electrical connector includes a connector body and a first connector portion and a second connector portion extending on both sides along the length direction of the connector body; the first connector portion is disposed on the second electrode of the first MOS chip, and the second connector portion is suspended and held above the base island by the insulating support member. The second MOS chip is disposed on the electrical connector, and the fourth electrode of the second MOS chip is electrically connected to the second electrode of the first MOS chip through the electrical connector.

3. The semiconductor packaging structure according to claim 2, characterized in that, The first connection portion covers a portion of the back surface of the first MOS chip, and the remaining area on the back surface of the first MOS chip forms an exposed area. The third electrode of the first MOS chip is disposed in the exposed area.

4. The semiconductor packaging structure according to claim 3, characterized in that, The first connecting part is L-shaped.

5. The semiconductor packaging structure according to claim 2, characterized in that, The first region of the first connecting part is formed by a stamping process to form a first deformable part that protrudes to one side. The first deformable part includes a first inclined sidewall and a first top platform that smoothly transition with the connecting body. The first deformable part is surrounded by an unstamped first continuous planar region, the thickness of which is the same as the thickness of the connecting body; The first top platform is at least partially electrically connected to the second electrode of the first MOS chip.

6. The semiconductor packaging structure according to claim 2, characterized in that, The second region of the second connecting part is formed by a stamping process to form a second deformed part that protrudes to one side. The second deformed part includes a second inclined sidewall and a second top platform that smoothly transition with the connecting body. The second deformed portion is surrounded by an unstamped second continuous planar region, the thickness of which is the same as the thickness of the connecting body; One end of the insulating support is fixedly connected to the second top platform, and the other end of the insulating support is fixedly connected to the base island.

7. The semiconductor packaging structure according to claim 2, characterized in that, The electrical connector is made of copper.

8. The semiconductor packaging structure according to claim 2, characterized in that, The insulating support is made of high-temperature resistant insulating material.

9. The semiconductor packaging structure according to claim 1, characterized in that, The sixth electrode of the second MOS chip is electrically connected to the first connection pin via a first wire; The third electrode of the first MOS chip is electrically connected to the second connection pin via a second wire; the fifth electrode of the second MOS chip is electrically connected to the second connection pin via a third wire.

10. The semiconductor packaging structure according to claim 1, characterized in that, The lead frame further includes a fourth connection pin electrically connected to the first connection pin; the fourth connection pin is disposed adjacent to the first connection pin, and the fourth connection pin is electrically connected to the sixth electrode of the second MOS chip through a fourth wire.

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