Low-power-consumption board card based on domestic processor

Abstract

The low-power-consumption board card comprises the domestic processor, an FPGA (Field Programmable Gate Array) chip, a first connector, a second connector and an Ethernet PHY (Physical Layer) chip, the multi-path GPIO interface and the multi-path UART interface of the processor are electrically connected with the first connector through the FPGA chip. A plurality of paths of RGMII interfaces and a plurality of paths of I2C interfaces of the processor are directly and electrically connected with the first connector; the processor is connected with the second connector through the Ethernet PHY chip; and the PCIE X4 interface, the PCIE X1 interface and the CAN interface of the processor are electrically connected with the second connector respectively. According to the utility model, on one hand, a 100% domestic chip is adopted, so that the cost can be greatly reduced, and autonomous and controllable resources are provided; and on the other hand, the whole circuit structure is simple, and the power consumption of the whole board card can be greatly reduced while more external flexible interfaces are provided.

Description

Technical Field

[0001] This utility model relates to a board, and more particularly to a low-power board based on a domestically produced processor. Background Technology

[0002] A circuit board (PCB) is a type of printed circuit board. During manufacturing, it includes inserts that allow it to be inserted into slots on the computer's main circuit board (motherboard) to control hardware such as monitors and data acquisition cards. After installing drivers, the corresponding hardware functions are implemented. PCBs are widely used in scientific research, communications, and many other fields. Existing high-performance PCBs typically have high power consumption, around 30W, thus requiring strict heat dissipation. However, the internal cooling conditions of some devices may not meet these requirements. Furthermore, existing PCBs offer a limited number of interfaces, and the chips used cannot be guaranteed to be 100% domestically produced, resulting in insufficient self-control and low security of the hardware platform. Alternatively, existing PCBs may have a large number of interfaces with an unreasonable layout, leading to high overall power consumption.

[0003] Therefore, this application urgently needs to design a low-power board based on a domestically produced processor to solve the above-mentioned technical problems. Utility Model Content

[0004] The purpose of this utility model is to overcome the above-mentioned shortcomings of the prior art and provide a low-power board based on a domestic processor that is low in cost, simple in structure, small in size, and independently controllable.

[0005] The technical solution of this utility model is: a low-power board based on a domestically produced processor, including a domestically produced processor, an FPGA chip, a first connector, a second connector, and an Ethernet PHY chip; the processor's multiple GPIO interfaces and multiple UART interfaces are electrically connected to the first connector via the FPGA chip; the processor's multiple RGMII interfaces and multiple I2C interfaces are directly electrically connected to the first connector; the processor is connected to the second connector via the Ethernet PHY chip; the processor's PCIE X4 interface, PCIE X1 interface, and CAN interface are electrically connected to the second connector.

[0006] Furthermore, the processor is a Phytium E2000Q processor.

[0007] Furthermore, the board also includes a storage unit, which includes an EMMC storage chip, a Norflash chip, and a DDR4 chip that are respectively connected to the processor. All chips in the storage unit are domestically produced chips.

[0008] Furthermore, the 8 GPIO interfaces of the E2000Q processor are connected to the first connector via an FPGA chip, and the 4 UART interfaces of the processor are also connected to the first connector via an FPGA chip.

[0009] Furthermore, the E2000Q processor's two RGMII interfaces and two I2C interfaces are respectively connected to the first connector.

[0010] Furthermore, the E2000Q processor establishes serial high-speed data communication with the Ethernet PHY chip through two SGMII interfaces, and the Ethernet PHY chip is connected to the second connector through two MDI interfaces.

[0011] Furthermore, the E2000Q processor is connected to the second connector via one PCIe x4 interface, two PCIe x1 interfaces, and two CAN interfaces.

[0012] Furthermore, the processor is connected to the Norflash chip via a QSPI interface.

[0013] Furthermore, the processor's storage end is connected to an onboard EMMC storage chip, and its memory end is connected to multiple onboard 8GB DDR4 memory chips.

[0014] The beneficial effects of this utility model are:

[0015] (1) All chips, including processor, FPGA chip, Ethernet PHY chip, etc., are domestically produced, which can greatly reduce costs and have independent and controllable resources.

[0016] (2) By combining the domestic processor with the FPGA chip, it can not only have more flexible external interfaces, but also greatly reduce the power consumption of the entire board, with the lowest operating power consumption reaching 4W; by combining the processor with the Ethernet PHY chip, and connecting the processor itself to the first connector through 2 RGMII interfaces, it can provide more external network ports, that is, it can directly connect to 4 Gigabit Ethernet ports on the basis of low power consumption.

[0017] (3) By bringing out 2 MDI Ethernet signals, 2 RGMII signals, 2 I2C signals, 2 CAN signals, 4 serial port signals, 1 QSPI signal, 8 GPIO signals, 1 PCIE X4 signal and 2 PCIE X1 signals, it provides more flexible interfaces while maintaining low power consumption. In other words, the board of this application can be used in various application scenarios without involving too many redundant interfaces to increase power consumption, and the overall size of the board is reduced.

[0018] (4) By setting two connectors, on the one hand, the two connectors can be connected to different external devices or used for different data channels. When one of the connectors fails, the system can continue to work normally through the other connector, which improves the stability and reliability of the system. On the other hand, the two connectors can avoid a single connector from generating too much heat due to carrying too much data, thereby avoiding the increase in power consumption due to overheating. Attached Figure Description

[0019] Figure 1 This is a schematic diagram of the circuit principle of the board in this embodiment of the utility model. Detailed Implementation

[0020] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0021] like Figure 1 The diagram shows a low-power board based on a domestically produced processor, comprising a processor, an FPGA chip, a first connector, a second connector, a storage unit, an Ethernet PHY chip, and a power module. The board's overall dimensions are 95mm × 75mm (length × width), making it suitable for various application scenarios. The board's operating temperature ranges from -40℃ to 55℃, and its storage temperature ranges from -55℃ to 125℃, meeting the industrial control requirements of industrial PCs and thus having a wide range of applications.

[0022] In this embodiment, the board's functional requirements are: to be able to output 2 MDI Ethernet signals, 2 RGMII signals, 2 I2C signals, 2 CAN signals, 4 serial port signals (3 functional serial ports and 1 debug serial port), 1 QSPI signal, 8 GPIO signals, 1 PCIe x4 signal, and 2 PCIe x1 signals. This embodiment uses a domestically produced processor to support the above functional interfaces and combines an FPGA for signal processing and adaptation, bringing more flexibility, scalability, and signal processing capabilities to the board. Specifically, the FPGA can process, convert, and adapt signals. For example, the interface between the processor and the first connector may differ in level, voltage, or communication protocol. The FPGA can convert different signal standards to ensure smooth data transmission. Furthermore, the FPGA chip provides high programmability, allowing designers to customize interface logic as needed. If the behavior of GPIO or UART needs to be changed during system operation (e.g., modifying the protocol or timing), the FPGA can be reprogrammed without changing the hardware.

[0023] In this embodiment, the processor used is the domestically produced Phytium E2000Q processor. Compared to the Phytium E2000D, this processor is superior in terms of core performance, number of PCIe ports, video encoding / decoding capabilities, and number of low-speed ports. The FPGA chip preferably uses Anlogic's EF2L45LG144B, which features an advanced 55nm low-power process, built-in Flash memory, supports fast power-on startup, and supports up to 700 Kbits of embedded block memory and 35 Kbits of distributed memory, offering advantages such as low cost and low power consumption.

[0024] In this embodiment, the storage unit includes an eMMC memory chip, a Norflash chip, and a DDR4 chip, all connected to the E2000Q processor. Specifically, the E2000Q processor's storage side is connected to an onboard eMMC memory chip, preferably the Longsys FEMDRW128G-88A19 eMMC memory chip, with a storage capacity of 128GB, supporting the eMMC 5.1 protocol, backward compatible with eMMC 4.41 / 4.5 / 5.0, a data transfer rate of up to 400MB / s, power-loss protection, and a hardware ECC engine. The E2000Q processor's memory side is connected to eight 8GB surface-mount DDR4 memory chips. By using surface-mount memory chips instead of the traditional memory slots and memory modules, the overall board's vibration and shock resistance is enhanced. The E2000Q processor connects to the Norflash chip via a QSPI interface, for example, using one EFM25F128A chip to form a 16MB capacity. Among them, the eMMC memory chip can store data for long periods, including the operating system, applications, and user data; the DDR4 chip mainly serves as temporary storage, supporting efficient data reading and writing to help the processor execute tasks quickly; and the Norflash chip provides fast read capabilities. Furthermore, using a QSPI interface to connect the NorFlash chip can significantly improve data transfer rates, accelerate the system boot process, and simplify system design without sacrificing cost.

[0025] In this embodiment, the power module is used to power the board. The power module is sent to the power supply terminal of the board through the first connector. The board preferably uses DC 5V power supply. The 5V power supply can be converted into multiple power supplies such as 0.8V, 1.2V, 1.8V, and 3.3V through the DC-DC power conversion module to power the processor, FPGA chip, etc.

[0026] In this embodiment, the processor's 8 GPIO interfaces are connected to the first connector via the FPGA chip, and the processor's 4 UART interfaces are also connected to the first connector via the FPGA chip. That is, the processor's 8 GPIO interfaces are connected to the 8 GPIO interfaces of the FPGA chip, and these 8 GPIO interfaces of the FPGA chip are further connected to the first connector; similarly, the processor's 4 UART interfaces are connected to the 4 UART interfaces of the FPGA chip, and these 4 UART interfaces of the FPGA chip are further connected to the first connector. It can be understood that, in this embodiment, other interfaces of the processor can be connected to the first connector via the FPGA chip according to the requirements of the board.

[0027] In the above connection, the processor outputs 8 GPIO signals and 4 serial port signals through the FPGA chip because GPIO and UART interfaces are typically used to handle low-speed signals or simple communication tasks. For example, GPIO is usually used for single digital signal input / output, while UART is commonly used for serial communication. The data transmission requirements of these interfaces are usually not complex, requiring more signal conditioning or protocol adaptation. The FPGA chip can be used for signal conditioning and protocol conversion, especially in applications with high speed requirements or real-time processing. For example, different hardware platforms or connectors may have specific requirements for UART baud rate, timing, etc., and the FPGA chip can help adapt to these different requirements. Furthermore, the FPGA allows for flexible signal processing on the GPIO interface, such as multiplexing and dynamically configuring multiple signal lines, enabling the processor to manage these signals more effectively.

[0028] In this embodiment, the processor's two RGMII interfaces and two I2C interfaces are connected to the first connector. These interfaces can be directly connected to the first connector without going through the FPGA chip. This helps the system maintain low power consumption and low cost; connecting all interfaces through the FPGA would not only increase hardware costs but also potentially lead to unnecessary power consumption increases. Furthermore, these signals typically do not require complex signal conditioning or conversion and can be directly connected to the first connector without FPGA processing. The RGMII interfaces in this embodiment support Gigabit Ethernet communication, and the first connector provides additional external network ports.

[0029] In this embodiment, the processor establishes high-speed serial data communication with the Ethernet PHY chip through two SGMII interfaces, primarily responsible for network data transmission. The Ethernet PHY chip connects to a second connector through two MDI interfaces, establishing a physical network connection with external devices and implementing electrical data transmission at the physical layer. Specifically, the SGMII interface converts data sent by the processor into serial signals and transmits them to the Ethernet PHY chip, while simultaneously transmitting data returned by the Ethernet PHY chip back to the processor. The Ethernet PHY chip converts network data into electrical signals through two MDI interfaces and establishes a physical connection and data transmission with external devices via a network cable. The Ethernet PHY chip used is the YT8521 PHY chip from Yutai Microelectronics.

[0030] In other words, this embodiment can provide more external network ports by combining the processor with the Ethernet PHY chip and connecting it to the second connector, and by connecting the processor itself to the first connector through two RGMII interfaces. For example, when using the E2000Q processor, up to four Gigabit Ethernet ports can be directly connected.

[0031] In this embodiment, the processor is connected to the second connector via one PCIe x4 interface, two PCIe x1 interfaces, and two CAN interfaces. The one PCIe x4 interface provides high-bandwidth data transmission for connecting devices with high bandwidth requirements, such as network cards and storage controllers. The two PCIe x1 interfaces provide lower-bandwidth data transmission for connecting devices with low bandwidth requirements, such as USB controllers or expansion cards. The two CAN interfaces are used for real-time and reliable data communication. This embodiment preferably achieves a transmission rate of 10Gbps.

[0032] In this embodiment, both the first and second connectors are domestically produced high-speed connectors. Using XMC connectors allows for easy connection to other hardware modules, such as external storage, accelerator cards, and network interfaces, supporting more expansion functions and adapting to different scenario requirements. Furthermore, XMC connectors support high-speed data transmission, providing sufficient bandwidth for each module within the board. By using two high-speed connectors compared to using only one, firstly, if the two connectors are connected to different external devices or used for different data channels, the system can continue to operate normally through the other connector if one connector fails, improving system stability and reliability. Secondly, multiple connectors can achieve parallel transmission, reducing data transmission latency, and they can help distribute heat within the board, preventing a single connector from generating excessive heat due to carrying too much data, thus avoiding increased power consumption due to overheating.

[0033] In summary, this embodiment utilizes domestically produced chips for all components, including the processor, FPGA chip, and Ethernet PHY chip, significantly reducing costs and providing self-controllable resources. Furthermore, by combining the processor with the FPGA chip, it offers more flexible external interfaces while significantly reducing the overall board's power consumption; the minimum operating power consumption in this embodiment is 4W. The combination of the processor with the Ethernet PHY chip, along with the processor's connection to the first connector via two RGMII interfaces, provides more external network ports; this embodiment can directly connect up to four Gigabit Ethernet ports. Moreover, it offers at least a larger storage capacity while maintaining low power consumption, with a default of 128GB.

Claims

1. A low-power board based on a domestically produced processor, characterized in that, This includes domestically produced processors, FPGA chips, first connectors, second connectors, and Ethernet PHY chips; The processor’s multi-channel GPIO interface and multi-channel UART interface are electrically connected to the first connector via the FPGA chip. The processor’s multiple RGMII interfaces and multiple I2C interfaces are directly electrically connected to the first connector; The processor is connected to the second connector via an Ethernet PHY chip; the processor's PCIE X4 interface, PCIE X1 interface, and CAN interface are electrically connected to the second connector respectively.

2. The low-power board based on a domestically produced processor according to claim 1, characterized in that, The processor is a Phytium E2000Q processor.

3. The low-power board based on a domestically produced processor according to claim 1, characterized in that, The board also includes a storage unit, which includes an EMMC storage chip, a Norflash chip, and a DDR4 chip that are respectively connected to the processor. All chips in the storage unit are domestically produced chips.

4. The low-power board based on a domestically produced processor according to claim 2, characterized in that, The E2000Q processor's 8 GPIO interfaces are connected to the first connector via an FPGA chip, and the processor's 4 UART interfaces are also connected to the first connector via an FPGA chip.

5. The low-power board based on a domestically produced processor according to claim 2, characterized in that, The E2000Q processor's two RGMII interfaces and two I2C interfaces are respectively connected to the first connector.

6. The low-power board based on a domestically produced processor according to claim 2, characterized in that, The E2000Q processor establishes high-speed serial data communication with the Ethernet PHY chip through two SGMII interfaces, and the Ethernet PHY chip is connected to the second connector through two MDI interfaces.

7. The low-power board based on a domestically produced processor according to claim 2, characterized in that, The E2000Q processor is connected to the second connector via one PCIe x4 interface, two PCIe x1 interfaces, and two CAN interfaces.

8. The low-power board based on a domestically produced processor according to claim 3, characterized in that, The processor is connected to the Norflash chip via a QSPI interface.

9. The low-power board based on a domestically produced processor according to claim 3, characterized in that, The processor's storage end is connected to the onboard EMMC storage chip, and its memory end is connected to multiple onboard 8GB DDR4 memory chips.

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