DDR3 and DDR4 common buck power supply mainboard circuit based on memory type identification

Abstract

The utility model discloses a DDR3 (double data rate 3) and DDR4 (double data rate 4) shared buck power supply mainboard circuit based on memory type identification. The core of the buck power supply mainboard circuit is a buck circuit formed by buck IC U26, and functions are realized through unique pin connection design. A second pin of a DDR3 memory slot is suspended to serve as a detection pin, when a DDR4 memory bank is inserted, DDR3DET is suspended, the resistance to ground of an FB pin-6 of a buck IC U26 is 2k, and 1.2 V voltage is calculated and output to meet the power supply requirement of the DDR4; when a DDR3 memory bank is inserted, the DDR3DET is pulled down, the resistance to ground of the FB pin 6 of the U26 is changed into 4.7 k to be connected with 2k in parallel, and 1.5 V voltage is output through calculation to be matched with the DDR3. The circuit solves the problem that a traditional mainboard cannot be compatible with the DDR3 memory bank and the DDR4 memory bank at the same time, has the advantages of being high in compatibility, low in cost and flexible and ingenious in design, and can supply power to the two memory banks only through one buck IC.

Description

Technical Field

[0001] This utility model relates to a power supply motherboard, specifically to a motherboard circuit for DDR3 and DDR4 to share a buck power supply based on memory type identification. Background Technology

[0002] According to the JEDEC memory specification, DDR4 memory modules require a 1.2V power supply, while DDR3 requires 1.5V. If a motherboard is designed with two types of memory modules, then two power supplies need to be designed, requiring two BUCK ICs.

[0003] The conventional design for pin 2 of a DDR3 memory slot is to connect to GNDv. Now it's left floating for detection purposes. This means that after a memory module is inserted, this pin is pulled low by the memory module, thus controlling the power supply at the back end. Note: There is no strict requirement for signal integrity if the memory slot is missing a GND pin.

[0004] In the existing technology, a computer motherboard can only install either DDR3 memory modules or DDR4 memory modules, and they are not compatible. In view of this, a circuit is developed that can simultaneously support both DDR3 and DDR4 memory modules on a computer motherboard to solve the above-mentioned technical problem. Utility Model Content

[0005] The purpose of this invention is to provide a motherboard circuit for DDR3 and DDR4 to share a buck power supply based on memory type identification, so as to solve the problem that the motherboard cannot be compatible with DDR3 and DDR4 memory modules at the same time in the existing technology. Through ingenious circuit design, it is possible to use a single buck IC to power two memory modules with different power requirements, simplifying the motherboard circuit design and reducing costs.

[0006] To solve the above technical problems, this utility model provides the following solution: A DDR3 and DDR4 shared buck power supply motherboard circuit based on memory type identification, comprising a buck circuit, which includes a buck IC U26. The circuits connected to each pin of the buck IC U26 include:

[0007] Pin FB-6 is connected to the first terminals of resistors R7, R10, R50, and R33, and the first terminal of capacitor C7. The second terminal of resistor R7 is connected to the first terminal of resistor R8, and the second terminal of resistor R8 is grounded. The second terminal of resistor R33 is grounded. The second terminal of resistor R50 is connected to the collector of transistor Q7, and the emitter of transistor Q7 is grounded. The base of transistor Q7 is connected to the first terminal of resistor R51 and the collector of transistor Q8, and the emitter of transistor Q8 is grounded. The base of transistor Q8 is connected to the first terminal of resistor R52 and the DDR3_DET circuit. The second terminal of resistor R51 is connected to the +3V3_DUAL circuit, and the second terminal of resistor R52 is connected to the +3V3_DUAL circuit.

[0008] OCSET / PH pin-7 is connected to the first terminal of capacitor C5, the second terminal of capacitor C5 is connected to the first terminal of resistor R8, resistor R6 and capacitor C6 are connected in series and then in parallel with capacitor C5, and OCSET / PH pin-7 also outputs the VSM_C23_EN circuit;

[0009] VCC pin -5 is connected to resistor R30 and capacitor C41 respectively. The other end of resistor R30 is connected to VCC12, and the other end of capacitor C41 is grounded.

[0010] BOOT pin-1 is connected to resistor R31, and the other end of resistor R31 is connected to the first end of capacitor C43.

[0011] UGATE pin-2 is connected to the gate of MOSFET Q3. The drain of MOSFET Q3 is connected to the first terminal of inductor L10 and the first terminal of capacitor C42. The second terminal of inductor L10 is connected to VCC12. The second terminal of capacitor C42 is grounded. Capacitor C42 is also connected in parallel with a polarized capacitor CE44 and a capacitor C102. The negative terminal of polarized capacitor CE44 is connected to the second terminal of capacitor C42. The source of MOSFET Q3 is connected to the second terminal of capacitor C43.

[0012] PHASE pin -8 is connected to the drain of MOSFET Q4, the first terminal of resistor R32, and the first terminal of inductor L2. The drain of MOSFET Q4 is connected to the source of MOSFET Q3. The second terminal of resistor R32 is connected to the first terminal of capacitor C44. The second terminal of capacitor C44 is grounded. The second terminal of inductor L2 is connected to the positive terminals of polarized capacitors CE31, CE32, and CE33, the V_SM_C23 circuit, the second terminal of resistor R10, and the second terminal of capacitor C7. The source of MOSFET Q4 is grounded. The negative terminals of polarized capacitors CE31, CE32, and CE33 are all grounded.

[0013] LGATE pin -4 is connected to the first end of resistor R9 and the gate of MOS transistor Q4, respectively, and the second end of resistor R9 is grounded;

[0014] GND1 pin -9 ground;

[0015] The GND pin is connected to the first end of resistor R2, and the second end of resistor R2 is grounded.

[0016] Furthermore, the buck IC U26 uses the UP1542 series IC.

[0017] Furthermore, the buck IC U26 used is model UP1542SSU8 SOP8.

[0018] Furthermore, the voltage at pin FB-6 of the buck IC U26 is 0.6V.

[0019] Compared with the prior art, the beneficial effects of this utility model are:

[0020] 1. Improved compatibility: Through a unique circuit design, this utility model enables a motherboard to be compatible with both DDR3 and DDR4 memory modules, greatly improving the motherboard's applicability. Users can flexibly choose to use DDR3 or DDR4 memory modules according to their needs and actual situation without having to replace the motherboard.

[0021] 2. Cost reduction of this utility model: Compared with the traditional design that requires two BUCK ICs to power DDR3 and DDR4 memory modules respectively, this utility model only uses one buck IC to complete the power supply task for both types of memory modules, reducing the number of electronic components used and reducing the production cost of the motherboard.

[0022] 3. This utility model has a flexible and ingenious design: it cleverly uses a floating GND pin on the DDR3 memory slot as a detection pin, and identifies the type of inserted memory module by changing the level of this pin, thereby controlling the Buck IC to output different voltages, achieving compatibility with memory modules with different power supply requirements. The design concept is novel and flexible. Attached Figure Description

[0023] Figure 1 This is a circuit diagram of a DDR3 memory slot in the existing technology.

[0024] Figure 2-4 The circuit connection forms the circuit diagram of the buck power supply motherboard of this utility model. Detailed Implementation

[0025] The technical solutions of the present utility model will be clearly and completely described below with reference to the accompanying drawings of the embodiments, so that the advantages and features of the present utility model can be more easily understood by those skilled in the art, thereby making a clearer and more definite definition of the protection scope of the present utility model. Obviously, the embodiments described in this utility model are only some embodiments of the present utility model, and not all embodiments. Based on the embodiments of the present utility model, all other embodiments obtained by those skilled in the art without creative effort are within the protection scope of the present utility model.

[0026] Furthermore, the technical features involved in the different embodiments of this utility model described below can be combined with each other as long as they do not conflict with each other.

[0027] Example 1: The specific structure of this utility model is as follows:

[0028] like Figure 1 As shown, Figure 1 This is a circuit diagram of a DDR3 memory slot in existing technology. The conventional design for pin 2 of a DDR3 memory slot is connected to GNDv, but it's currently left floating for detection purposes. This means that after the memory module is inserted, this pin is pulled low by the memory module, thus controlling the power supply. Note: Omitting one GND pin in the memory slot does not interfere with signal integrity.

[0029] Please refer to the appendix. Figure 2-4 This utility model discloses a DDR3 and DDR4 shared buck power supply motherboard circuit based on memory type identification, including a buck circuit, which includes a buck IC U26. The circuits connected to each pin of the buck IC U26 include:

[0030] Pin FB-6 is connected to the first terminals of resistors R7, R10, R50, and R33, and the first terminal of capacitor C7. The second terminal of resistor R7 is connected to the first terminal of resistor R8, and the second terminal of resistor R8 is grounded. The second terminal of resistor R33 is grounded. The second terminal of resistor R50 is connected to the collector of transistor Q7, and the emitter of transistor Q7 is grounded. The base of transistor Q7 is connected to the first terminal of resistor R51 and the collector of transistor Q8, and the emitter of transistor Q8 is grounded. The base of transistor Q8 is connected to the first terminal of resistor R52 and the DDR3_DET circuit. The second terminal of resistor R51 is connected to the +3V3_DUAL circuit, and the second terminal of resistor R52 is connected to the +3V3_DUAL circuit.

[0031] OCSET / PH pin-7 is connected to the first terminal of capacitor C5, the second terminal of capacitor C5 is connected to the first terminal of resistor R8, resistor R6 and capacitor C6 are connected in series and then in parallel with capacitor C5, and OCSET / PH pin-7 also outputs the VSM_C23_EN circuit;

[0032] VCC pin -5 is connected to resistor R30 and capacitor C41 respectively. The other end of resistor R30 is connected to VCC12, and the other end of capacitor C41 is grounded.

[0033] BOOT pin-1 is connected to resistor R31, and the other end of resistor R31 is connected to the first end of capacitor C43.

[0034] UGATE pin-2 is connected to the gate of MOSFET Q3. The drain of MOSFET Q3 is connected to the first terminal of inductor L10 and the first terminal of capacitor C42. The second terminal of inductor L10 is connected to VCC12. The second terminal of capacitor C42 is grounded. Capacitor C42 is also connected in parallel with a polarized capacitor CE44 and a capacitor C102. The negative terminal of polarized capacitor CE44 is connected to the second terminal of capacitor C42. The source of MOSFET Q3 is connected to the second terminal of capacitor C43.

[0035] PHASE pin -8 is connected to the drain of MOSFET Q4, the first terminal of resistor R32, and the first terminal of inductor L2. The drain of MOSFET Q4 is connected to the source of MOSFET Q3. The second terminal of resistor R32 is connected to the first terminal of capacitor C44. The second terminal of capacitor C44 is grounded. The second terminal of inductor L2 is connected to the positive terminals of polarized capacitors CE31, CE32, and CE33, the V_SM_C23 circuit, the second terminal of resistor R10, and the second terminal of capacitor C7. The source of MOSFET Q4 is grounded. The negative terminals of polarized capacitors CE31, CE32, and CE33 are all grounded.

[0036] LGATE pin -4 is connected to the first end of resistor R9 and the gate of MOS transistor Q4, respectively, and the second end of resistor R9 is grounded;

[0037] GND1 pin -9 ground;

[0038] The GND pin is connected to the first end of resistor R2, and the second end of resistor R2 is grounded.

[0039] The buck IC U26 used is an IC from the UP1542 series.

[0040] The buck IC U26 used is model UP1542SSU8 SOP8.

[0041] The voltage at pin FB-6 of the buck IC U26 is 0.6V.

[0042] Through the above circuit, the voltage at pin FB-6 of the buck IC U26 in this invention is 0.6V. Simultaneously, the default V_SM voltage is supplied to DDR4. DDR4, according to the JEDEC specification, is 1.2V, and DDR3 is 1.5V. Therefore, when a DDR4 memory is inserted into the slot, DDR3_DET is floating but has a pull-up resistor R52. Thus, pin 6 of the buck IC U26 (i.e., pin FB-6) has a 2kΩ resistor to ground, calculating the output V_SM voltage to be 1.2V. When a DDR3 memory is inserted, DDR3_DET is pulled low by the memory module, resulting in pin 6 of the buck IC U26 (i.e., pin FB-6) having a 4.7kΩ resistor and a 2kΩ resistor in parallel to ground. Finally, V_SM is calculated to be 1.5V. Therefore, by utilizing the floating GND pin on the slot, a design is achieved where DDR3 and DDR4 share a single buck. This design is flexible and convenient. Note: DDR4 and DDR3 modules cannot be inserted simultaneously. That is, on the same motherboard, only DDR4 modules or only DDR3 modules can be installed. You cannot have DDR4 in one channel and DDR3 in another. This is because the circuit design switches the output voltage based on changes in the level of the detection pins; simultaneous insertion will cause the detection logic to malfunction and prevent the correct supply voltage.

[0043] In summary, when a DDR3 memory module is inserted into the buck power supply motherboard circuit of this utility model, DDR3_DET is pulled low by the memory module. At this time, the resistance to ground of pin -6 of buck IC U26 becomes a parallel connection of a 4.7k resistor and a 2k resistor.

[0044] Similarly, based on the voltage output calculation formula of the buck power supply motherboard circuit, the output V_SM voltage can be calculated to be 1.5V, which meets the power supply requirements of DDR3 memory modules.

[0045] The working principle of other parts of the circuit is similar to that when inserting a DDR4 memory stick. Each pin and component works together according to the predetermined circuit connection method to convert the input VCC12 voltage into a 1.5V power supply voltage suitable for DDR3 memory sticks through the buck power supply motherboard circuit.

[0046] Through the above circuit, the compatibility of this utility model is improved: Through a unique circuit design, this utility model enables a motherboard to be compatible with both DDR3 and DDR4 memory modules, greatly improving the applicability of the motherboard. Users can flexibly choose to use DDR3 or DDR4 memory modules according to their needs and actual situation without replacing the motherboard.

[0047] Through the above circuit, the cost of this utility model is reduced: compared with the traditional design that requires two BUCK ICs to power the DDR3 and DDR4 memory modules respectively, this utility model only uses one buck IC to complete the power supply task for the two memory modules, reducing the number of electronic components used and reducing the production cost of the motherboard.

[0048] Through the above circuit, this utility model is ingeniously and flexibly designed: it cleverly uses a floating GND pin on the DDR3 memory slot as a detection pin, and identifies the type of inserted memory module by the level change of this pin, thereby controlling the buck IC to output different voltages, achieving compatibility with memory modules with different power supply requirements. The design concept is novel and flexible.

[0049] The above description is only a preferred embodiment of the present utility model and does not limit the patent scope of the present utility model. Any equivalent structural or procedural transformations made based on the contents of the present utility model specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of the present utility model.

Claims

1. A motherboard circuit for DDR3 and DDR4 sharing a buck power supply based on memory type identification, characterized in that, The circuit includes a buck circuit, which includes a buck IC U26, and the circuits connected to the pins of the buck IC U26 include: Pin FB-6 is connected to the first terminals of resistors R7, R10, R50, and R33, and the first terminal of capacitor C7. The second terminal of resistor R7 is connected to the first terminal of resistor R8, and the second terminal of resistor R8 is grounded. The second terminal of resistor R33 is grounded. The second terminal of resistor R50 is connected to the collector of transistor Q7, and the emitter of transistor Q7 is grounded. The base of transistor Q7 is connected to the first terminal of resistor R51 and the collector of transistor Q8, and the emitter of transistor Q8 is grounded. The base of transistor Q8 is connected to the first terminal of resistor R52 and the DDR3_DET circuit. The second terminal of resistor R51 is connected to the +3V3_DUAL circuit, and the second terminal of resistor R52 is connected to the +3V3_DUAL circuit. OCSET / PH pin-7 is connected to the first terminal of capacitor C5, the second terminal of capacitor C5 is connected to the first terminal of resistor R8, resistor R6 and capacitor C6 are connected in series and then in parallel with capacitor C5, and OCSET / PH pin-7 also outputs the VSM_C23_EN circuit; VCC pin -5 is connected to resistor R30 and capacitor C41 respectively. The other end of resistor R30 is connected to VCC12, and the other end of capacitor C41 is grounded. BOOT pin-1 is connected to resistor R31, and the other end of resistor R31 is connected to the first end of capacitor C43. UGATE pin-2 is connected to the gate of MOSFET Q3. The drain of MOSFET Q3 is connected to the first terminal of inductor L10 and the first terminal of capacitor C42. The second terminal of inductor L10 is connected to VCC12. The second terminal of capacitor C42 is grounded. Capacitor C42 is also connected in parallel with a polarized capacitor CE44 and a capacitor C102. The negative terminal of polarized capacitor CE44 is connected to the second terminal of capacitor C42. The source of MOSFET Q3 is connected to the second terminal of capacitor C43. PHASE pin -8 is connected to the drain of MOSFET Q4, the first terminal of resistor R32, and the first terminal of inductor L2. The drain of MOSFET Q4 is connected to the source of MOSFET Q3. The second terminal of resistor R32 is connected to the first terminal of capacitor C44. The second terminal of capacitor C44 is grounded. The second terminal of inductor L2 is connected to the positive terminals of polarized capacitors CE31, CE32, and CE33, the V_SM_C23 circuit, the second terminal of resistor R10, and the second terminal of capacitor C7. The source of MOSFET Q4 is grounded. The negative terminals of polarized capacitors CE31, CE32, and CE33 are all grounded. LGATE pin -4 is connected to the first end of resistor R9 and the gate of MOS transistor Q4, respectively, and the second end of resistor R9 is grounded; GND1 pin -9 ground; The GND pin is connected to the first end of resistor R2, and the second end of resistor R2 is grounded.

2. The DDR3 and DDR4 shared buck power supply motherboard circuit based on memory type identification according to claim 1, characterized in that, The buck IC U26 used is an IC from the UP1542 series.

3. The DDR3 and DDR4 shared buck power supply motherboard circuit based on memory type identification according to claim 2, characterized in that, The buck IC U26 used is model UP1542SSU8 SOP8.

4. The DDR3 and DDR4 shared buck power supply motherboard circuit based on memory type identification according to claim 1, characterized in that, The voltage at pin FB-6 of the buck IC U26 is 0.6V.

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