High electron mobility transistor

Abstract

The embodiment of the utility model relates to a high-electron-mobility transistor, and the transistor comprises a substrate which is provided with a first surface and a second surface which are opposite to each other, and is a heavily-doped conductive substrate; the grid electrode and the source electrode are distributed on the first surface side at intervals; the heterojunction structure is located on the first surface side and located between the substrate and the grid electrode, and the heterojunction structure comprises a channel layer and a barrier layer which are sequentially stacked in the direction away from the substrate; the drain electrode through hole penetrates through the heterojunction structure and extends to the substrate; the drain electrode is filled in the drain electrode through hole; the drain electrode bonding pad is located on the second surface side, and the drain electrode bonding pad is conductively connected with the drain electrode through the substrate. Therefore, stray capacitance is reduced, and device performance is guaranteed.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a high electron mobility transistor. Background Technology

[0002] High Electron Mobility Transistor (HEMT) is a field-effect transistor based on the high mobility characteristics of two-dimensional electron gas (2DEG) in a heterojunction structure. It has high electron mobility at low temperature and low electric field, enabling high-speed and low-noise operation.

[0003] In HEMTs, the source, gate, and drain are typically formed on the front side of the device structure. This electrode arrangement makes HEMT packaging incompatible with the conventional packaging of current power devices, resulting in poor process compatibility. To achieve packaging, metal interconnection processes are usually performed on the front side of the device to bring out the source, gate, and drain through the metal interconnection layer. This increases the process flow and production costs. Furthermore, when the device is operating, the metal interconnection layer introduces parasitic capacitance, reducing high-frequency switching efficiency and affecting device performance. Utility Model Content

[0004] In view of this, embodiments of this application provide a high electron mobility transistor to solve at least one problem existing in the prior art.

[0005] In a first aspect, embodiments of this application provide a high electron mobility transistor, comprising:

[0006] A substrate having a first surface and a second surface opposite to each other, wherein the substrate is a heavily doped conductive substrate;

[0007] The gate and source are spaced apart on the first surface side;

[0008] A heterojunction structure is located on the first surface side and between the substrate and the gate. The heterojunction structure includes a channel layer and a barrier layer stacked sequentially in a direction away from the substrate.

[0009] A drain via penetrates the heterojunction structure and extends to the substrate;

[0010] Drain electrode, filling the drain via;

[0011] A drain pad is located on the second surface side, and the drain pad is electrically connected to the drain through the substrate.

[0012] In conjunction with a first aspect of this application, in an alternative embodiment, the drain includes a first ohmic contact layer and a first conductive fill layer, wherein the first ohmic contact layer is located at least between the first conductive fill layer and the substrate.

[0013] In conjunction with the first aspect of this application, in an alternative embodiment, the first ohmic contact layer is further located between the first conductive fill layer and the heterojunction structure.

[0014] In conjunction with the first aspect of this application, in an optional embodiment, the first ohmic contact layer covers the sidewall and bottom wall of the drain via, the first conductive filler layer fills the first ohmic contact layer, and the ratio of the linewidth of the first ohmic contact layer to the linewidth of the first conductive filler layer is in the range of 1:10-1:5.

[0015] In conjunction with the first aspect of this application, in an optional embodiment, the material of the first conductive filling layer includes at least one of W, AlSiCu alloy, and AlCu alloy, and the material of the first ohmic contact layer includes at least one of Ti, TiAl alloy, and TiNi alloy.

[0016] In conjunction with the first aspect of this application, in an alternative embodiment, the drain via extends into the interior of the substrate.

[0017] In conjunction with the first aspect of this application, in an optional embodiment, it further includes: a first interlayer dielectric layer located on the first surface side and covering the heterojunction structure, the gate, and the drain;

[0018] The source via penetrates the first interlayer dielectric layer and extends to the heterojunction structure;

[0019] The source electrode is filled within the source electrode via;

[0020] The source electrode includes a second ohmic contact layer and a second conductive filling layer, wherein the second ohmic contact layer is located at least between the second conductive filling layer and the heterojunction structure.

[0021] In conjunction with the first aspect of this application, in an optional embodiment, the second ohmic contact layer covers the sidewall and bottom wall of the source via, the second conductive fill layer fills the second ohmic contact layer, and the ratio of the linewidth of the second ohmic contact layer to the linewidth of the second conductive fill layer is in the range of 1:10-1:5.

[0022] In conjunction with the first aspect of this application, in an alternative embodiment, the second ohmic contact layer extends to cover a portion of the first interlayer dielectric layer;

[0023] It also includes: a second interlayer dielectric layer, located on the first surface side, and covering the first interlayer dielectric layer and the source electrode;

[0024] A source connection via penetrates the second interlayer dielectric layer and extends to the source electrode;

[0025] A source connection structure is filled within the source connection via.

[0026] In conjunction with the first aspect of this application, in an optional embodiment, the drain further includes a first protective layer located between the first conductive filling layer and the first ohmic contact layer;

[0027] The material of the first protective layer includes TiN.

[0028] The high electron mobility transistor provided in this application embodiment has a drain via that penetrates the heterojunction structure and extends to the substrate. The drain is formed in the drain via, and a heavily doped conductive substrate is used to make the drain electrically connected to the substrate, thus achieving back-side lead-out of the drain. Therefore, in HEMT, the source and gate are located on the front side of the device, and the drain is located on the back side of the device. This electrode arrangement is compatible with existing packaging methods, facilitates packaging design, reduces the fabrication of metal interconnect layers, saves process and cost, alleviates the problem of parasitic capacitance introduced by metal interconnect layers, and ensures device performance.

[0029] Additional aspects and advantages of this application will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of this application. Attached Figure Description

[0030] The accompanying drawings, which are included to provide a further understanding of this application and form part of this application, illustrate exemplary embodiments and are used to explain this application, but do not constitute an undue limitation of this application. In the drawings:

[0031] Figure 1 A schematic cross-sectional structure of a high electron mobility transistor provided for related technologies;

[0032] Figure 2 A schematic cross-sectional view of a high electron mobility transistor provided in an embodiment of this application;

[0033] Figures 3 to 15 This is a cross-sectional structural diagram of the high electron mobility transistor provided in the embodiments of this application during the fabrication process. Detailed Implementation

[0034] Exemplary embodiments of the present application will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the present application are shown in the drawings, it should be understood that the present application may be implemented in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided to enable a more thorough understanding of the present application and to fully convey the scope of the disclosure of the present application to those skilled in the art.

[0035] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of this application. However, it will be apparent to those skilled in the art that this application can be practiced without one or more of these details. In other instances, to avoid confusion with this application, some technical features well-known in the art have not been described; that is, not all features of actual embodiments are described herein, nor are well-known functions and structures described in detail.

[0036] In the accompanying drawings, for clarity, the dimensions of layers, areas, and elements, as well as their relative dimensions, may be exaggerated. The same reference numerals denote the same elements throughout.

[0037] When an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. Although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this application, the first element, component, area, layer, or portion discussed below may be referred to as a second element, component, area, layer, or portion. And the discussion of a second element, component, area, layer, or portion does not imply that the first element, component, area, layer, or portion necessarily exists in this application.

[0038] Spatial relation terms such as “below,” “under,” “below,” “below,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. In addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below,” “below,” or “below” will be oriented “above” the other element or feature. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0039] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the scope of this application. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising” and / or “including,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0040] To fully understand this application, detailed steps and structures will be presented in the following description to illustrate the technical solution of this application. Preferred embodiments of this application are described in detail below; however, in addition to these detailed descriptions, this application may have other implementation methods.

[0041] Figure 1This is a cross-sectional schematic diagram of a high electron mobility transistor (HMT) in related technologies. As shown in the figure, the HMT includes: a substrate 100 having a first surface 101 and a second surface 102 opposite to each other; a heterojunction structure 120 located on the first surface 101, the heterojunction structure 120 including a channel layer 121 and a barrier layer 122 sequentially stacked along a direction away from the substrate 100; a source 500, a gate 300, and a drain 600, spaced apart on the first surface 101 side of the substrate 100; a metal interconnect layer 130 located on the first surface 101 side, covering the source 500, the gate 300, and the drain 600, and conductively leading out the source 500, the gate 300, and the drain 600 respectively; and a top metal layer 140 located on the metal interconnect layer 130, conductively connected to the source 500, the gate 300, and the drain 600 through the metal interconnect layer 130. As can be seen, in a conventional HEMT, the source 500, gate 300, and drain 600 are all located on the front side of the device. This electrode arrangement makes it difficult to be compatible with the packaging lead configuration of other power devices.

[0042] The metal interconnect layer 130 includes conductive interconnect structures and interlayer dielectric layers. The interlayer dielectric layers include a first interlayer dielectric layer 410 and a second interlayer dielectric layer 420. The metal interconnect structures include a first conductive connection structure 131, an intermediate metal layer 132, and a second conductive connection structure 133 sequentially conductively connected along a direction away from the substrate 100. It should be understood that the figure only shows two interlayer dielectric layers as an example. In practical applications, the metal interconnect layer 130 may obviously include more interlayer dielectric layers, and correspondingly more conductive interconnect structures and intermediate metal layers. Thus, the top metal layer 140 must be conductively connected to the electrode at least sequentially through the second conductive connection structure 133, the intermediate metal layer 132, and the first conductive connection structure 131. This results in complex conductive circuitry, making it prone to parasitic capacitance, and the multiple layers of the metal interconnect layer 130 increase the process complexity and cost.

[0043] Based on this, the embodiments of this application provide a high electron mobility transistor, please refer to... Figure 2 High electron mobility transistors include:

[0044] Substrate 100 has a first surface 101 and a second surface 102 opposite to each other, and substrate 100 is a heavily doped conductive substrate;

[0045] Gate 300 and source 500 are spaced apart on the first surface 101 side;

[0046] The heterojunction structure 120 is located on the first surface 101 side and between the substrate 100 and the gate 300. The heterojunction structure 120 includes a channel layer 121 and a barrier layer 122 stacked sequentially in a direction away from the substrate 100.

[0047] Drain via 601 penetrates the heterojunction structure 120 and extends to the substrate 100;

[0048] Drain 600 is filled in drain via 601;

[0049] Drain pad 610 is located on the second surface 102 side and is electrically connected to drain 600 through substrate 100.

[0050] The HEMT provided in this application embodiment has a drain via 601 that penetrates the heterojunction structure 120 and extends to the substrate 100. The drain 600 is formed in the drain via 601. By using a heavily doped conductive substrate, the drain 600 is electrically connected to the substrate 100, and the drain 600 is led out from the back side. Thus, in the HEMT, the source 500 and the gate 300 are located on the front side of the device, and the drain 600 is located on the back side of the device. This electrode arrangement is compatible with existing packaging methods, facilitates packaging design, reduces the fabrication of metal interconnect layers, saves process and cost, alleviates the problem of parasitic capacitance introduced by metal interconnect layers, and ensures device performance.

[0051] The substrate 100 can be made of any suitable semiconductor material known to those skilled in the art, including but not limited to germanium and silicon. In this embodiment, the substrate 100 is specifically made of silicon, for example. Understandably, in actual fabrication, a doping process can be performed during the growth of the semiconductor material to obtain a heavily doped semiconductor material. Compared to conductors such as metals, semiconductor materials have weaker conductivity. By heavily doping the semiconductor material, its conductivity can be effectively enhanced, ensuring the conductive connection between the drain 600 and the drain pad 610.

[0052] The substrate 100 can be doped with either N-type or P-type doping, and this application does not limit either type.

[0053] In the heterojunction structure 120, a two-dimensional electron gas channel 123 is formed in at least a portion of the channel layer 121 near the barrier layer 122. Specifically, the band gap width of the barrier layer 122 is larger than that of the channel layer 121, causing electrons in the wide-bandgap barrier layer 122 and electrons on the surface of the barrier layer 122 to overflow and move toward the interface of the channel layer 121 near the barrier layer 122, where they are confined in a potential well formed at the interface, thereby forming a two-dimensional electron gas (2DEG).

[0054] The channel layer 121 can be made of N-group alloy materials, including but not limited to GaN, AlGaN, InGaN, InAlGaN, InAlScN, AlScN, InScN, etc. Furthermore, the channel layer 121 can be an undoped material layer (e.g., an undoped GaN layer), thereby causing the channel layer 121 to exhibit high resistance at least in the portion below the two-dimensional electron gas.

[0055] The material of the barrier layer 122 includes any material capable of forming a two-dimensional electron gas channel 123 with the channel layer 121. Specifically, the material of the barrier layer 122 can also be an N-group alloy material, such as gallium nitride-based alloys, specifically one or more of AlGaN, AlScN, InAlGaN, etc. Furthermore, the material of the barrier layer 122 can be an undoped material (e.g., an undoped AlGaN layer); or, the barrier layer 122 can also be an N-doped material layer (e.g., an N-type doped AlGaN layer), thus facilitating the induction of a higher density two-dimensional electron gas.

[0056] In this embodiment, the channel layer 121 is made of GaN; the barrier layer 122 is made of AlGaN. GaN and AlGaN constitute a heterojunction structure 120.

[0057] In some embodiments, the HEMT further includes a buffer layer 110 located between the substrate 100 and the heterojunction structure 120. The buffer layer 110 relieves interfacial stress, reduces defect density, and reduces static current leakage of the device, thereby improving device performance.

[0058] In this embodiment, the material of the buffer layer 110 includes GaN. Of course, the material of the buffer layer 110 can be any suitable semiconductor material well known in the art, and this embodiment does not limit it.

[0059] In some embodiments, the HEMT further includes a first dielectric layer 200 covering the heterojunction structure 120, thereby protecting the heterojunction structure 120. Understandably, the portion of the first dielectric layer 200 corresponding to the gate 300 serves as a gate dielectric layer.

[0060] In this embodiment, the first dielectric layer 200 includes an oxide layer. Of course, the material of the first dielectric layer 200 can be any dielectric material well known in the art, and this embodiment does not limit this.

[0061] In some embodiments, the drain via 601 extends into the substrate 100. In this case, the bottom surface and part of the side surface of the drain 600 are in contact with the substrate 100, resulting in a large contact area. This helps reduce contact resistance, enhances device performance, and anchors the drain 600 to the substrate 100, improving the mechanical reliability of the device. It should be noted that... Figure 2 Taking the example of the drain via 601 extending into the interior of the substrate 100, in some other embodiments, the drain via 601 may also extend to the first surface 101 of the substrate 100, which reduces the difficulty of etching the via while ensuring the conductive connection between the drain 600 and the substrate 100.

[0062] In some embodiments, please refer to Figure 2 The drain 600 includes a first ohmic contact layer 710 and a first conductive filling layer 810, with the first ohmic contact layer 710 located at least between the first conductive filling layer 810 and the substrate 100. Thus, the first ohmic contact layer 710 achieves ohmic contact between the first conductive filling layer 810 and the substrate 100, reducing contact resistance and helping to ensure device performance.

[0063] Optionally, the material of the first conductive filling layer 810 includes at least one of W, AlSiCu alloy, and AlCu alloy, and the material of the first ohmic contact layer 710 includes at least one of Ti, TiAl alloy, and TiNi alloy.

[0064] In one specific example, the material of the first conductive filling layer 810 includes an AlSiCu alloy, wherein the atomic ratio of the AlSiCu alloy is Al:Si:Cu = 98:X:Y, 0 < X ​​< 2, Y = 2 - X.

[0065] In one specific example, the material of the first conductive filling layer 810 includes an AlCu alloy, wherein the atomic ratio of the AlCu alloy is Al:Cu = 98:2.

[0066] Of course, the embodiments of this application do not exclude the possibility that the materials of the first conductive filling layer 810 and the first ohmic contact layer 710 are any suitable materials known to those skilled in the art. Materials with good conductivity and high adhesion can be selected as the material of the first ohmic contact layer 710 based on the materials of the substrate 100 and the first conductive filling layer 810, thereby ensuring the stability of the contact while achieving ohmic contact. Materials with good conductivity and high oxidation resistance can be selected as the material of the first conductive filling layer 810, thereby forming a good conductive channel with the first ohmic contact layer 710 while avoiding the drain 600 from being oxidized and causing a decrease in conductivity.

[0067] In some embodiments, the first ohmic contact layer 710 is also located between the first conductive fill layer 810 and the heterojunction structure 120. This allows the drain 600 to form a good ohmic contact with the heterojunction structure 120.

[0068] Optionally, the first ohmic contact layer 710 covers the sidewall and bottom wall of the drain via 601, and the first conductive fill layer 810 fills the first ohmic contact layer 710. The ratio of the linewidth of the first ohmic contact layer 710 to the linewidth of the first conductive fill layer 810 is in the range of 1:10-1:5.

[0069] Understandably, if the linewidth ratio of the two layers is too small, in other words, the thickness of the first ohmic contact layer 710 is too small, it may lead to insufficient ohmic contact, affecting current flow efficiency, reducing device performance, and potentially causing insufficient adhesion, affecting the stability and reliability of the drain 600. Furthermore, it is difficult to precisely control its thickness during actual fabrication, resulting in a narrow process window and increased fabrication difficulty. Conversely, if the linewidth ratio is too large, the first conductive filler layer 810 may be too thin, potentially leading to insufficient oxidation resistance of the drain 600, making it susceptible to oxidation during device use. During actual fabrication, the narrow process window for the first conductive filler layer 810 increases filling difficulty, resulting in incomplete filling or voids, affecting conductivity. Therefore, controlling the linewidth ratio of the first ohmic contact layer 710 to the first conductive filler layer 810 within the range of 1:10 to 1:5 is more beneficial for improving device performance.

[0070] In one optional specific example, the cross-sectional shape of the first ohmic contact layer 710 is annular in the direction perpendicular to the thickness of the substrate 100; the ratio of the annular width of the first ohmic contact layer 710 to the diameter of the first conductive fill layer 810 is in the range of 1:10-1:5.

[0071] In some embodiments, the drain 600 may further include a first protective layer (not shown in the figure), which is located between the first conductive filling layer 810 and the first ohmic contact layer 710; the material of the first protective layer may include TiN.

[0072] In some embodiments, please refer to Figure 2 The HEMT further includes: a first interlayer dielectric layer 410 located on the first surface 101 side, covering the heterojunction structure 120, the gate 300, and the drain 600; a source via 501 penetrating the first interlayer dielectric layer 410 and extending to the heterojunction structure 120; a source 500 filling the source via 501; the source 500 including a second ohmic contact layer 720 and a second conductive fill layer 820, the second ohmic contact layer 720 being at least located between the second conductive fill layer 820 and the heterojunction structure 120. Thus, the second ohmic contact layer 720 achieves ohmic contact between the second conductive fill layer 820 and the heterojunction structure 120, reducing contact resistance and helping to ensure device performance.

[0073] Optionally, the material of the second conductive filling layer 820 includes at least one of W, AlSiCu alloy, and AlCu alloy, and the material of the second ohmic contact layer 720 includes at least one of Ti, TiAl alloy, and TiNi alloy.

[0074] In one specific example, the material of the second conductive filling layer 820 includes an AlSiCu alloy, wherein the atomic ratio of the AlSiCu alloy is Al:Si:Cu = 98:X:Y, 0 < X ​​< 2, Y = 2 - X.

[0075] In one specific example, the material of the second conductive filling layer 820 includes an AlCu alloy, wherein the atomic ratio of the AlCu alloy is Al:Cu = 98:2.

[0076] Optionally, the second ohmic contact layer 720 covers the sidewall and bottom wall of the source via 501, and the second conductive fill layer 820 fills the second ohmic contact layer 720. The ratio of the linewidth of the second ohmic contact layer 720 to the linewidth of the second conductive fill layer 820 is in the range of 1:10-1:5. Understandably, if the linewidth ratio of the two layers is too small, in other words, the thickness of the second ohmic contact layer 720 is too small, it may lead to insufficient ohmic contact with the heterojunction structure 120, affecting current flow efficiency, reducing device performance, and potentially causing insufficient adhesion, affecting the stability and reliability of the source 500. Furthermore, it is difficult to precisely control its thickness during actual fabrication, resulting in a narrow process window and increased fabrication difficulty. Conversely, if the linewidth ratio is too large, the second conductive filler layer 820 may be too thin, potentially leading to insufficient oxidation resistance of the source 500, making it susceptible to oxidation during device use. In actual fabrication, the narrow process window for the second conductive filler layer 820 increases filling difficulty, resulting in incomplete filling or voids, affecting conductivity. Therefore, controlling the linewidth ratio of the second ohmic contact layer 720 to the second conductive filler layer 820 within the range of 1:10 to 1:5 is more beneficial for improving device performance.

[0077] In one optional specific example, the cross-sectional shape of the second ohmic contact layer 720 is annular in the direction perpendicular to the thickness of the substrate 100; the ratio of the annular width of the second ohmic contact layer 720 to the diameter of the second conductive fill layer 820 is in the range of 1:10-1:5.

[0078] In some embodiments, the source via 501 extends into the heterojunction structure 120. In this case, the bottom surface and part of the side surface of the source 500 are in contact with the heterojunction structure 120, resulting in a large contact area. This helps reduce contact resistance, enhances device performance, and anchors the source 500 to the heterojunction structure 120, enhancing the mechanical reliability of the device. In this embodiment, since part of the side surface of the source 500 is also in contact with the heterojunction structure 120, the second ohmic contact layer 720 covers the sidewall of the source via 501 located within the heterojunction structure 120. In the direction perpendicular to the thickness of the substrate 100, the cross-sectional shape of the second ohmic contact layer 720 is annular. The ratio of the annular width of the second ohmic contact layer 720 to the diameter of the second conductive filling layer 820 also affects the ohmic contact effect of the second ohmic contact layer 720.

[0079] In some embodiments, the source 500 may further include a second protective layer (not shown in the figure), which is located between the second conductive filling layer 820 and the second ohmic contact layer 720; the material of the second protective layer may include TiN.

[0080] Understandably, please refer to the following when actually preparing the product. Figure 3 First, a buffer layer 110, a channel layer 121, and a barrier layer 122 are sequentially formed on a substrate 100, wherein the channel layer 121 and the barrier layer 122 constitute a heterojunction structure 120; then, please refer to... Figure 4 A first dielectric layer 200 is formed on the heterojunction structure 120; please refer to Figure 5 A gate material layer is formed on the first dielectric layer 200, and a first patterning process is performed to obtain the gate 300; next, please refer to Figure 6 A first interlayer dielectric layer 410 is deposited, which covers the first dielectric layer 200 and the gate 300; then, please refer to... Figure 7 A second patterning process is performed to form source via 501, which exposes the heterojunction structure 120; please refer to... Figure 8 The third patterning process is then performed to form a drain via 601, which exposes the substrate 100. Next, please refer to... Figure 9 An ohmic contact layer material 700 is deposited, covering the inner wall of the source via 501, the inner wall of the drain via 601, and the second interlayer dielectric layer 420. Then, a protective layer material (not shown in the figure) is deposited, covering the ohmic contact layer material 700. Please refer to... Figure 10 A conductive filler layer material (not shown in the figure) is deposited, and the conductive filler layer material is etched back to form a first conductive filler layer 810 and a second conductive filler layer 820; then, please refer to... Figure 11The fourth patterning process is performed to remove part of the ohmic contact layer material 700 and the protective layer material, forming a first ohmic contact layer 710 and a second ohmic contact layer 720, as well as a first protective layer (not shown in the figure) and a second protective layer (not shown in the figure), thereby constituting the source 500 and the drain 600; finally, please refer to Figure 2 The substrate 100 is thinned from the second surface 102 side, and a backside metallization process is performed to form the drain pad 610. Thus, the drain 600 is brought out from the backside through the drain via 601 and the heavily doped conductive substrate.

[0081] Please refer to Figure 8 Since the drain via 601 needs to penetrate the first interlayer dielectric layer 410, the first dielectric layer 200, the heterojunction structure 120 and the buffer layer 110 to expose the substrate 100, the source via 501 can be understood as a deep trench, and the third patterning process can be specifically understood as deep trench etching. In some related technologies, during the third patterning process, the substrate 100 is etched through, so that the drain via 601 penetrates the first interlayer dielectric layer 410, the first dielectric layer 200, the heterojunction structure 120, the buffer layer 110, and the substrate 100. The bottom surface of the drain 600 and the second surface 102 of the substrate 100 form a complete plane. At this time, the drain pad 610 on the second surface 102 directly contacts the drain 600. The etching of the drain via 601 is difficult and has high process requirements. In the embodiment of this application, with the synergistic effect of the heavily doped conductive substrate, the drain via 601 only needs to expose the substrate 100 so that the subsequently filled drain 600 can directly contact the substrate 100. This allows the drain 600 to be electrically connected to the heavily doped conductive substrate, and the process difficulty is lower.

[0082] In some embodiments, please refer to Figure 9 and Figure 11 The first ohmic contact layer 710 and the second ohmic contact layer 720 are made of the same material; the first ohmic contact layer 710 and the second ohmic contact layer 720 are prepared in the same process.

[0083] In some embodiments, the first protective layer and the second protective layer are made of the same material; the first protective layer and the second protective layer are prepared in the same process.

[0084] In some embodiments, please refer to Figure 10 The first conductive filling layer 810 and the second conductive filling layer 820 are made of the same material; the first conductive filling layer 810 and the second conductive filling layer 820 are prepared in the same process.

[0085] In some embodiments, please refer to Figure 2The second ohmic contact layer 720 extends to cover a portion of the first interlayer dielectric layer 410; the HEMT also includes: a second interlayer dielectric layer 420 located on the first surface 101 side and covering the first interlayer dielectric layer 410 and the source 500; a source connection via 502 penetrating the second interlayer dielectric layer 420 and extending to the source 500; and a source connection structure 510 filling the source connection via 502.

[0086] Understandably, please refer to the following when actually preparing the product. Figure 12 First, a second interlayer dielectric layer 420 is deposited, covering the source 500, drain 600, and the first interlayer dielectric layer 410. Then, a planarization process is performed on the second interlayer dielectric layer 420. Afterwards, please refer to... Figure 13 The fifth patterning process is performed to form source connection via 502, which exposes the source electrode 500; then, please refer to... Figure 14 Deposit metallic materials to form source connection structure 510 and source pad 520.

[0087] Please refer to the details. Figure 11 During the fourth patterning process, by etching the ohmic contact layer material 700 through a mask, a portion of the ohmic contact layer material 700 covering the first interlayer dielectric layer 410 can be retained. This allows a portion of the final second ohmic contact layer 720 to extend and cover the first interlayer dielectric layer 410. Consequently, the cross-sectional area of ​​the source electrode 500 is larger in the direction perpendicular to the substrate thickness. Then, during the subsequent fifth patterning process, when etching the source via 501, the requirements for interlayer overlay accuracy can be reduced, making process alignment easier. The source connection via 502 can better and more easily expose the source electrode 500, reducing deviation.

[0088] Please refer to Figure 2 The HEMT also includes: a source pad 520 located on the first surface 101, covering the second interlayer dielectric layer 420 and the source interconnect structure 510. The source pad 520 is electrically connected to the source 500 through the source interconnect structure 510. For actual fabrication, please refer to... Figure 14 After the source connection structure 510 is fabricated, the current process can be continued to fabricate the source pad 520.

[0089] Please refer to Figure 2 The HEMT also includes a passivation layer 900, located on the source pad 520 and exposing a portion of the source pad 520. This provides insulation protection for the source pad 520 and exposes a portion of the source pad 520 to facilitate conductive connections. Please refer to [the relevant documentation] for actual fabrication. Figure 15 First, a passivation layer 900 can be deposited, and then a sixth patterning process can be performed to expose part of the source pad 520, so that the source 500 can be brought out on the front side of the device.

[0090] This application also provides a semiconductor integrated structure, including the high electron mobility transistor provided in the above embodiments. It is understood that because the performance of the high electron mobility transistor provided in the above embodiments is guaranteed, the semiconductor integrated structure has better yield and more stable performance.

[0091] It should be understood that the above embodiments are exemplary and not intended to encompass all possible implementations. Various modifications and changes can be made to the above embodiments without departing from the scope of this disclosure. Similarly, the various technical features of the above embodiments can be arbitrarily combined to form other embodiments of this application that may not be explicitly described. Therefore, the above embodiments only illustrate several implementations of this application and do not limit the scope of protection of this patent application.

Claims

1. A high electron mobility transistor, characterized in that, include: A substrate having a first surface and a second surface opposite to each other, wherein the substrate is a heavily doped conductive substrate; The gate and source are spaced apart on the first surface side; A heterojunction structure is located on the first surface side and between the substrate and the gate. The heterojunction structure includes a channel layer and a barrier layer stacked sequentially in a direction away from the substrate. A drain via penetrates the heterojunction structure and extends to the substrate; Drain electrode, filling the drain via; A drain pad is located on the second surface side, and the drain pad is electrically connected to the drain through the substrate.

2. The high electron mobility transistor according to claim 1, characterized in that, The drain includes a first ohmic contact layer and a first conductive filling layer, wherein the first ohmic contact layer is located at least between the first conductive filling layer and the substrate.

3. The high electron mobility transistor according to claim 2, characterized in that, The first ohmic contact layer is also located between the first conductive fill layer and the heterojunction structure.

4. The high electron mobility transistor according to claim 2 or 3, characterized in that, The first ohmic contact layer covers the sidewall and bottom wall of the drain via, and the first conductive fill layer fills the first ohmic contact layer. The ratio of the linewidth of the first ohmic contact layer to the linewidth of the first conductive fill layer is in the range of 1:10-1:

5.

5. The high electron mobility transistor according to claim 1, characterized in that, The drain via extends into the interior of the substrate.

6. The high electron mobility transistor according to claim 1, characterized in that, Also includes: A first interlayer dielectric layer is located on the first surface side and covers the heterojunction structure, the gate, and the drain. The source via penetrates the first interlayer dielectric layer and extends to the heterojunction structure; The source electrode is filled within the source electrode via; The source electrode includes a second ohmic contact layer and a second conductive filling layer, wherein the second ohmic contact layer is located at least between the second conductive filling layer and the heterojunction structure.

7. The high electron mobility transistor according to claim 6, characterized in that, The second ohmic contact layer covers the sidewalls and bottomwalls of the source via, and the second conductive fill layer fills the second ohmic contact layer. The ratio of the linewidth of the second ohmic contact layer to the linewidth of the second conductive fill layer is in the range of 1:10-1:

5.

8. The high electron mobility transistor according to claim 6, characterized in that, The second ohmic contact layer extends to cover a portion of the first interlayer dielectric layer; It also includes: a second interlayer dielectric layer, located on the first surface side, and covering the first interlayer dielectric layer and the source electrode; A source connection via penetrates the second interlayer dielectric layer and extends to the source electrode; A source connection structure is filled within the source connection via.

9. The high electron mobility transistor according to claim 2 or 3, characterized in that, The drain electrode further includes a first protective layer, which is located between the first conductive filling layer and the first ohmic contact layer. The material of the first protective layer includes TiN.

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