Test circuit, chip and equipment
By designing a data selector and a scan bypass structure in the test circuit, the problem of parameter acquisition during chip testing was solved, enabling parameter acquisition and analysis in test mode and providing evidence of failure causes.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- BEIJING PINGTOUGE INFORMATION TECH CO LTD
- Filing Date
- 2025-04-07
- Publication Date
- 2026-05-19
AI Technical Summary
During chip testing, fluctuations in the chip's operating parameters can lead to test failures. Existing technologies cannot effectively analyze the causes of these failures because the components used to acquire parameters cannot properly obtain the operating parameters in the test mode after being inserted into the scan chain.
A test circuit was designed, including a first data selector, a sensor control scan bypass, and a logic unit. By switching the enable signal in different test modes, the normal parameter acquisition and output of the sensor control unit and the sensor unit in the test mode can be realized.
Without affecting chip testing, the operating parameters of the chip in test mode are obtained normally, providing a basis for analysis of the causes of chip test failures.
Smart Images
Figure CN224263326U_ABST
Abstract
Description
Technical Field
[0001] This utility model relates to the field of chip testing, and more specifically, to a test circuit, chip, and device. Background Technology
[0002] During chip testing, fluctuations in chip operating parameters can lead to test failures. Therefore, obtaining the chip's operating parameters in test mode is crucial for analyzing the causes of test failures. However, to ensure test coverage, components used to acquire chip operating parameters (e.g., sensor control units and sensor units) are often inserted into the scan chain. This makes it impossible to properly acquire the chip's operating parameters in test mode, thus hindering effective analysis of the causes of chip test failures. Utility Model Content
[0003] In view of this, the present invention provides a test circuit, chip, and device to obtain the chip's operating parameters in test mode without affecting chip testing, thereby providing an analytical basis for the cause of chip test failure.
[0004] In a first aspect, the present invention aims to provide a test circuit, the circuit comprising:
[0005] The first data selector includes a first input terminal, a second input terminal, and a first enable terminal, wherein the first input terminal is connected to the signal output terminal of the sensing control unit;
[0006] The sensor control scan bypass includes storage units connected in the form of a scan chain. One end of the sensor control scan bypass is connected to the signal receiving end of the sensor control unit, and the other end is connected to the second input end.
[0007] A logic unit, connected to the first enable terminal, is configured to output a first enable signal or a second enable signal to the first enable terminal in a first test mode, such that the first data selector is controlled by the first enable signal to select and output the test signal of the sensing control scan bypass, or is controlled by the second enable signal to select and output the sensing signal of the sensing control unit, wherein the sensing control unit is a non-test object in the first test mode.
[0008] Secondly, embodiments of this utility model aim to provide a chip, the chip comprising:
[0009] The test logic circuit is configured to generate a test signal and perform test logic on the chip based on the test signal;
[0010] The test circuit as described in the first aspect.
[0011] Thirdly, embodiments of the present invention aim to provide an electronic device, the electronic device comprising the chip described in the second aspect.
[0012] The test circuit of this application includes a first data selector, a sensor control scan bypass, and a logic unit. The first data selector includes a first input terminal, a second input terminal, and a first enable terminal. The first input terminal is connected to the signal output terminal of the sensor control unit. The sensor control scan bypass includes a storage unit connected in a scan chain, one end of which is connected to the signal receiving terminal of the sensor control unit, and the other end is connected to the second input terminal. The logic unit is connected to the first enable terminal and is configured to output a first enable signal or a second enable signal to the first enable terminal in a first test mode. This allows the first data selector to be controlled by the first enable signal to select and output the test signal of the sensor control scan bypass, or controlled by the second enable signal to select and output the sensor signal of the sensor control unit. Therefore, this embodiment can obtain the chip's operating parameters in test mode without affecting chip testing, thereby providing an analytical basis for the cause of chip test failure. Attached Figure Description
[0013] The above and other objects, features, and advantages of the present invention will become clearer from the following description of embodiments of the present application with reference to the accompanying drawings, in which:
[0014] Figure 1 This is a schematic diagram of the test circuit according to an embodiment of this application;
[0015] Figure 2 This is a circuit diagram of the test circuit in an embodiment of this application;
[0016] Figure 3 This is a schematic diagram of another test circuit according to an embodiment of this application;
[0017] Figure 4 This is a circuit diagram of another test circuit according to an embodiment of this application. Detailed Implementation
[0018] The present application is described below based on embodiments, but it is not limited to these embodiments. In the detailed description of the present application below, certain specific details are described in detail. Those skilled in the art can fully understand the present application without these details. To avoid obscuring the substance of the present application, well-known methods, processes, flows, elements, and circuits are not described in detail.
[0019] Furthermore, those skilled in the art should understand that the accompanying drawings provided herein are for illustrative purposes only and are not necessarily drawn to scale.
[0020] Furthermore, it should be understood that in the following description, "circuit" refers to a conductive loop consisting of at least one element or sub-circuit connected by electrical or electromagnetic connections. When an element or circuit is said to be "connected" to another element or "connected" between two nodes, it can be directly coupled or connected to another element, or there may be intermediate elements. The connection between elements can be physical, logical, or a combination thereof. Conversely, when an element is said to be "directly coupled to" or "directly connected" to another element, it means that there are no intermediate elements between them.
[0021] Unless the context explicitly requires it, words such as "including" or "contains" throughout the application should be interpreted as including rather than exclusive or exhaustive; that is, meaning "including but not limited to".
[0022] In the description of this application, it should be understood that the terms "first," "second," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance. Furthermore, in the description of this application, unless otherwise stated, "a plurality of" means two or more.
[0023] In this embodiment, a scan chain refers to one or more chain-like structures formed by connecting the storage units of circuit elements in a chip, such as flip-flops or latches. Inserting a circuit element into a scan chain can be understood as connecting the storage units belonging to the circuit element into the corresponding chain structure. The formed scan chain can achieve the testing of the circuit elements in the chip without affecting the normal operation of the chip. Specifically, when the chip is in normal mode, each storage unit in the scan chain can provide storage services for the circuit element to which it belongs, thereby ensuring the normal operation of the chip. When the chip is in test mode, each storage unit in the scan chain can be used as a shift register, allowing the test signal generation circuit to transmit test signals to or read test signals from each storage unit, thereby achieving the testing of the circuit elements in the chip. It should be understood that since the test signal generation circuit transmits test signals to the storage units to overwrite their original stored data when the chip is in test mode, the circuit elements inserted into the scan chain will not be able to perform their original functions when the chip is in test mode. For example, once the component used to acquire chip operating parameters is inserted into the scan chain, it will be unable to properly acquire and output the chip's operating parameters when the chip is in test mode.
[0024] The test circuit of this application embodiment is mainly described in detail based on ensuring that the sensing control unit and sensing unit can normally collect and output the chip's operating parameters when the chip is in test mode. However, it should be understood that the sensing control unit and sensing unit in this application embodiment can also be equivalently replaced by other circuit elements used to collect chip operating parameters, and this application does not limit this. Furthermore, in some embodiments, by adaptively adjusting the test circuit, the sensing control unit and sensing unit in this application embodiment can also be equivalently replaced by other related circuit elements so that the related circuit elements can normally perform their original functions when the chip is in test mode.
[0025] Figure 1 This is a schematic diagram of a test circuit according to an embodiment of this application. Figure 1 As shown, the test circuit includes a first data selector 11, a sensor control scan bypass 12, and a logic unit 13.
[0026] The first data selector 11 can be used to select any one of the multiple input signals for output based on the enable signal. Optionally, the first data selector 11 can be a multiplexer or other circuit devices capable of achieving the above functions, and this application does not impose any limitations on this. Further, in this embodiment, the first data selector 11 may include a first input terminal, a second input terminal, and a first enable terminal.
[0027] The sensor control scan bypass 12 may include at least one memory cell connected in a scan chain. It should be understood that connecting memory cells in a scan chain specifically means cascading memory cells so that the scan input port of each memory cell is connected to the scan output port of the adjacent preceding memory cell, and the scan output port of each memory cell is connected to the scan input port of the adjacent following memory cell. In this embodiment, the sensor control scan bypass 12 can be used to replace the scan chain portion belonging to the sensor control unit 14 to participate in the reception and output of test signals, thereby enabling the sensor control unit 14 to normally acquire and output the chip's operating parameters when the chip is in test mode. Further, in this embodiment, the signal output terminal of the sensor control unit 14 can be connected to the first input terminal of the first data selector 11. One end of the sensor control scan bypass 12 can be connected to the signal receiving terminal of the sensor control unit 14, and the other end can be connected to the second input terminal of the first data selector 11.
[0028] It should be understood that, in this embodiment, the signal receiving end of the sensor control unit can specifically refer to the port of the scan chain portion belonging to the sensor control unit 14 used for receiving test signals, and the signal output end of the sensor control unit can specifically refer to the port of the scan chain portion belonging to the sensor control unit 14 used for outputting test signals.
[0029] It should be understood that, in this embodiment, the number of storage units in the sensor control scan bypass 12 should be equal to the number of storage units inserted into the scan chain in the sensor control unit 14.
[0030] Logic unit 13 can be used to output an enable signal, i.e., a level signal, to control the selection of the data selector. Further, in this embodiment, logic unit 13 can be connected to the first enable terminal of the first data selector 11. Logic unit 13 can be configured to output a first enable signal or a second enable signal to the first enable terminal of the first data selector 11 in a first test mode, so that the first data selector 11 is controlled by the first enable signal to select and output the test signal of the sensor control scan bypass 12, or, controlled by the second enable signal, select and output the sensor signal of the sensor control unit 14. The sensor control unit 14 is not a test object in the first test mode. Therefore, this embodiment can obtain the chip's operating parameters in test mode without affecting chip testing, thereby providing an analytical basis for the cause of chip test failure.
[0031] Figure 2 This is a circuit diagram of the test circuit according to an embodiment of this application. Figure 2 As shown, the test circuit includes a first data selector 21, a sensor control scan bypass 22, and a logic unit 23.
[0032] The first data selector 21 includes a first input terminal I1, a second input terminal I2, and a first enable terminal E1. The sensing control unit 24 includes a signal receiving terminal S. i1 and signal output terminal S o1 Signal receiver S i1 and signal output terminal S o1 These are the ports belonging to the scan chain section of the sensor control unit 24, used for receiving and outputting test signals. The signal output terminal S of the sensor control unit... o1 It is connected to the first input terminal I1 of the first data selector 21. One end of the sensor control scan bypass 22 is connected to the signal receiving terminal S of the sensor control unit 24. i1 One end is connected to the first input terminal I2 of the first data selector 21. The logic unit 23 is connected to the first enable terminal E1 of the first data selector 21.
[0033] It should be understood that the first data selector 21 may also include an output terminal O1, which can be connected to a test signal output terminal. In this embodiment, the test signal output terminal may refer to the signal input port of the scan chain portion belonging to other circuit elements, or it may be the signal recovery port of the test logic circuit; this application does not impose any limitations on this. The test logic circuit can be used to generate and recover test signals, and to test the circuit elements by comparing the changes before and after the two.
[0034] Furthermore, the sensor control scan bypass 22 includes storage units 221 and 222 connected in a scan chain configuration. Storage unit 221 includes an input terminal D1, an output terminal Q1, and a clock signal terminal CLK1. Storage unit 222 includes an input terminal D2, an output terminal Q2, and a clock signal terminal CLK2. The connection of storage units 221 and 222 in a scan chain configuration specifically means that storage units 221 and 222 are connected in series, such that the output terminal Q1 of storage unit 221 is connected to the input terminal D2 of storage unit 222. One end of the sensor control scan bypass 22 is connected to the signal receiving terminal S of the sensor control unit 24. i1 The connection, specifically connecting the other end to the second input terminal I2 of the first data selector 21, can refer to connecting the input terminal of the first storage unit in the sensor control scan bypass 22 (i.e., the input terminal D1 of storage unit 221) to the signal receiving terminal S of the sensor control unit 24. i1 The output terminal of the last bit storage unit in the sensor control scan bypass 22 (that is, the output terminal Q2 of storage unit 222) is connected to the second input terminal I2 of the first data selector 21.
[0035] Furthermore, in order to avoid affecting chip testing, this embodiment can further subdivide the chip testing mode into a first testing mode and a second testing mode based on whether the sensing control unit 24 is the test object.
[0036] In the first test mode, the sensor control unit 24 is not the test object. In this mode, this embodiment can use the sensor control scan bypass 22 to replace the scan chain portion belonging to the sensor control unit 24 to receive and output test signals, thereby enabling the sensor control unit 24 to normally acquire and output the chip's operating parameters in the test mode. Further, the logic unit 23 can output a first enable signal or a second enable signal to the first enable terminal E1 of the first data selector 21, so that the first data selector 21 is controlled by the first enable signal to select the output of the test signal of the sensor control scan bypass 22, or is controlled by the second enable signal to select the output of the sensor signal of the sensor control unit 24.
[0037] It should be understood that in this embodiment, the sensing signal is the chip's operating parameters collected by the sensing control unit 24, which may include at least one or a combination of the following: voltage detection signal, temperature detection signal, and process parameter detection signal.
[0038] In the second test mode, the sensor control unit 24 is the test object. In this mode, this embodiment allows the sensor control unit 24 to participate in the test normally. Furthermore, the logic unit 23 can maintain the output of a second enable signal to the first enable terminal of the first data selector 21 in the second test mode, so that the first data selector 21 is controlled by the second enable signal and selects to output the test signal of the sensor control unit 24. Therefore, this embodiment can normally obtain the chip's operating parameters in test mode without affecting chip testing, thereby providing an analytical basis for the cause of chip test failure.
[0039] Optionally, in order for the sensor control unit 24 to normally acquire and output chip operating parameters in the first test mode and to normally participate in testing in the second test mode, the sensor control unit 24 can be pre-configured in this embodiment. Specifically, in this embodiment, the sensor control unit 24 can be pre-configured to shield the received test signal in the first test mode and to receive and output test signals in the second test mode.
[0040] Alternatively, to enable the sensor control unit 24 to properly acquire and output chip operating parameters in the first test mode and participate in testing normally in the second test mode, this embodiment can also include a switch unit with signal interception functionality. Specifically, the test circuit may further include a first switch unit. This first switch unit can be located between the test signal input terminal and the signal receiving terminal of the sensor control unit. In this embodiment, the first switch unit can be configured to intercept the test signal in the first test mode and allow the test signal to pass through in the second test mode.
[0041] It should be understood that, in this embodiment, the test signal input terminal may specifically refer to the signal output port of the scan chain portion belonging to other circuit elements, or it may be the signal generation port of the test logic circuit; this application does not impose any limitations on this. The test logic circuit can be used to generate and retrieve test signals, and to test the circuit elements by comparing the changes before and after the signals.
[0042] Optionally, in some scenarios, the sensor control unit will acquire chip operating parameters through independent sensor units. To meet test coverage requirements, these independent sensor units will also be inserted into the scan chain. In this scenario, to ensure that the sensor units can provide data support to the sensor control unit normally when the chip is in test mode, the test circuit in this embodiment may also include a second data selector and a sensor scan bypass.
[0043] Figure 3 This is a schematic diagram of another test circuit according to an embodiment of this application. Figure 3 As shown, the test circuit includes a first data selector 31, a sensor control scan bypass 32, a second data selector 33, a sensor scan bypass 34, and a logic unit 35.
[0044] The first data selector 31 and the sensor control scan bypass 32 are the same as the first data selector and the sensor control scan bypass in the above embodiments, and will not be described in detail here.
[0045] The second data selector 33 can be used to select any one of the multiple input signals for output based on the enable signal. Optionally, the second data selector 33 can be a multiplexer or other circuit devices capable of achieving the above functions, and this application does not impose any limitations on this. Further, in this embodiment, the second data selector 33 may include a third input terminal, a fourth input terminal, and a second enable terminal.
[0046] The sensor scan bypass 34 may include at least one memory cell connected in the form of a scan chain. In this embodiment, the sensor scan bypass 34 can be used to replace the scan chain portion belonging to the sensor unit 37 to participate in the reception and output of test signals, thereby enabling the sensor unit 37 to normally provide data support to the sensor control unit 36 when the chip is in test mode. Further, in this embodiment, the signal output terminal of the sensor unit 37 can be connected to the third input terminal of the second data selector 33. One end of the sensor scan bypass 34 can be connected to the signal receiving terminal of the sensor unit 37, and the other end can be connected to the fourth input terminal of the second data selector 33.
[0047] It should be understood that, in this embodiment, the number of storage units in the sensing scan bypass 34 should be equal to the number of storage units in the sensing unit 37 that are inserted into the scan chain.
[0048] Optionally, in this embodiment, in addition to being connected to the first enable terminal of the first data selector 31, the logic unit 35 can also be connected to the second enable terminal of the second data selector 33. Besides implementing the functions mentioned in the above embodiments, the logic unit 35 can also maintain the output of a third enable signal to the second enable terminal of the second data selector 33 in the first test mode, so that the second data selector 33 is controlled by the third enable signal and selects to output the test signal of the sensor scan bypass 34. Furthermore, the logic unit 35 can also maintain the output of a fourth enable signal to the second enable terminal of the second data selector 33 in the second test mode, so that the second data selector 33 is controlled by the fourth enable signal and selects to output the test signal of the sensor unit 37.
[0049] Figure 4 This is a circuit diagram of another test circuit according to an embodiment of this application. Figure 4 As shown, the test circuit includes a first data selector 41, a sensor control scan bypass 42, a second data selector 43, a sensor scan bypass 44, and a logic unit 45.
[0050] The first data selector 41 and the sensor control scan bypass 42 are the same as the first data selector and the sensor control scan bypass in the above embodiment, so they will not be described in detail here.
[0051] The second data selector 43 includes a third input terminal I3, a fourth input terminal I4, and a second enable terminal E2. The sensing unit 47 includes a signal receiving terminal S. i2 and signal output terminal S o2 Signal receiver S i2 and signal output terminal S o2 These are the ports belonging to the scan chain section of sensing unit 47, used for receiving and outputting test signals. The signal output terminal S of the sensing unit... o2 It is connected to the third input terminal I3 of the second data selector 43. One end of the sensing scan bypass 44 is connected to the signal receiving terminal S of the sensing unit 47. i2 One end is connected to the first enable terminal E1 of the first data selector 41, and the other end is connected to the fourth input terminal I4 of the second data selector 43. Logic unit 45 is connected to the second enable terminal E2 of the second data selector 43, in addition to being connected to the first enable terminal E1 of the first data selector 41. It should be understood that the second data selector 43 may also include an output terminal O2, which can be connected to a test signal output terminal.
[0052] Furthermore, the sensor scan bypass 44 includes storage units 441 and 442 connected in a scan chain configuration. Storage unit 441 includes an input terminal D3, an output terminal Q3, and a clock signal terminal CLK3. Storage unit 442 includes an input terminal D4, an output terminal Q4, and a clock signal terminal CLK4. The connection of storage units 441 and 442 in a scan chain configuration specifically means that storage units 441 and 442 are connected in series, such that the output terminal Q3 of storage unit 441 is connected to the input terminal D4 of storage unit 442. One end of the sensor scan bypass 44 is connected to the signal receiving terminal S of the sensing unit 47. i2 The connection, specifically connecting the other end to the fourth input terminal I4 of the second data selector 43, can refer to connecting the input terminal of the first storage unit in the sensing scan bypass 44 (i.e., the input terminal D3 of storage unit 441) to the signal receiving terminal S of the sensing unit 47. i2 The output terminal of the last bit storage unit in the sensor scan bypass 44 (that is, the output terminal Q4 of storage unit 442) is connected to the fourth input terminal I4 of the second data selector 43.
[0053] In the first test mode, this embodiment can use the sensor control scan bypass 42 to replace the scan chain part belonging to the sensor control unit 46 to receive and output test signals, and use the sensor scan bypass 44 to replace the scan chain part belonging to the sensor unit 47 to receive and output test signals, so that the sensor unit 47 can normally provide data support to the sensor control unit 46, thereby enabling the sensor control unit 46 to normally collect and output the chip's operating parameters in the test mode with the support of the sensor unit 47. Furthermore, the logic unit 45 can output a first enable signal or a second enable signal to the first enable terminal E1 of the first data selector 41, so that the first data selector 41 is controlled by the first enable signal to select the output test signal of the sensor control scan bypass 42, or is controlled by the second enable signal to select the output sensor signal of the sensor control unit 46, and the output of a third enable signal to the second enable terminal E2 of the second data selector 43 remains unchanged, so that the second data selector 43 is controlled by the third enable signal to select the output test signal of the sensor scan bypass 44.
[0054] In the second test mode, this embodiment allows the sensing control unit 46 and the sensing unit 47 to participate in the test normally. Further, the logic unit 45 can maintain the output of a second enable signal to the first enable terminal E1 of the first data selector 41, so that the first data selector 41 is controlled by the second enable signal and selects to output the test signal of the sensing control unit 46; and maintain the output of a fourth enable signal to the second enable terminal E2 of the second data selector 43, so that the second data selector 43 is controlled by the fourth enable signal and selects to output the test signal of the sensing unit 47.
[0055] Optionally, in order for the sensing unit 47 to provide data support to the sensing control unit 46 normally in the first test mode and to participate in the test normally in the second test mode, the sensing unit can be pre-configured in this embodiment. Specifically, in this embodiment, the sensing unit 47 can be pre-configured to shield the received test signal in the first test mode and to receive and output the test signal in the second test mode.
[0056] Alternatively, to enable the sensing unit 47 to provide data support to the sensing control unit 46 normally in the first test mode and to participate in the test normally in the second test mode, this embodiment can also provide a switch unit with signal interception function. Specifically, the test circuit can also include a second switch unit. This second switch unit can be set at the test signal input terminal and the signal receiving terminal S of the sensing unit 47. i2 In this embodiment, the second switching unit can be configured to intercept the test signal in the first test mode and allow the test signal to pass in the second test mode.
[0057] Optionally, in this embodiment, the logic unit 45 may employ an OR gate structure. The logic unit 45 may include an input terminal In1, an input terminal In2, and an output terminal O. The connection of the logic unit 45 to the first enable terminal E1 of the first data selector 41 and the second enable terminal E2 of the second data selector 43 specifically means that the input terminal In1 of the logic unit 45 is connected to the first enable terminal E1 of the first data selector 41, and the output terminal O of the logic unit 45 is connected to the second enable terminal E2 of the second data selector 43.
[0058] It should be understood that in this embodiment, the selection control of the first data selector 41 and the second data selector 43 can be achieved by inputting corresponding level signals to the input terminals In1 and In2 of the logic unit 45.
[0059] Specifically, in the first test mode, this embodiment can maintain a high-level signal input to input terminal In2 and simultaneously input either a high-level signal or a low-level signal to input terminal In1. Therefore, based on the hardware characteristics of the OR gate structure, this embodiment can ensure that the logic unit 45 maintains a third enable signal (i.e., a high-level signal) output to the second enable terminal E2 of the second data selector 43, so that the second data selector 43 is controlled by the third enable signal to select and output the test signal of the sensor scan bypass 44, and outputs a first enable signal (i.e., a high-level signal) or a second enable signal (i.e., a low-level signal) to the first enable terminal E1 of the first data selector 41, so that the first data selector 41 is controlled by the first enable signal to select and output the test signal of the sensor control scan bypass 42, or, controlled by the second enable signal, select and output the sensor signal of the sensor control unit 46.
[0060] In the second test mode, this embodiment can maintain the low-level signals input to input terminals In1 and In2 unchanged. Therefore, based on the hardware characteristics of the OR gate structure, this embodiment can ensure that the logic unit 45 maintains the output of a second enable signal (i.e., a low-level signal) to the first enable terminal E1 of the first data selector 41, so that the first data selector 41 is controlled by the second enable signal to select and output the test signal of the sensing control unit 46; and maintains the output of a fourth enable signal (i.e., a low-level signal) to the second enable terminal E2 of the second data selector 43, so that the second data selector 43 is controlled by the fourth enable signal to select and output the test signal of the sensing unit 47.
[0061] It should be understood that in this embodiment, by adjusting the level signal of the input terminal In2 of the input logic unit 45, the current test mode can be set. Specifically, when it is necessary to be in the first test mode (in the first test mode, the sensor control unit and the sensor unit are not the test objects, and it is necessary to ensure that the sensor control unit and the sensor unit can normally acquire and output chip parameters), this embodiment can input a high-level signal to the input terminal In2 of the logic unit 45. When it is necessary to be in the second test mode (in the second test mode, the sensor control unit and the sensor unit are the test objects, and it is necessary to ensure that the sensor control unit and the sensor unit can normally participate in the test), this embodiment can input a low-level signal to the input terminal In2 of the logic unit 45. Furthermore, after entering the first test mode by adjusting the level signal of the input terminal In2 of the input logic unit 45, this embodiment can also adjust the level signal of the input terminal In1 of the input logic unit 45 to acquire the test signal of the sensor control scan bypass 42 or the sensor signal of the sensor control unit 46. Specifically, when it is necessary to acquire the test signal of the sensor control scan bypass 42, this embodiment can input a high-level signal to the input terminal In1 of the logic unit 45. When it is necessary to acquire the sensing signal of the sensor control unit 46, this embodiment can input a low-level signal to the input terminal In1 of the logic unit 45.
[0062] Optionally, to ensure the normal operation of the sensor control scan bypass and the sensor scan bypass, this embodiment can provide clock signals independent of the sensor control unit and the sensor unit. Furthermore, to ensure the normal operation of the sensor control unit and the sensor unit in chip test mode, this embodiment can also provide independent signal support for the relevant ports of the sensor control unit and the sensor unit (e.g., reset ports or other test-related interfaces), and this application does not impose any limitations on this.
[0063] The test circuit of this application includes a first data selector, a sensor control scan bypass, and a logic unit. The first data selector includes a first input terminal, a second input terminal, and a first enable terminal. The first input terminal is connected to the signal output terminal of the sensor control unit. The sensor control scan bypass includes a storage unit connected in a scan chain, one end of which is connected to the signal receiving terminal of the sensor control unit, and the other end is connected to the second input terminal. The logic unit is connected to the first enable terminal and is configured to output a first enable signal or a second enable signal to the first enable terminal in a first test mode. This allows the first data selector to be controlled by the first enable signal to select and output the test signal of the sensor control scan bypass, or controlled by the second enable signal to select and output the sensor signal of the sensor control unit. Therefore, this embodiment can obtain the chip's operating parameters in test mode without affecting chip testing, thereby providing an analytical basis for the cause of chip test failure.
[0064] Furthermore, another embodiment of this application also provides a chip. Specifically, this chip may be a chip integrating the test circuit described in the above embodiments. It should be understood that, through the test circuit, this embodiment can normally obtain the chip's operating parameters in test mode without affecting chip testing, thereby providing an analytical basis for the cause of chip test failure.
[0065] Furthermore, another embodiment of this application also provides an electronic device. Specifically, this electronic device may be a device that utilizes the chip described in the above embodiments. It should be understood that, through the test circuit, this embodiment can normally obtain the chip's operating parameters in test mode without affecting the testing of the chip in the device, thereby providing an analytical basis for the cause of chip test failure.
[0066] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.
Claims
1. A test circuit, characterized in that, The circuit includes: The first data selector includes a first input terminal, a second input terminal, and a first enable terminal, wherein the first input terminal is connected to the signal output terminal of the sensing control unit; The sensor control scan bypass includes storage units connected in the form of a scan chain. One end of the sensor control scan bypass is connected to the signal receiving end of the sensor control unit, and the other end is connected to the second input end. A logic unit, connected to the first enable terminal, is configured to output a first enable signal or a second enable signal to the first enable terminal in a first test mode, such that the first data selector is controlled by the first enable signal to select and output the test signal of the sensing control scan bypass, or is controlled by the second enable signal to select and output the sensing signal of the sensing control unit, wherein the sensing control unit is a non-test object in the first test mode.
2. The circuit according to claim 1, characterized in that, The logic unit is further configured to maintain the output of a second enable signal to the first enable terminal in the second test mode, so that the first data selector is controlled by the second enable signal and selects to output the test signal of the sensing control unit, which is the test object in the second test mode.
3. The circuit according to claim 2, characterized in that, The sensing control unit is configured to shield the received test signal in the first test mode, and to receive and output the test signal in the second test mode.
4. The circuit according to claim 2, characterized in that, The test circuit also includes: A first switching unit is disposed between the test signal input terminal and the signal receiving terminal of the sensing control unit. The first switching unit is configured to intercept the test signal in the first test mode and allow the test signal to pass in the second test mode.
5. The circuit according to claim 1, characterized in that, The circuit also includes: The second data selector includes a third input terminal, a fourth input terminal, and a second enable terminal, wherein the third input terminal is connected to the signal output terminal of the sensing unit. The sensor scan bypass includes storage units connected in the form of a scan chain. One end of the sensor scan bypass is connected to the signal receiving end of the sensing unit, and the other end is connected to the fourth input end.
6. The circuit according to claim 5, characterized in that, The logic unit is also connected to the second enable terminal, and the logic unit is further configured to maintain the output of a third enable signal to the second enable terminal in the first test mode, so that the second data selector is controlled by the third enable signal and selects to output the test signal of the sensing scan bypass, and the sensing unit is a non-test object in the first test mode.
7. The circuit according to claim 6, characterized in that, The logic unit is further configured to maintain the output of a fourth enable signal to the second enable terminal in the second test mode, so that the second data selector is controlled by the fourth enable signal to select and output the test signal of the sensing unit, wherein the sensing unit is the test object in the second test mode.
8. The circuit according to claim 7, characterized in that, The sensing unit is configured to shield the received test signal in the first test mode, and to receive and output the test signal in the second test mode.
9. The circuit according to claim 7, characterized in that, The test circuit also includes: A second switching unit is disposed between the test signal input terminal and the signal receiving terminal of the sensing unit. The second switching unit is configured to intercept the test signal in the first test mode and allow the test signal to pass through in the second test mode.
10. The circuit according to claim 1, characterized in that, The number of storage units in the sensor control scan bypass is equal to the number of storage units inserted into the scan chain in the sensor control unit.
11. The circuit according to claim 5, characterized in that, The number of storage units in the sensor scan bypass is equal to the number of storage units inserted into the scan chain in the sensor unit.
12. The circuit according to claim 1, characterized in that, The sensing signal includes at least one or a combination of the following: voltage detection signal, temperature detection signal, and process parameter detection signal.
13. A chip, characterized in that, The chip includes: The test circuit as described in any one of claims 1-12.
14. An electronic device, characterized in that, The electronic device includes the chip as described in claim 13.