Delay power-off and power-on impact current suppression circuit
By using a PMOS and NPN transistor circuit structure in the automotive motor controller, the PMOS transistor is delayed to control the power-on surge current, and the activation detection signal is fed back through the NPN transistor. This solves the controller failure problem caused by the power failure of the activation signal, and achieves power-on surge current suppression and delayed power-off, ensuring stable operation of the controller.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- SHENZHEN LIDE ELECTRIC CONTROL TECH
- Filing Date
- 2025-05-08
- Publication Date
- 2026-05-19
AI Technical Summary
Existing automotive motor controllers are prone to internal circuit failures when the activation signal is suddenly lost, such as PI regulation malfunction and module damage.
The circuit structure consists of PMOS transistors, NPN transistors, and NPN transistors. The turn-on of the PMOS transistor is delayed by capacitor C60 to control the surge current at the moment of power-on. The activation detection signal is fed back by NPN transistor Q14 to ensure that the controller is stably powered down when the DSP enable signal is present.
It effectively suppresses the inrush current during power-on, preventing damage to the controller. At the same time, no current flows during standby, achieving delayed power-off and ensuring normal operation of the controller.
Smart Images
Figure CN224264690U_ABST
Abstract
Description
Technical Field
[0001] This utility model relates to controller protection circuits, and more particularly to a delayed power-off and power-on inrush current suppression circuit. Background Technology
[0002] Existing automotive motor controllers require an activation signal to enter normal operation. If the activation signal suddenly loses power during operation, the internal circuitry of the controller will lose power in a short period of time. This short period of time, lasting only tens of milliseconds, can cause unpredictable malfunctions. For example, changes in the sampling level can easily lead to PI regulation going out of control, which in turn can cause sudden damage to internal components and even cause the module to explode. Utility Model Content
[0003] The technical problem to be solved by this utility model is to provide a circuit that has power-on inrush current suppression function, no standby current, and can delay power-off, in order to address the shortcomings of the existing technology.
[0004] To solve the above-mentioned technical problems, the present invention adopts the following technical solution.
[0005] A delayed power-off and power-on inrush current suppression circuit includes a PMOS transistor Q15, an NPN transistor Q10, an NPN transistor Q13, and an NPN transistor Q14. The source of the PMOS transistor Q15 is connected to the power supply terminal Vbat+, and the drain of the PMOS transistor Q15 is connected to the load. A capacitor C60 is connected between the source and gate of the PMOS transistor Q15. The gate voltage of the PMOS transistor Q15 is applied to the collectors of the NPN transistors Q10 and Q13. The emitter of NPN transistor Q10 is grounded, and the base of NPN transistor Q10 is used to receive the DSP enable signal issued by the controller. The emitter of NPN transistor Q13 is grounded, and the collector of NPN transistor Q14 is connected to a high potential of +3.3V through resistor R218. The collector of NPN transistor Q14 is used to transmit an activation detection signal to the controller. The emitter of NPN transistor Q14 is grounded, and the bases of NPN transistors Q13 and Q14 are used to receive external activation signals.
[0006] Preferably, it includes a Zener diode D46, the cathode and anode of which are connected to the source and gate of the PMOS transistor Q15, respectively.
[0007] Preferably, the device includes resistors R216 and R217 and diode D45. Resistor R216 is connected between the source and gate of PMOS transistor Q15, resistor R217 is connected between the gate of PMOS transistor Q15 and the anode of diode D45, and the cathode of diode D45 is connected to the collector of NPN transistor Q10 and the collector of NPN transistor Q13.
[0008] Preferably, a resistor R214 and a capacitor C58 are connected in parallel between the base and emitter of the NPN transistor Q10.
[0009] Preferably, a capacitor C59 is connected between the base and emitter of the NPN transistor Q13.
[0010] Preferably, the base of the NPN transistor Q13 is connected to resistors R200 and R162 connected in series.
[0011] Preferably, the device includes a diode D44 and a resistor R177. The connection point of the resistors R200 and R162 is connected to the cathode of the diode D44, the anode of the diode D44 is grounded, and the resistor R177 is connected in parallel with the diode D44.
[0012] Preferably, the base of the NPN transistor Q14 is grounded through capacitor C61, and the collector of the NPN transistor Q14 is grounded through capacitor C62.
[0013] In the delayed power-off and power-on inrush current suppression circuit disclosed in this utility model, when an external activation signal is input, it drives NPN transistors Q13 and Q14 to conduct, and the gate of PMOS transistor Q15 is pulled low. Because a capacitor C60 is connected between the source and gate of PMOS transistor Q15, it is necessary to wait for the capacitor C60 to finish charging before PMOS transistor Q15 slowly turns on, so that the inrush current at the moment of power-on is effectively controlled. At the same time, NPN transistor Q14 conducts and feeds back an activation detection signal to the controller to characterize the input state of the external activation signal. The device sends a DSP enable signal to the base of the NPN transistor Q10. After the NPN transistor Q10 is turned on, it also pulls the gate of the PMOS transistor Q15 low. In the subsequent timing sequence, even if the external activation signal suddenly disappears or goes low, the controller can still work normally due to the presence of the DSP enable signal. This provides sufficient time for the controller to shut down various functions, ensuring that the controller can complete the power-down timing normally and stably. Compared with the prior art, this invention has a power-on inrush current suppression function, and no current flows during standby. In addition, this invention also achieves delayed power-off, which better meets the application requirements. Attached Figure Description
[0014] Figure 1 This is the circuit schematic diagram of this utility model;
[0015] Figure 2 The waveform of the surge current at the moment of power-on in a traditional circuit;
[0016] Figure 3 This is a waveform diagram of the surge current at the moment of power-on of the circuit of this utility model. Detailed Implementation
[0017] The present invention will now be described in more detail with reference to the accompanying drawings and embodiments.
[0018] This utility model discloses a circuit for delayed power-off and power-on inrush current suppression. Please refer to [link / reference]. Figure 1 It includes a PMOS transistor Q15, an NPN transistor Q10, an NPN transistor Q13, and an NPN transistor Q14. The source of the PMOS transistor Q15 is connected to the power supply terminal Vbat+, and the drain of the PMOS transistor Q15 is connected to the load. A capacitor C60 is connected between the source and gate of the PMOS transistor Q15. The gate voltage of the PMOS transistor Q15 is applied to the collectors of the NPN transistors Q10 and Q13. The emitter of the NPN transistor Q10 is grounded, and the base of the NPN transistor Q10 is used to receive the DSP enable signal from the controller. The emitter of the NPN transistor Q13 is grounded. The collector of the NPN transistor Q14 is connected to a high potential of +3.3V through a resistor R218. The collector of the NPN transistor Q14 is used to transmit an activation detection signal to the controller. The emitter of the NPN transistor Q14 is grounded, and the bases of the NPN transistors Q13 and Q14 are used to receive external activation signals.
[0019] In the above circuit, when an external activation signal is input, it drives NPN transistors Q13 and Q14 to conduct, pulling the gate of PMOS transistor Q15 low. Because a capacitor C60 is connected between the source and gate of PMOS transistor Q15, it is necessary to wait for capacitor C60 to finish charging before slowly turning on PMOS transistor Q15, effectively controlling the surge current at power-on. Simultaneously, NPN transistor Q14 feeds back an activation detection signal to the controller to characterize the input state of the external activation signal. At the same time, the controller sends a signal to NPN transistor Q13. The base of 0 emits a DSP enable signal. After the NPN transistor Q10 is turned on, it also pulls the gate of the PMOS transistor Q15 low. In the subsequent timing sequence, even if the external activation signal suddenly disappears or goes low, the controller can still work normally due to the presence of the DSP enable signal. This provides sufficient time for the controller to shut down various functions, ensuring that the controller can complete the power-down timing normally and stably. Compared with the prior art, this utility model has a power-on inrush current suppression function, and no current flows during standby. In addition, this utility model also achieves delayed power-off, which better meets the application requirements.
[0020] To ensure that the PMOS transistor Q15 starts up more accurately, this embodiment includes a Zener diode D46, the cathode and anode of which are connected to the source and gate of the PMOS transistor Q15, respectively.
[0021] Further, the device includes resistors R216 and R217, and diode D45. Resistor R216 is connected between the source and gate of the PMOS transistor Q15, resistor R217 is connected between the gate of the PMOS transistor Q15 and the anode of diode D45, and the cathode of diode D45 is connected to the collectors of NPN transistors Q10 and Q13. Diode D45 prevents reverse current flow. Resistors R216 and R217 are connected in series and act as a voltage divider, creating a voltage drop between the source and gate of the PMOS transistor Q15.
[0022] To filter out the ripple at the base of the NPN transistor Q10, in this embodiment, a resistor R214 and a capacitor C58 are connected in parallel between the base and emitter of the NPN transistor Q10.
[0023] In this embodiment, a capacitor C59 is connected between the base and emitter of the NPN transistor Q13. Furthermore, a resistor R200 and a resistor R162 are connected in series at the base of the NPN transistor Q13. The function of resistors R200 and R162 is to limit current.
[0024] Based on this, this embodiment includes a diode D44 and a resistor R177. The connection point of the resistors R200 and R162 is connected to the cathode of the diode D44, the anode of the diode D44 is grounded, and the resistor R177 is connected in parallel with the diode D44. The function of the diode D44 and the resistor R177 is to suppress and absorb the reverse electromotive force.
[0025] To improve the stability of the detection signal, in this embodiment, the base of the NPN transistor Q14 is grounded through capacitor C61, and the collector of the NPN transistor Q14 is grounded through capacitor C62.
[0026] Please see Figure 1 In this embodiment, Vbat+ and Vbat- are externally input power signals that are constantly connected to the two ends of the low-voltage battery. When the activation signal is high, the external enable controller starts to work, and when the activation signal is low, it is in a standby static state.
[0027] In practical applications, controllers contain many capacitors, typically with capacitance values exceeding 100uF. When the activation signal is high, without any intervention, the power supply charges these capacitors, resulting in instantaneous surge currents often reaching the hundreds of amps level. Figure 2 As shown. In this embodiment, a 2.2uF capacitor C60 is added to the gate terminal of the PMOS transistor Q15, causing Q15 to turn on slowly, effectively controlling the inrush current to approximately 10A. Figure 3 As shown.
[0028] In this embodiment, the PMOS transistor Q15 is applied to the front end of the power supply. When the activation signal is low, there is no static current at the back end, which meets the requirement of less than 1mA of static power consumption currently required by the vehicle manufacturing industry.
[0029] When the circuit is working normally, if the activation signal suddenly loses power, the internal circuit of the controller will be running during the power failure, resulting in a module explosion. To address this, this embodiment adds a DSP enable power supply circuit and an activation signal detection circuit. The specific timing includes: when the activation signal is high, the controller starts working, the controller DSP enable power supply signal is simultaneously high, the controller detects the level of the external activation signal, when the level of the external activation signal goes low, the DSP enable signal is high, so the controller power supply is still normal, the controller DSP performs the final work in time, shuts down all functions, and sets the DSP enable signal to the bottom until the entire controller is powered down.
[0030] The above description is only a preferred embodiment of the present utility model and is not intended to limit the present utility model. All modifications, equivalent substitutions or improvements made within the technical scope of the present utility model should be included within the scope of protection of the present utility model.
Claims
1. A circuit for delayed power-off and power-on inrush current suppression, characterized in that, The system includes a PMOS transistor Q15, an NPN transistor Q10, an NPN transistor Q13, and an NPN transistor Q14. The source of the PMOS transistor Q15 is connected to the power supply terminal Vbat+, and the drain of the PMOS transistor Q15 is connected to the load. A capacitor C60 is connected between the source and gate of the PMOS transistor Q15. The gate voltage of the PMOS transistor Q15 is applied to the collectors of the NPN transistors Q10 and Q13. The emitter of the NPN transistor Q10 is grounded, and the base of the NPN transistor Q10 is used to receive the DSP enable signal from the controller. The emitter of the NPN transistor Q13 is grounded. The collector of the NPN transistor Q14 is connected to a high potential of +3.3V through a resistor R218. The collector of the NPN transistor Q14 is used to transmit an activation detection signal to the controller. The emitter of the NPN transistor Q14 is grounded, and the bases of the NPN transistors Q13 and Q14 are used to receive external activation signals.
2. The delayed power-off and power-on inrush current suppression circuit as described in claim 1, characterized in that, It includes a Zener diode D46, the cathode and anode of which are connected to the source and gate of the PMOS transistor Q15, respectively.
3. The delayed power-off and power-on inrush current suppression circuit as described in claim 1, characterized in that, It includes resistor R216, resistor R217 and diode D45. Resistor R216 is connected between the source and gate of PMOS transistor Q15, resistor R217 is connected between the gate of PMOS transistor Q15 and the anode of diode D45, and the cathode of diode D45 is connected to the collector of NPN transistor Q10 and the collector of NPN transistor Q13.
4. The delayed power-off and power-on inrush current suppression circuit as described in claim 1, characterized in that, A resistor R214 and a capacitor C58 are connected in parallel between the base and emitter of the NPN transistor Q10.
5. The delayed power-off and power-on inrush current suppression circuit as described in claim 1, characterized in that, A capacitor C59 is connected between the base and emitter of the NPN transistor Q13.
6. The delayed power-off and power-on inrush current suppression circuit as described in claim 1, characterized in that, The base of the NPN transistor Q13 is connected to resistors R200 and R162 connected in series.
7. The delayed power-off and power-on inrush current suppression circuit as described in claim 6, characterized in that, It includes a diode D44 and a resistor R177. The connection point of the resistors R200 and R162 is connected to the cathode of the diode D44. The anode of the diode D44 is grounded. The resistor R177 is connected in parallel with the diode D44.
8. The delayed power-off and power-on inrush current suppression circuit as described in claim 1, characterized in that, The base of the NPN transistor Q14 is grounded through capacitor C61, and the collector of the NPN transistor Q14 is grounded through capacitor C62.