Numerical control attenuator and phased array system

Abstract

The utility model relates to the field of integrated circuits, and provides a numerical control attenuator and a phased array system.The numerical control attenuator comprises a transmission trunk and an attenuation branch, the transmission trunk is connected between a radio frequency input end and a radio frequency output end in series, and one end of the attenuation branch is connected with the transmission trunk; the at least one attenuation branch comprises a first resistor, a first transistor and an adjustable capacitor, and the first resistor and the first transistor are connected in series; the first resistor is connected with the adjustable capacitor in parallel, the control end of the adjustable capacitor receives the bias voltage, the capacitance value of the adjustable capacitor is regulated and controlled by the bias voltage, and the numerical control attenuator can keep low parasitic phase modulation at high and low temperatures.

Description

Technical Field

[0001] This disclosure relates to the field of wireless communication, and more particularly to a digitally controlled attenuator and a phased array system. Background Technology

[0002] Millimeter-wave phased array technology is an antenna array technology where the phase of each antenna element is controllable. It alters the direction and intensity of the array's equivalent beam by changing the amplitude and phase information of the radiated or received electrical signals by each antenna in the array. Millimeter-wave phased array technology can be used in military applications, such as designing phased array radars. Furthermore, in 5G mobile communications, millimeter-wave phased array technology is a key implementation method for beamforming in massive MIMO (Multiple-Input Multiple-Output) systems. In a phased array system, each array element has independent transmit / receive components to provide amplitude and phase control functions for the signal. Typically, the RF front-end of a phased array includes low-noise amplifiers, power amplifiers, phase shifters, and attenuators. Attenuators, as the amplitude control module in a phased array system, can be classified into active attenuators and passive attenuators based on their implementation method.

[0003] Taking a passive digitally controlled attenuator as an example, it is an attenuator implemented based on passive components (such as resistors, diodes, or transistors), and its attenuation value can be controlled by digital signals. Unlike active attenuators, passive digitally controlled attenuators do not require an external power supply to operate, thus featuring low power consumption, high linearity, and wide bandwidth. However, in practical applications, due to significant variations in ambient temperature, existing digitally controlled attenuators exhibit substantial parasitic phase modulation changes at high and low temperatures, leading to inaccurate attenuation control. Utility Model Content

[0004] To address the issue of significant parasitic phase modulation variations in digitally controlled attenuators, this disclosure provides a digitally controlled attenuator and a phased array system that can maintain low parasitic phase modulation at different temperatures.

[0005] The technical solution disclosed herein is implemented as follows:

[0006] In a first aspect, embodiments of this disclosure provide a digitally controlled attenuator, the digitally controlled attenuator including a transmission trunk and an attenuation branch, the transmission trunk being connected in series between an RF input terminal and an RF output terminal, and one end of the attenuation branch being connected to the transmission trunk; at least one of the attenuation branches includes a first resistor, a first transistor, and an adjustable capacitor, the first resistor and the first transistor being connected in series; the first resistor and the adjustable capacitor being connected in parallel, the control terminal of the adjustable capacitor receiving a bias voltage, and the capacitance value of the adjustable capacitor being adjusted by the bias voltage.

[0007] In this way, by providing different bias voltages at different ambient temperatures, the capacitance value of the adjustable capacitor can be changed with the ambient temperature, compensating for the parasitic phase shift at different temperatures, so that the digitally controlled attenuator can maintain a small parasitic phase shift at different ambient temperatures.

[0008] In some embodiments, the adjustable capacitor includes a third transistor and a fourth transistor, the input and output terminals of the third transistor and the input and output terminals of the fourth transistor are connected together to form a connection point, and the connection point receives the bias voltage.

[0009] In this way, the adjustable capacitor can be implemented using a transistor with a control terminal, an input terminal, and an output terminal. Within an appropriate bias range, the capacitance value changes linearly with the bias voltage, resulting in high capacitance density and saving circuit area.

[0010] In some embodiments, the adjustable capacitor includes a first diode and a second diode, wherein the anodes of the first diode and the second diode both receive the bias voltage.

[0011] In this way, the adjustable capacitor can be implemented using a diode, resulting in a fast adjustment response; small size, light weight, small circuit area, low cost; and low power consumption, consuming almost no current.

[0012] In some embodiments, the numerically controlled attenuator further includes a control circuit connected to the control terminal of the adjustable capacitor, the control circuit being used to output the bias voltage with a positive temperature coefficient.

[0013] In this way, the bias voltage increases with increasing temperature, and the capacitance of the adjustable capacitor increases with increasing temperature, thereby achieving drift compensation for parasitic phase modulation at different temperatures.

[0014] In some embodiments, the control circuit includes: a temperature reference voltage source configured to output an initial voltage that is positively correlated with absolute temperature; a first adjustment circuit connected to the temperature reference voltage source configured to receive the initial voltage and output an intermediate voltage, wherein the intermediate voltage changes linearly with the initial voltage and the slope of the change is greater than 1; and a second adjustment circuit cascaded with the first adjustment circuit configured to receive the intermediate voltage and output a bias voltage, wherein the bias voltage changes linearly with the intermediate voltage and the slope of the change is greater than 1.

[0015] In this way, after the initial voltage is generated, the required bias voltage is generated after passing through two stages of adjustment circuit. By designing the device parameters in the adjustment circuit, the relationship between the bias voltage and temperature is adjusted to achieve compensation for parasitic phase shift at different temperatures.

[0016] In some embodiments, the control circuit includes a temperature reference voltage source, a temperature sensor, and a digital-to-analog converter connected in sequence; wherein the temperature reference voltage source outputs an initial voltage that is positively correlated with the absolute temperature; the temperature sensor converts the initial voltage into a temperature code, and the digital-to-analog converter converts the temperature code into the bias voltage.

[0017] In this way, the conversion between digital and analog signals is achieved through a digital-to-analog converter, thereby providing a bias voltage that varies linearly with temperature, and controlling the capacitance of the adjustable capacitor to the desired value at different temperatures.

[0018] Secondly, embodiments of this disclosure provide a phased array system, which includes a digitally controlled attenuator as described in the first aspect.

[0019] In this phased array system, the resistor of the attenuation branch of the digitally controlled attenuator is connected in parallel with an adjustable capacitor. The capacitance value of the adjustable capacitor is different at different temperatures to achieve parasitic phase modulation compensation at different temperatures, so that the digitally controlled attenuator has small parasitic phase modulation at different temperatures. Attached Figure Description

[0020] Figure 1 This is a schematic diagram of the structure of a first type of numerically controlled attenuator provided in an embodiment of this disclosure;

[0021] Figure 2 A performance schematic diagram of the first type of numerically controlled attenuator provided in the embodiments of this disclosure;

[0022] Figure 3 This is a schematic diagram of the structure of a second type of numerically controlled attenuator provided in an embodiment of this disclosure;

[0023] Figure 4 This is a schematic diagram illustrating the structure and performance of a first type of adjustable capacitor provided in an embodiment of this disclosure;

[0024] Figure 5 This is a schematic diagram illustrating the structure and performance of a second type of adjustable capacitor provided in an embodiment of this disclosure;

[0025] Figure 6 A detailed schematic diagram of the second type of numerically controlled attenuator (π-type single-ended structure) provided in the embodiments of this disclosure;

[0026] Figure 7 A detailed schematic diagram of the third type of digitally controlled attenuator (T-type single-ended structure) provided in this embodiment of the present disclosure;

[0027] Figure 8 A detailed schematic diagram of the fourth type of numerically controlled attenuator (bridge T-type single-ended structure) provided in this embodiment of the present disclosure;

[0028] Figure 9A detailed schematic diagram of the fifth type of numerically controlled attenuator (the first type of π-type double-ended structure) provided in the embodiments of this disclosure;

[0029] Figure 10 A detailed schematic diagram of the sixth type of numerically controlled attenuator (first type of T-shaped double-ended structure) provided in the embodiments of this disclosure;

[0030] Figure 11 A detailed schematic diagram of the seventh type of numerically controlled attenuator (the first type of bridge T-type double-ended structure) provided in the embodiments of this disclosure;

[0031] Figure 12 A detailed schematic diagram of the eighth type of numerically controlled attenuator (second type of π-type double-ended structure) provided in the embodiments of this disclosure;

[0032] Figure 13 A detailed schematic diagram of the ninth type of digitally controlled attenuator (second type of T-shaped double-ended structure) provided in the embodiments of this disclosure;

[0033] Figure 14 A detailed schematic diagram of the tenth type of numerically controlled attenuator (second type of bridge T-type double-ended structure) provided in the embodiments of this disclosure;

[0034] Figure 15 This is a schematic diagram of the structure of a first control circuit provided in an embodiment of the present disclosure;

[0035] Figure 16 This is a schematic diagram illustrating the change of initial voltage with temperature provided in an embodiment of the present disclosure;

[0036] Figure 17 Partial circuit diagram of the first type of control circuit provided in the embodiments of this disclosure Figure 1 ;

[0037] Figure 18 Partial circuit diagram of the first type of control circuit provided in the embodiments of this disclosure Figure 2 ;

[0038] Figure 19 A schematic diagram illustrating the variation of initial voltage, intermediate voltage, and bias voltage with temperature for embodiments of this disclosure;

[0039] Figure 20 This is a schematic diagram of the structure of a second control circuit provided in an embodiment of this disclosure;

[0040] Figure 21 This is a schematic diagram of the simulation results of the second type of numerically controlled attenuator provided in the embodiments of this disclosure;

[0041] Figure 22 This is a schematic diagram of the structure of a phased array system provided in an embodiment of the present disclosure. Detailed Implementation

[0042] The technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. It is understood that the specific embodiments described herein are merely for explaining the relevant applications and not for limiting the applications. It should also be noted that, for ease of description, only the parts related to the relevant applications are shown in the accompanying drawings. Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used herein is for the purpose of describing embodiments of this disclosure only and is not intended to limit this disclosure. In the following description, references to "some embodiments" describe a subset of all possible embodiments; however, it is understood that "some embodiments" can be the same subset or different subsets of all possible embodiments and can be combined with each other without conflict. It should be noted that the terms "first, second, third" involved in the embodiments of this disclosure are only used to distinguish similar objects and do not represent a specific ordering of objects. It is understood that "first, second, third" can be interchanged in a specific order or sequence where permitted, so that the embodiments of this disclosure described herein can be implemented in an order other than that illustrated or described.

[0043] The embodiments of this disclosure will now be described in detail with reference to the accompanying drawings.

[0044] In one embodiment of this disclosure, see Figure 1 This illustration shows a structural schematic diagram of a numerically controlled attenuator 10 provided in an embodiment of this disclosure. Figure 1 As shown, the numerically controlled attenuator 10 adopts a π-type structure, including a transmission trunk 11 and attenuation branches 12. The transmission trunk 11 includes a transistor M1, which is connected in series between the RF input terminal Rfin and the RF output terminal Rfout. The transistor M1 is connected in parallel with a resistor RL. There are two attenuation branches 12. Each attenuation branch 12 includes a resistor Rp and a transistor M2 connected in series. The end of the transistor M2 away from the resistor Rp is connected to standard ground. The resistor Rp in the first attenuation branch 12 is connected to the input terminal of the transistor M1, and the resistor Rp in the second attenuation branch 12 is connected to the output terminal of the transistor M1. Each attenuation branch 12 also includes a fixed capacitor Ccomp, which is connected in parallel with the resistor Rp.

[0045] Thus, in this embodiment, in order to reduce parasitic phase modulation at high frequencies of the attenuator, a fixed capacitor Ccomp is connected in parallel with the resistor of the attenuation branch of the attenuator. Figure 2This diagram illustrates the performance of an attenuator with a fixed capacitance. For example, in (a), the horizontal axis (X-axis) represents the signal frequency, and the vertical axis (Y-axis) represents the signal amplitude from port 1 to port 2 (S21). One curve (solid line) represents the attenuator operating in the reference state (Ref_w / Ccomp), and the other curve (dashed line) represents the attenuator operating in the attenuation state (Att_w / Ccomp). In example (b), the horizontal axis (X-axis) represents the signal frequency, and the vertical axis (Y-axis) represents the phase of the signal from port 1 to port 2 (S21). (Combined with...) Figure 2 (a) and Figure 2 As can be seen from (b) in the equation, the fixed capacitor Ccomp can introduce an additional pole in the decaying state, so that compared with the low frequency, the phase curve of the decaying state changes from negative to positive with frequency, making the phase in the decaying state change from leading to lagging, thus reducing parasitic phase modulation. Equation (1) shows Figure 2 f (within the dashed box) π ,ω / CC,Att, p2 The value of this point.

[0046]

[0047] In formula (1), Rp and RL are Figure 1 The corresponding resistance value of the device, Ccomp is Figure 1 The capacitance value of the corresponding device, R M2 for Figure 1 The resistance value of transistor M2.

[0048] However, this parallel fixed capacitor compensation method has a good phase compensation effect at a single temperature. But usually, because the device parameters of other devices, such as transistors, change with temperature, the required capacitance value varies at different temperatures. However, the fixed capacitor changes less with temperature. Therefore, the phase compensation effect of this parallel fixed capacitor method is not ideal when the temperature changes.

[0049] In another embodiment of this disclosure, see Figure 3 This illustrates a schematic diagram of another numerically controlled attenuator 10 provided in an embodiment of this disclosure. For example... Figure 3As shown, the numerically controlled attenuator 10 includes a transmission trunk 11 and an attenuation branch 12. The transmission trunk 11 is connected in series between the RF input terminal Rfin and the RF output terminal Rfout. One end of the attenuation branch 12 is connected to the transmission trunk 11. At least one attenuation branch 12 includes a first resistor 121, a first transistor 122, and an adjustable capacitor 123. The first resistor 121 and the first transistor 122 are connected in series. The first resistor 121 and the adjustable capacitor 123 are connected in parallel. The control terminal of the adjustable capacitor 123 receives a bias voltage Vbias. The capacitance value of the adjustable capacitor 123 is adjusted by the bias voltage Vbias.

[0050] It should be understood that the numerically controlled attenuator 10 is a passive device, and the direction of the radio frequency signal between the radio frequency input terminal Rfin and the radio frequency output terminal Rfout can be changed, so their actual physical positions can be interchanged.

[0051] It should be noted that the capacitance value of the adjustable capacitor 123 is related to the value of the bias voltage Vbias. In this way, by adjusting the value of the bias voltage Vbias to adjust the capacitance value of the adjustable capacitor 123 under different ambient temperatures, different phase compensations can be achieved for different temperatures, so that the digitally controlled attenuator 10 has a small amount of parasitic phase modulation under different temperatures.

[0052] In some embodiments, see Figure 4 In (a), the adjustable capacitor 123 includes a third transistor 123a and a fourth transistor 123b. The input and output terminals of the third transistor 123a and the input and output terminals of the fourth transistor 123b are connected together to form a connection point, and the connection point receives a bias voltage Vbias.

[0053] It should be noted that the third transistor 123a can be made of various types of transistors, such as MOS transistors, JFETs, bipolar junction transistors (BJTs), etc.

[0054] Taking the third transistor 123a and the fourth transistor 123b as examples of using MOSFETs, the input terminal refers to one of the source and drain terminals in the MOSFET, the output terminal refers to the other of the source and drain terminals in the MOSFET, and the control terminal refers to the gate. Therefore, when the source and drain terminals of the third transistor 123a and the fourth transistor 126b are connected together, the insulating layer (oxide) between the gate and the source and drain will form a capacitor, and the capacitance value can be adjusted by the voltage difference between the source and drain terminals and the gate. Using a MOSFET as the adjustable capacitor 123 has the following advantages: (1) Within an appropriate bias range, the capacitance value changes linearly with the bias voltage Vbias. Please refer to Figure 4(b) shows a schematic diagram of the capacitance of the adjustable capacitor formed by the N-type doped MOSFET as a function of the bias voltage Vbias; (2) it has a high capacitance density, saving circuit area; (3) it consumes almost no static power.

[0055] In other embodiments, please refer to Figure 5 In (a), the adjustable capacitor 123 includes a first diode 123c and a second diode 123d. The positive terminals of the first diode 123c and the second diode 123d both receive a bias voltage Vbias. The negative terminal of the first diode 123c serves as the first terminal of the adjustable capacitor 123, and the negative terminal of the second diode 123d serves as the second terminal of the adjustable capacitor 123.

[0056] Thus, adjustable capacitor 123 can also be formed using diodes; please refer to [link / reference]. Figure 5 (b) shows a schematic diagram of the change of the capacitance of the diode-formed adjustable capacitor 123 with the bias voltage Vbias. The diode-formed adjustable capacitor 123 has the following advantages: (1) fast adjustment response speed; (2) small size, light weight, small circuit area, and low cost; (3) low power consumption, with almost no current consumption.

[0057] It should be understood that, due to the device characteristics of other transistors in the numerically controlled attenuator 10, the higher the ambient temperature, the larger the capacitance of the adjustable capacitor 123 is desired to reduce parasitic phase modulation. In this example, such as Figure 4 (b) and Figure 5 As shown in (b) of the diagram, the capacitance of the adjustable capacitor 123 increases with increasing bias voltage Vbias. Therefore, as the temperature rises, it is desirable for the bias voltage Vbias to increase. Please refer to [link to diagram]. Figure 4 (c) shows an ideal curve of the bias voltage Vbias required for the adjustable capacitor 123 composed of an N-type doped MOSFET as a function of temperature; see also (c). Figure 5 (c) shows an ideal curve of the bias voltage Vbias required for the adjustable capacitor 123 composed of diodes as a function of temperature.

[0058] In a specific scenario, targeting Figure 5 In (c), Tmin is -40℃, Tmax is 85℃, Vmin is 0V, and Vmax is 2.5V. This means that within the temperature range of -40℃ to 85℃, the bias voltage Vbias exhibits a linear variation with temperature within the range of 0-2.5V. This corresponds to the change in the capacitance of the adjustable capacitor 123 with temperature, resulting in relatively small parasitic phase modulation values ​​at different temperatures. 。

[0059] Based on this, please refer to some embodiments. Figure 6The numerically controlled attenuator 10 also includes a control circuit 13, which is connected to the control terminal of the adjustable capacitor 123. The control circuit 13 is used to output a bias voltage Vbias with a positive temperature coefficient.

[0060] In this way, the bias voltage Vbias increases with the rise in temperature, and the capacitance of the adjustable capacitor 123 increases with the rise in temperature. It provides the corresponding capacitance at different temperatures to reduce parasitic phase modulation, thereby achieving compensation at different temperatures. This allows the digitally controlled attenuator 10 to maintain a small amount of parasitic phase modulation at both high and low temperatures.

[0061] There are many types of numerically controlled attenuators 10. According to the application scenario, they can be divided into single-ended attenuators and differential attenuators. According to the structure, they can be divided into π-type structure, T-type structure, L-type structure, etc. The following provides several specific examples.

[0062] Depending on the application scenario, numerically controlled attenuators can adopt single-ended or differential structures.

[0063] See Figures 6-8 Any one of them, the numerically controlled attenuator 10 is a single-ended attenuator; the attenuation branch 12 includes at least one first resistor 121 and at least one first transistor 122 connected in series; each first resistor 121 is connected in parallel with an adjustable capacitor 123.

[0064] Please see Figures 9-14 Any one of them, the numerically controlled attenuator 10 is a differential attenuator, applied to differential signal transmission scenarios, there are 2 transmission trunks 11, the first transmission trunk 11 is connected in series between the positive RF input terminal Rfin+ and the positive RF output terminal Rfout+, the second transmission trunk 11 is connected in series between the negative RF input terminal Rfin- and the negative RF output terminal Rfout-, the attenuation branch 12 is connected between the two transmission trunks 11; the attenuation branch 12 is connected in series between the first transmission trunk 11 and the second transmission trunk 11, the circuit devices of the attenuation branch 12 near one transmission trunk 11 are symmetrical and the same as the circuit devices of the attenuation branch 12 near the other transmission trunk 11.

[0065] The following provides descriptions of several specific types of single-ended attenuators.

[0066] Please see Figure 6 It shows a digitally controlled attenuator 10 with a π-type single-ended structure, such as Figure 6As shown, the transmission trunk 11 includes a second transistor 111 and a second resistor 112. The second transistor 111 is connected in series between the RF input terminal Rfin and the RF output terminal Rfout, and the second resistor 112 is connected in parallel with the second transistor 111. There are two attenuation branches 12. One end of the first attenuation branch 12 is connected to the input terminal of the second transistor 111, and the other end of the first attenuation branch 12 is connected to the standard ground. One end of the second attenuation branch 12 is connected to the output terminal of the second transistor 111, and the other end of the second attenuation branch 12 is connected to the standard ground.

[0067] The advantages of the π-type numerically controlled attenuator are as follows: (1) Wide bandwidth performance, suitable for high frequency applications, with good frequency response; (2) Impedance matching, easy to achieve input and output impedance matching, reducing signal reflection; (3) Large attenuation range, a large attenuation range can be achieved by adjusting the resistance value; (4) Simple structure, easy to design and implement; (5) Adjustable capacitor 123 provides phase compensation at different temperatures, making the numerically controlled attenuator have low parasitic phase modulation.

[0068] Please see Figure 7 It shows a digitally controlled attenuator 10 with a T-type single-ended structure. For example... Figure 7 As shown, the transmission trunk 11 includes a second transistor 111, a second resistor 112, and a third resistor 113; the second transistor 111 is connected in series between the RF input terminal Rfin and the RF output terminal Rfout, the second resistor 112 and the third resistor 113 are connected in series to form a resistor unit, and the resistor unit is connected in parallel with the second transistor 111; the number of attenuation branches 12 is 1, one end of the attenuation branch 12 is connected to the series connection point of the second resistor 112 and the third resistor, and the other end of the attenuation branch 12 is connected to the standard ground.

[0069] The advantages of the T-type numerically controlled attenuator are as follows: (1) Good symmetry, with symmetrical input and output impedances, suitable for differential signal processing; (2) Low insertion loss, with small insertion loss at low attenuation values; (3) High flexibility, with different attenuation values ​​achieved by adjusting the resistance value; (4) Suitable for low-frequency applications, with good performance in the low-frequency and mid-frequency range; (5) Adjustable capacitors 123 provide phase compensation at different temperatures, giving the numerically controlled attenuator lower parasitic phase modulation.

[0070] Please see Figure 8 This illustrates a digitally controlled attenuator 10 employing a bridge-T single-ended structure. For example... Figure 8As shown, the transmission trunk 11 includes a second transistor 111, a second resistor 112, a third resistor 113, and a fourth resistor 114. The second transistor 111 is connected in series between the RF input terminal Rfin and the RF output terminal Rfout. The second resistor 112 and the third resistor 113 are connected in series to form a resistor unit, and the resistor unit is connected in parallel with the second transistor 111. The fourth resistor 114 is connected in parallel with the second transistor 111.

[0071] The advantages of the bridge T-type structure numerically controlled attenuator are as follows: (1) High-precision attenuation, which can achieve very precise attenuation control; (2) Good frequency response, which is suitable for wide-band applications, especially in the high-frequency range; (3) Good impedance matching, which can better maintain the matching of input and output impedance; (4) Low reflection loss, which is relatively small in high-frequency applications; (5) Adjustable capacitor 123 provides phase compensation at different temperatures, which makes the numerically controlled attenuator have low parasitic phase modulation.

[0072] The following provides a description of several specific structures of the first type of differential attenuator.

[0073] Please refer to Figures 9-11 In any one of these configurations, the attenuation branch 12 includes 2n first resistors 121 connected in series, at least one first transistor 122, and 2n adjustable capacitors 123. Each first resistor 121 is connected in parallel with an adjustable capacitor 123, where N is a positive integer. n first resistors 121 are connected in series between the first transmission trunk and the first transistor 122, and the other n first resistors 121 are connected in series between the first transistor 122 and the second transmission trunk. For Figures 9-11 For example, n=1, each attenuation branch 12 includes two first resistors 121, one first transistor 122 and two adjustable capacitors 123. The first transistor 122 is connected in series between the two first resistors 121, and the adjustable capacitor 123 is connected in parallel with the first resistors 121.

[0074] Please see Figure 9 This shows a schematic diagram of the structure of the first type of numerically controlled attenuator 10 employing a π-type differential structure. For example... Figure 9 As shown, the numerically controlled attenuator 10 includes two transmission trunks 11 and two attenuation branches 12. Each transmission trunk 11 includes a second transistor 111 and a second resistor 112. The first attenuation branch 12 is connected in series between the input terminal of the second transistor 111 in the first transmission trunk 11 and the input terminal of the second transistor 111 in the second transmission trunk 11. The second attenuation branch 12 is connected in series between the output terminal of the second transistor 111 in the first transmission trunk 11 and the output terminal of the second transistor 111 in the second transmission trunk 11.

[0075] Please see Figure 10This shows a schematic diagram of the first type of digitally controlled attenuator 10 employing a T-type differential structure. (See attached diagram.) Figure 10 As shown, the numerically controlled attenuator 10 includes two transmission trunks 11 and one attenuation branch. The transmission trunk 11 includes a second transistor 111, a second resistor 112 and a third resistor 113. The attenuation branch 12 is connected in series at the connection point of the second resistor 112 and the connection point of the third resistor 113 in the first transmission trunk 11 and the connection point of the second resistor 112 and the third resistor 113 in the second transmission trunk 11.

[0076] Please see Figure 11 This shows a schematic diagram of the first type of digitally controlled attenuator 10 employing a T-type differential structure. (See attached diagram.) Figure 11 As shown, the numerically controlled attenuator 10 includes two transmission trunks 11 and one attenuation branch. The transmission trunk 11 includes a second transistor 111, a second resistor 112, a third resistor 113, and a fourth resistor 114. The attenuation branch 12 is connected in series at the connection point of the second resistor 112 and the third resistor 113 in the first transmission trunk 11 and the connection point of the second resistor 112 and the third resistor 113 in the second transmission trunk 11.

[0077] The following provides a description of several specific structures of the second type of differential attenuator.

[0078] Please refer to Figures 12-14 In any one of these configurations, the attenuation branch 12 includes 2n first transistors 122 connected in series, at least one first resistor 121, and at least one adjustable capacitor 123; n first transistors 122 are connected in series between the first transmission trunk and the first resistor 121, and the other n first transistors 122 are connected in series between the first resistor 121 and the second transmission trunk; each first resistor 121 is connected in parallel with an adjustable capacitor 123. Thus, the attenuation branch 12 presents a symmetrical structure.

[0079] Please see Figure 12 This illustrates a schematic diagram of the second type of digitally controlled attenuator 10 employing a π-type differential structure. For example... Figure 12 As shown, the numerically controlled attenuator 10 includes two transmission trunks 11 and two attenuation branches 12. Each attenuation branch 12 includes two first transistors 122, one first resistor 121, and one adjustable capacitor 123. The first resistor 121 is connected in series between the two first transistors 122, and the adjustable capacitor 123 is connected in parallel with the first resistor 121. Other structures are similar to those shown. Figure 9 same.

[0080] Please see Figure 13 This illustrates a schematic diagram of the second type of digitally controlled attenuator 10 employing a T-type differential structure. (See diagram for example.) Figure 13As shown, the numerically controlled attenuator 10 includes two transmission trunks 11 and one attenuation branch 12. Each attenuation branch 12 includes two first transistors 122, one first resistor 121, and one adjustable capacitor 123. Other structures are similar to those shown. Figure 10 same.

[0081] Please see Figure 14 This illustrates a schematic diagram of a second type of digitally controlled attenuator 10 employing a bridge-T differential structure. (See diagram for example.) Figure 14 As shown, the numerically controlled attenuator 10 includes two transmission trunks 11 and one attenuation branch 12. Each attenuation branch 12 includes two first transistors 122, one first resistor 121, and one adjustable capacitor 123. Other structures are similar to those shown. Figure 11 same.

[0082] exist Figures 6 to 14 In this diagram, the components in each numerically controlled attenuator 10 are conceptual illustrations. The first transistor and the second transistor are abstract units, but in reality, they can include multiple independent transistor devices. For example, the first transistor can include multiple transistor devices connected in series and / or in parallel, and can even include resistors. As long as the overall device has transistor-like operating characteristics, it can be considered the first transistor. The same applies to other transistors and the transistor concepts described later. In addition, the first resistor to the third resistor and the resistors described later can each include multiple resistor devices connected in series and / or in parallel. Besides those shown in the figures, the transmission trunk 11 and the attenuation branch 12 can also include other circuit devices, such as other transistors, other resistors, and other capacitors.

[0083] In particular, Figures 6 to 14 In the attenuation branch 12, the control terminal of the transistor receives the main control signal Vctrl to control the attenuation amount; the control terminal of the transistor in the transmission trunk 11 receives the feedback control signal Vtune. The feedback control signal Vtune and the main control signal Vctrl have a dynamic negative correlation, which can compensate for the change in standing wave caused by the change in the main control signal Vctrl. Thus, the digitally controlled attenuator 10 can operate in the radio frequency link with better standing wave characteristics.

[0084] In some embodiments, see Figure 15 The aforementioned control circuit 13 includes:

[0085] Temperature reference voltage source 131 is configured to output an initial voltage that is positively correlated with absolute temperature;

[0086] The first adjustment circuit 132 is connected to the temperature reference voltage source 131 and is configured to receive the initial voltage and output the intermediate voltage. The intermediate voltage changes linearly with the initial voltage and the slope of the change is greater than 1.

[0087] The second adjustment circuit 133 is cascaded with the first adjustment circuit 132; it is configured to receive the intermediate voltage and output the bias voltage Vbias, the bias voltage Vbias changing linearly with the intermediate voltage, and the slope of the change being greater than 1.

[0088] It should be noted that the temperature reference voltage source 131 is also called a PTAT (Proportional To Absolute Temperature) voltage source, which generates an initial voltage (also called a PTAT voltage) that is proportional to the absolute temperature. Please refer to [link to relevant documentation]. Figure 16 It shows a schematic diagram of the change of initial voltage with absolute temperature. Figure 16 This is just one example; the initial voltage doesn't necessarily have to be zero-crossing; it can also have an intercept, for example... Figure 19 (a) shows another initial voltage V TC A schematic diagram showing how temperature changes.

[0089] In one example, the temperature reference voltage source 131 can be implemented by a pair of bipolar transistors, an operational amplifier, a resistor network, etc.; the first adjustment circuit 132 and the second adjustment circuit 133 are used to further amplify / reduce the initial voltage to the required linear voltage range to obtain the bias voltage Vbias, so that the capacitance of the adjustable capacitor 123 becomes more linear with the change of the bias voltage Vbias, while being within the required voltage range.

[0090] In some embodiments, see Figure 17 The temperature reference voltage source 131 includes a first current branch 21a, a second current branch 21b, a first bipolar transistor 215, a second bipolar transistor 216, and a fifth resistor 217. The second current branch 21b replicates the current of the first current branch 21a. The input terminals of the first current branch 21a and the second current branch 21b receive the power supply voltage. The output terminal of the first current branch 21a is connected to the standard ground via the first bipolar transistor 215. The output terminal of the second current branch 21b is connected to the standard ground via the fifth resistor 217 and the second bipolar transistor 216 connected in series. The control terminals of the first bipolar transistor 215 and the second bipolar transistor 216 are both connected to the standard ground.

[0091] Please see Figure 17The first current branch 21a includes a fifth transistor 211 and a sixth transistor 212, and the second current branch 21b includes a seventh transistor 213 and an eighth transistor 214. The input terminals of the fifth transistor 211 and the seventh transistor 213 receive the power supply voltage; the control terminal of the sixth transistor 212, the input terminal of the sixth transistor 212, the control terminal of the eighth transistor 214, and the output terminal of the fifth transistor 211 are connected together; the control terminal of the seventh transistor 213, the output terminal of the seventh transistor 213, the control terminal of the fifth transistor 211, and the input terminal of the eighth transistor 214 are connected together; the output terminal of the sixth transistor 212 is connected to standard ground via a first bipolar transistor 215; the output terminal of the eighth transistor 214 is connected to standard ground sequentially via a second resistor and a second bipolar transistor 216.

[0092] Please see Figure 17 The temperature reference voltage source 131 also includes a third current branch 22, which replicates the current of the first current branch 21a. The third current branch 22 includes a ninth transistor 221 and a sixth resistor 222. The control terminal of the ninth transistor 221 is connected to the control terminal of the seventh transistor 213. The input terminal of the ninth transistor 221 receives the power supply voltage, and the output terminal of the ninth transistor 221 outputs the initial voltage V. TC The free end of the sixth resistor 222 is connected to standard ground.

[0093] Please see Figure 17 Assuming that transistors 212 through 221 are all transistors with the same device parameters, then:

[0094] I D1 =I D2 =I D5 =(V T lnn) / R1………………(2)

[0095] Where n is a constant, specifically the ratio of the current of the first bipolar transistor to the current of the second bipolar transistor 216.

[0096] Among them, V T = kT / q, where T is the absolute temperature, q is the electron charge, and k is a constant. Therefore, the initial voltage V TC It varies linearly with absolute temperature; please refer to [reference needed]. Figure 17 I D1 This refers to the current I in the first current branch 21a. D2 This refers to the current in the second current branch 21b, I. D5 This refers to the current in the third current branch 22 and the resistance value of the fifth resistor 217 in R1.

[0097] Initial voltage V TC Specifically:

[0098] V TC =(V T lnn)R2 / R1………………(3)

[0099] R2 refers to the resistance value of the sixth resistor 222.

[0100] Here, the device parameters of transistors 211 to 221 can be different, at which point I D1 I D5 They are no longer equal, but rather have a proportionality coefficient a, i.e., I D5 =a·I D1 If a > 0, then the initial voltage V TC The coefficient of variation changes with temperature.

[0101] In some embodiments, the first adjustment circuit 132 includes a first voltage proportional amplifier. The second adjustment circuit 133 includes a second voltage proportional amplifier. The voltage proportional amplifier may also be referred to as a multiplier, feedback amplifier, proportional amplifier, etc., and specifically includes an operational amplifier and a resistor.

[0102] Please see Figure 18 The first adjustment circuit 132 includes a first operational amplifier 31, a seventh resistor 32, and an eighth resistor 33. Specifically, the first input terminal of the first operational amplifier 31 receives the initial voltage V. TC The seventh resistor 32 and the eighth resistor 33 are connected in series, and the series connection point is connected to the second input terminal of the first operational amplifier 31. The free end of the seventh resistor 32 is connected to the output terminal of the first operational amplifier 31, and the free end of the eighth resistor 33 is connected to the first preset voltage terminal V. R1 The first operational amplifier 31 outputs an intermediate voltage Vo. At this time, the intermediate voltage Vo is given by formula (4).

[0103]

[0104] Where R7 refers to the resistance value of the seventh resistor 32, and R8 refers to the resistance value of the eighth resistor 33.

[0105] Please see Figure 18 The second adjustment circuit 133 includes a second operational amplifier 36, a ninth resistor 34, and a tenth resistor 35. Specifically, the ninth resistor 34 and the tenth resistor 35 are connected in series, and the series connection point is connected to the first input terminal of the second operational amplifier 36. The free end of the ninth resistor 34 receives the intermediate voltage Vo, and the free end of the tenth resistor 35 is connected to the second preset power supply terminal V. R2 The first input terminal of the second operational amplifier 36 is connected to its own output terminal, and this output terminal outputs a bias voltage Vbias. At this time, the intermediate voltage Vbias is as shown in the following formula.

[0106]

[0107] Wherein, R9 refers to the resistance value of the ninth resistor 34, R 10 This refers to the resistance value of the tenth resistor, which is 35.

[0108] Therefore, the bias voltage Vbias and the initial voltage V TC The relationship is shown below, and both its slope and intercept can be adjusted.

[0109]

[0110] Please see Figure 19 (a) shows an example of the initial voltage V. TC The slope k0 and intercept a0 of the temperature-dependent curve are both constants; please refer to [link to relevant documentation]. Figure 19 Figure (b) shows the curve of the intermediate voltage Vo as a function of temperature, with a slope of... Intercept is Please see Figure 19 Figure (c) shows the curve of bias voltage Vbias as a function of temperature, with a slope of... Intercept is

[0111] Thus, when the initial voltage V is generated TC Afterwards, the required bias voltage Vbias is generated through two stages of bias circuitry. This is achieved by appropriately setting the seventh resistor R7 to the tenth resistor R... 10 The resistance value, the preset voltage source V R1 V R2 By determining the voltage value, the required bias voltage Vbias can be obtained. Simultaneously, by selecting resistors with different electrical parameters from the seventh resistor R7 to the tenth resistor R... 10 It enables the slope of the bias voltage Vbias to be positive and adjustable, and the intercept to be adjustable.

[0112] In other embodiments, please refer to Figure 20 The control circuit 13 includes a temperature reference voltage source 131, a temperature sensor 134, and a digital-to-analog converter 135 connected in sequence; wherein, the temperature reference voltage source 131 generates an initial voltage that is positively correlated with the absolute temperature; the temperature sensor 134 converts the initial voltage into a temperature code, and the digital-to-analog converter converts the temperature code into a bias voltage.

[0113] In this way, the temperature reference voltage source 131 (PTAT voltage source) generates an initial voltage, and the temperature sensor 134 generates a corresponding temperature code (digital signal). Thus, the combined structure of the temperature reference voltage source 131 and the temperature sensor 134 can measure the current ambient temperature and convert it into a corresponding temperature code. The digital-to-analog converter 135 converts the digital temperature code into an analog signal, which is the required bias voltage. In other examples, the digital-to-analog converter 135 outputs a temperature-varying current, which is then converted into the required bias voltage through resistors and other circuit components.

[0114] In summary, in active phased array systems, passive digitally controlled attenuators (DCAs) are a crucial component of the T / R (transmit / receive) assembly, serving to calibrate gain differences between different channels and improve the sidelobe suppression ratio. To accurately adjust the beam size, direction, and main-sidelobe ratio of the phased array antenna, DCAs require low parasitic phase modulation. However, in practical applications, due to significant ambient temperature variations, the parasitic phase modulation of DCAs changes considerably at high and low temperatures, introducing deviations. To maintain low parasitic phase modulation of DCAs at high and low temperatures, this embodiment proposes a parasitic phase modulation temperature compensation method for DCAs. Please refer to [link to relevant documentation]. Figure 16 In the attenuation branch 12 of the numerically controlled attenuator 10, an adjustable capacitor 123 is connected in parallel with the resistor. The capacitance of the adjustable capacitor 123 increases with the bias voltage Vbias, and the bias voltage Vbias increases linearly with increasing temperature. Therefore, the capacitance of the adjustable capacitor 123 is different under different ambient temperatures, thereby achieving dynamic phase compensation at different temperatures. The adjustable capacitor 123 can be formed by at least a MOSFET or a diode.

[0115] Please see Figure 21 They respectively illustrate digitally controlled attenuators using fixed capacitors (see [link to documentation]). Figure 1 Parasitic phase modulation with temperature variation at 25 GHz RF signal and digitally controlled attenuators using adjustable capacitors (see [link to relevant documentation]). Figure 3 The parasitic phasing at 25 GHz varies with temperature. Figure 21 It can be seen that if a fixed capacitor is used, the parasitic phase modulation is only low at around 30°C; however, if an adjustable capacitor is used, the parasitic phase modulation can be maintained at a low level in the range of -40°C to 125°C.

[0116] Thus, this disclosure proposes a digitally controlled attenuator that does not drift with temperature due to parasitic phase modulation. By introducing an adjustable capacitor in the attenuation branch, the drift of parasitic phase modulation at different temperatures can be compensated. Specifically, it can be implemented using a MOSFET variable capacitor, a diode variable capacitor, or other forms of variable capacitor. This can minimize the parasitic phase modulation under different temperature environments, without requiring additional feedback networks or other attenuation units for compensation, and without requiring additional digital control signals, thereby reducing the design cost of the chip.

[0117] In yet another embodiment of this disclosure, see [link to relevant documentation]. Figure 22 This illustrates a schematic diagram of the composition structure of a phased array system 50 provided in an embodiment of this disclosure. For example... Figure 22 As shown, the phased array system 50 includes at least the aforementioned digitally controlled attenuator 10.

[0118] In addition, the phased array system 50 may also include an antenna array, phase and amplitude controllers, beamformers, etc. In this way, since the capacitance of the adjustable capacitor 123 in the digitally controlled attenuator 10 changes accordingly at different temperatures, it can achieve drift compensation for parasitic phase modulation at different temperatures. Thus, the digitally controlled attenuator 10 has low parasitic phase modulation at both high and low temperatures, and the phased array system 50 can accurately adjust the size, direction, and main-sidelobe ratio of the phased array antenna beam.

[0119] The above are merely preferred embodiments of this disclosure and are not intended to limit the scope of protection of this disclosure. It should be noted that in this disclosure, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that includes a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element. The sequence numbers of the embodiments in this disclosure are merely descriptive and do not represent the superiority or inferiority of the embodiments. The methods disclosed in the several method embodiments provided in this disclosure can be arbitrarily combined to obtain new method embodiments without conflict. The features disclosed in the several product embodiments provided in this disclosure can be arbitrarily combined to obtain new product embodiments without conflict. The features disclosed in the several method or device embodiments provided in this disclosure can be arbitrarily combined to obtain new method or device embodiments without conflict. The above are merely specific embodiments of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure.

Claims

1. A digitally controlled attenuator, characterized in that, The numerically controlled attenuator includes a transmission trunk and an attenuation branch. The transmission trunk is connected in series between the RF input terminal and the RF output terminal, and one end of the attenuation branch is connected to the transmission trunk. At least one of the attenuation branches includes a first resistor, a first transistor, and an adjustable capacitor, wherein the first resistor and the first transistor are connected in series; the first resistor is connected in parallel with the adjustable capacitor, the control terminal of the adjustable capacitor receives a bias voltage, and the capacitance value of the adjustable capacitor is adjusted by the bias voltage.

2. The numerically controlled attenuator according to claim 1, characterized in that, The adjustable capacitor includes a third transistor and a fourth transistor. The input and output terminals of the third transistor and the input and output terminals of the fourth transistor are connected together to form a connection point, and the connection point receives the bias voltage.

3. The numerically controlled attenuator according to claim 1, characterized in that, The adjustable capacitor includes a first diode and a second diode, both of which receive the bias voltage at their positive terminals.

4. The digitally controlled attenuator according to any one of claims 1-3, characterized in that, The numerically controlled attenuator also includes a control circuit, which is connected to the control terminal of the adjustable capacitor. The control circuit is used to output the bias voltage with a positive temperature coefficient.

5. The digitally controlled attenuator according to any one of claims 1-3, characterized in that, The numerically controlled attenuator is a single-ended attenuator. The attenuation branch includes at least one first resistor and at least one first transistor connected in series; each first resistor is connected in parallel with the adjustable capacitor.

6. The digitally controlled attenuator according to any one of claims 1-3, characterized in that, The digitally controlled attenuator is a differential attenuator, and there are two transmission trunks. The first transmission trunk is connected in series between the positive RF input terminal and the positive RF output terminal, and the second transmission trunk is connected in series between the negative RF input terminal and the negative RF output terminal. The attenuation branch is connected in series between the first transmission trunk and the second transmission trunk, and the circuit devices of the attenuation branch near one transmission trunk are symmetrical and identical to the circuit devices of the attenuation branch near the other transmission trunk.

7. The digitally controlled attenuator according to any one of claims 1-3, characterized in that, The transmission trunk includes a second transistor and a second resistor, wherein the second transistor is connected in series between the RF input terminal and the RF output terminal, and the second resistor is connected in parallel with the second transistor; The number of attenuation branches is 2. One end of the first attenuation branch is connected to the input terminal of the second transistor, and one end of the second attenuation branch is connected to the output terminal of the second transistor.

8. The digitally controlled attenuator according to any one of claims 1-3, characterized in that, The transmission trunk includes a second transistor, a second resistor, and a third resistor; the second transistor is connected in series between the RF input terminal and the RF output terminal, the second resistor and the third resistor are connected in series to form a resistor unit, and the resistor unit is connected in parallel with the second transistor; The number of attenuation branches is 1, and one end of the attenuation branch is connected to the series connection point of the second resistor and the third resistor.

9. The numerically controlled attenuator according to claim 4, characterized in that, The control circuit includes: A temperature reference voltage source is configured to output an initial voltage that is positively correlated with the absolute temperature. The first adjustment circuit is connected to the temperature reference voltage source and is configured to receive the initial voltage and output an intermediate voltage, wherein the intermediate voltage changes linearly with the initial voltage and the slope of the change is greater than 1. The second adjustment circuit is cascaded with the first adjustment circuit; it is configured to receive the intermediate voltage and output the bias voltage, wherein the bias voltage changes linearly with the intermediate voltage and the slope of the change is greater than 1.

10. The numerically controlled attenuator according to claim 9, characterized in that, The first adjustment circuit includes a first voltage proportional amplifier, and the second adjustment circuit includes a second voltage proportional amplifier; The first voltage proportional amplifier has a gain greater than 1, the second voltage proportional amplifier has a gain less than 1, and each voltage proportional amplifier includes at least an operational amplifier and a resistor.

11. The numerically controlled attenuator according to claim 4, characterized in that, The control circuit includes a temperature reference voltage source, a temperature sensor, and a digital-to-analog converter connected in sequence. The temperature reference voltage source outputs an initial voltage that is positively correlated with the absolute temperature; the temperature sensor converts the initial voltage into a temperature code, and the digital-to-analog converter converts the temperature code into the bias voltage.

12. A phased array system, characterized in that, The phased array system includes a digitally controlled attenuator as described in any one of claims 1-11.

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