Electronic carrier board

By introducing a second insulating layer to cover the adhesive layer in the redistribution layer, the problem of the redistribution layer peeling off during the etching process is solved, thus achieving protection of the adhesive layer and improving the stability of the structure.

CN224265181UActive Publication Date: 2026-05-19KORE SEMICONDUCTOR INC
View PDF 0 Cites 0 Cited by

Patent Information

Authority / Receiving Office
CN · China
Patent Type
Utility models(China)
Current Assignee / Owner
KORE SEMICONDUCTOR INC
Filing Date
2025-05-29
Publication Date
2026-05-19

AI Technical Summary

Technical Problem

The existing redistribution layer has a problem where gaps are formed due to the erosion of the adhesive material during the etching process, making it easy for the redistribution layer to peel off from the carrier board.

Method used

A second insulating layer is used to completely cover the adhesive layer, forming a sealing part to protect the adhesive layer, avoid damage during the etching process, and improve the bonding strength through the interlocking contact surfaces.

Benefits of technology

It effectively prevents the adhesive layer from being damaged during etching, avoids the peeling of the redistribution layer's self-supporting components, and improves the stability and durability of the structure.

✦ Generated by Eureka AI based on patent content.

Smart Images

  • Figure CN224265181U_ABST
    Figure CN224265181U_ABST
Patent Text Reader

Abstract

An electronic carrier plate includes a carrier member, an adhesive layer, a first insulating layer and a second insulating layer. The first insulating layer is bonded to the carrier through the adhesive layer. The second insulating layer is arranged on the first insulating layer and wraps the adhesive layer and the first insulating layer. The second insulating layer can completely cover the adhesive layer so as to prevent the adhesive layer from being eroded by an etching process or damaged due to other reasons. Therefore, the adhesive layer can be protected so as to prevent the insulating layer from being stripped from the bearing part.
Need to check novelty before this filing date? Find Prior Art

Description

Technical Field

[0001] This application relates to a semiconductor structure, and more particularly to an electronic carrier. Background Technology

[0002] Redistribution layers are commonly found in existing semiconductor packages and are used to electrically connect electronic components such as semiconductor wafers, resistors, capacitors, and inductors within the package, or to provide external electrical connections for these electronic components. A typical redistribution layer includes at least one insulating layer and at least one wiring layer bonded to the insulating layer.

[0003] Please see Figure 1 This is a partial cross-sectional view of an existing circuit board 1. The circuit board 1 includes a carrier board 11, an adhesive 12, and a redistribution layer 13. The redistribution layer 13 is bonded to the carrier board 11 via the adhesive 12 and includes multiple insulating layers 131 and multiple circuit layers 132 bonded to the multiple insulating layers 131. In addition, the redistribution layer 13 is provided with openings 101.

[0004] When plasma etching is performed in the opening 101, the adhesive 12 will be eroded to form gaps 121 and 122, which will cause the redistribution layer 13 to peel off, i.e. it is easy to peel off the self-supporting board 11. Utility Model Content

[0005] To address the aforementioned problems, this application provides an electronic carrier board, comprising a carrier member, an adhesive layer, a first insulating layer, and a second insulating layer. The first insulating layer is bonded to the carrier member via the adhesive layer. The second insulating layer is disposed on the first insulating layer and covers both the adhesive layer and the first insulating layer.

[0006] The aforementioned second insulating layer can completely cover the adhesive layer to prevent the adhesive layer from being eroded by the etching process or damaged for other reasons. This protects the adhesive layer from peeling off the aforementioned insulating layer from the carrier. Attached Figure Description

[0007] Figure 1 This is a partial cross-sectional view of an existing circuit board.

[0008] Figure 2 This is a partial cross-sectional schematic diagram of an electronic carrier board according to an embodiment of this application.

[0009] Figure 3 This is a partial cross-sectional schematic diagram of the contact surface of the insulating layer according to an embodiment of this application.

[0010] Explanation of reference numerals in the attached figures

[0011] 1 Circuit board

[0012] 101 opening

[0013] 11 Carrier Board

[0014] 12 Adhesive Materials

[0015] Gap 121, 122

[0016] 13 Rewiring Layer

[0017] 131 Insulation layer

[0018] 132 Line Layer

[0019] 2 Electronic Carrier

[0020] 201 Opening

[0021] 21. Bearing components

[0022] 22 Adhesive layer

[0023] 23 Wiring Structure

[0024] 231-234 First insulation layer to fourth insulation layer

[0025] 2321 Sealing part

[0026] 235-237 First Line Layer to Third Line Layer

[0027] 238 Contact surface

[0028] W represents the width. Detailed Implementation

[0029] The following specific embodiments illustrate the implementation of this application. Those skilled in the art can easily understand other advantages and effects of this application from the content disclosed in this specification.

[0030] Figure 2 This is a partial cross-sectional schematic diagram of an electronic carrier board 2 according to an embodiment of this application, including an enlarged view of a portion thereof. Figure 2 As shown, the electronic carrier 2 includes a carrier 21, an adhesive layer 22, and a wiring structure 23. The carrier 21 may be a substrate, carrier plate, or other board material or plate body. The wiring structure 23 is bonded to the carrier 21 by the adhesive layer 22, such as an adhesive material. In one application example, the electronic carrier 2 is, for example, a strip substrate used to carry a chip.

[0031] Wiring structure 23 is a rewiring layer, including at least one insulating layer and at least one wiring layer bonded to the insulating layer. For example... Figure 2As shown, the wiring structure 23 includes a first insulating layer 231, a second insulating layer 232, a third insulating layer 233, a fourth insulating layer 234, a first wiring layer 235, a second wiring layer 236, and a third wiring layer 237. The materials forming the first to fourth insulating layers 231-234 can be polybenzoxazole (PBO), polyimide (PI), prepreg (PP), or other dielectric materials. The materials forming the first to third wiring layers 235-237 can be copper or other conductive materials.

[0032] The first insulating layer 231 is bonded to the carrier 21 via the adhesive layer 22. In this embodiment, the first insulating layer 231 does not contain a wiring layer. Alternatively, in one embodiment, the first insulating layer 231 may include a wiring layer.

[0033] The second insulating layer 232 is disposed on the first insulating layer 231 and covers the adhesive layer 22 and the first insulating layer 231. The first circuit layer 235 is embedded in the second insulating layer 232 and is adjacent to the first insulating layer 231.

[0034] The third insulating layer 233 is disposed on the second insulating layer 232. The second circuit layer 236 is embedded in the third insulating layer 233 and adjacent to the second insulating layer 232.

[0035] The fourth insulating layer 234 is disposed on the third insulating layer 233. The third circuit layer 237 is embedded in the fourth insulating layer 234 and is adjacent to the third insulating layer 233.

[0036] The wiring structure 23 is provided with an opening 201, which penetrates the first insulation layer to the fourth insulation layer 231-234 and exposes the carrier 21.

[0037] The second insulating layer 232 extends parallel to the first insulating layer 231 and toward the opening 201. After extending beyond the first insulating layer 231, it turns and extends toward and to the carrier 21 to form a sealing portion 2321. The sealing portion 2321 is part of the second insulating layer 232 and completely covers the adhesive layer 22 to prevent the adhesive layer 22 from being exposed in the opening 201. In this embodiment, the width W of the sealing portion 2321 is at least 10 micrometers (μm).

[0038] Figure 3 This is a partial cross-sectional schematic diagram of the contact surface of the insulating layer according to an embodiment of this application. To improve the bonding strength between the first insulating layer 231 and the second insulating layer 232, it can be done as follows: Figure 3As shown, the contact surfaces 238 of the first insulating layer 231 and the second insulating layer 232 are made into interlocking concave-convex shapes. For example, the sealing portion 2321 of the second insulating layer 232 and the contact surface 238 of the first insulating layer 231 can be made into interlocking concave-convex shapes to prevent the relatively thin sealing portion 2321 from detaching from the first insulating layer 231 and exposing the adhesive layer 22.

[0039] In summary, the sealing portion 2321 of the second insulating layer 232 of this application can completely cover the adhesive layer 22 to prevent the adhesive layer 22 from being exposed and thus corroded by the etching process or damaged for other reasons. This protects the adhesive layer 22 from peeling off the wiring structure 23 from the carrier member 21.

[0040] The above embodiments are merely illustrative of the principles and effects of this application and are not intended to limit this application. Those skilled in the art can modify and alter the above embodiments without departing from the spirit and scope of this application. Therefore, the scope of protection of this application should be as set forth in the claims.

Claims

1. An electronic carrier board, characterized in that, include: One load-bearing component; One adhesive layer; A first insulating layer is bonded to the carrier through the adhesive layer; as well as A second insulating layer is disposed on the first insulating layer and covers the adhesive layer and the first insulating layer.

2. The electronic carrier board as described in claim 1, characterized in that, The second insulating layer extends parallel to the first insulating layer, extends beyond the first insulating layer and then extends toward the carrier, reaching the carrier to form a sealing portion that completely covers the adhesive layer.

3. The electronic carrier board as described in claim 2, characterized in that, The electronic carrier board has an opening that penetrates the first insulating layer and the second insulating layer, and the sealing part completely covers the adhesive layer so that the adhesive layer is not exposed in the opening.

4. The electronic carrier board as described in claim 2, characterized in that, The contact surfaces of the sealing part and the first insulating layer are made into interlocking concave and convex shapes.

5. The electronic carrier board as described in claim 2, characterized in that, The width of the seal is at least 10 micrometers.

6. The electronic carrier board as described in claim 1, characterized in that, This first insulation layer does not contain a wiring layer.

7. The electronic carrier board as described in claim 1, characterized in that, The electronic carrier board also includes: A first circuit layer is embedded in the second insulation layer and adjacent to the first insulation layer.

8. The electronic carrier board as described in claim 7, characterized in that, The electronic carrier board also includes: A third insulating layer is disposed on the second insulating layer; and A second circuit layer is embedded in the third insulation layer and adjacent to the second insulation layer.

9. The electronic carrier board as described in claim 8, characterized in that, The electronic carrier board also includes: A fourth insulating layer is disposed on the third insulating layer; and A third circuit layer is embedded in the fourth insulation layer and adjacent to the third insulation layer.