Package substrate and semiconductor package

Abstract

The utility model discloses a packaging substrate and a semiconductor package, and belongs to the technical field of semiconductor packaging. According to the invention, the core insulation structure is completely wrapped in other insulation materials with the characteristics of insulation, oxygen insulation and moisture insulation, so that the core insulation structure is not in contact with the atmosphere, the problem of wiring structure layering caused by moisture absorption of the core insulation structure is effectively avoided, and the product reliability is improved; according to the technical scheme, packaging can be completed without turning over, the technological process is simplified, compared with an existing six-face packaging process needing one-time plate releasing and turning over, the six-face packaging process is simpler and more convenient, and the packaging cost is reduced; the advantage that the core insulation structure can be provided with through holes with the diameter smaller than 10 micrometers (suitable for a fine line wiring layer) and the characteristics of other dielectric materials are combined, and the requirements of different levels are met; and by reasonably designing the width (greater than 25 [mu] m) of the encapsulating compound structure, sufficient protective force of the side wall is ensured, moisture is effectively insulated and isolated, the encapsulating compound structure is prevented from being too thin and cracked, and the reliability of the product is further improved.

Description

Technical Field

[0001] This application relates to the field of semiconductor packaging technology, and more particularly to packaging substrates and semiconductor packaging. Background Technology

[0002] As electronic products evolve towards thinner, smaller, and higher-performance designs, semiconductor packaging technology is constantly innovating. In the modern semiconductor packaging field, fan-out surface-level packaging (FOPLP) technology has garnered significant attention due to its ability to provide higher integration and better electrical performance. By packaging at the wafer level, FOPLP technology enables smaller package sizes and shorter interconnect distances, thereby improving device performance and reducing power consumption.

[0003] In traditional semiconductor packaging structures, the packaging substrate acts as a bridge connecting the chip to external circuits, and its structural design and material selection have a decisive impact on packaging performance. Currently, common packaging substrates on the market typically employ multi-layer structures, including a core layer, an insulating layer, and wiring layers. A major problem with existing technologies is that PSPI materials in FOPLP (Flat-Ended Packaging Package) are prone to moisture absorption. If exposed to atmospheric conditions, this can lead to delamination of the RDL (Residual Layer), severely impacting product reliability. Traditional solutions typically employ a six-sided packaging method using molding compounds for molding on both sides. While this method can address the moisture absorption problem to some extent, it requires additional processes such as transfer molding, molding, polishing, and disassembly, significantly increasing packaging costs and hindering product competitiveness.

[0004] Furthermore, existing packaging substrate structures lack a reasonable design in terms of the dimensional ratio between the core insulation structure and the encapsulation structure, making it impossible to control costs while ensuring packaging reliability. In particular, existing technologies fail to provide effective design parameters regarding the relationship between the height of the core insulation structure and the width of the encapsulation structure, making it difficult to achieve a balance between moisture resistance and cost control in the packaging structure.

[0005] Therefore, there is an urgent need for a new type of packaging substrate structure that can effectively solve the RDL delamination problem caused by moisture absorption of PSPI material, while avoiding the increased process and cost of traditional six-sided packaging, thereby improving the reliability and economy of semiconductor packaging. Utility Model Content

[0006] The technical problem this application aims to solve is that PSPI (photosensitive polyimide) material in FOPLP (fan-out panel-level packaging) is prone to moisture absorption, which can lead to delamination of RDL (redistribution layer) if exposed to the atmosphere, seriously affecting product reliability. At the same time, the traditional six-sided packaging method using molding compound for molding on both sides increases the number of processes (transfer, molding, grinding, and unmolding), resulting in a significant increase in packaging costs.

[0007] This application provides a packaging substrate, including:

[0008] The core insulation structure boasts the highest height.

[0009] A first encapsulating structure is applied to the lower surface and sidewalls of the core insulating structure. The first encapsulating structure has a first width, which is greater than the first height.

[0010] Multiple wiring structures extend through the core insulation structure and the first encapsulating adhesive structure, and a first connecting pad is provided on the lower surface of the wiring structure.

[0011] Optionally, the core insulation structure includes at least one first insulation layer.

[0012] Optionally, the first insulating layer is made of photosensitive polyimide.

[0013] Optionally, the thickness of the first insulating layer is between 3 μm and 20 μm.

[0014] Optionally, the first encapsulating material structure is a molding compound, and the thickness of the first encapsulating material structure is greater than 25 μm.

[0015] This application provides a packaging substrate, including:

[0016] The core insulation structure boasts the highest height.

[0017] A multilayer insulation structure is disposed on the lower surface of the core insulation structure, wherein the upper surface area of ​​the multilayer insulation structure is larger than the lower surface area of ​​the core insulation structure;

[0018] The second encapsulation structure covers the sidewall of the core insulation structure and the edge region of the upper surface of the multilayer insulation structure. The second encapsulation structure has a second width, which is greater than the first height.

[0019] Multiple wiring structures extend through the core insulation structure and the multilayer insulation structure, and a first connection pad is provided on the lower surface of the wiring structure.

[0020] Optionally, the core insulation structure includes at least one first insulation layer, the first insulation layer being made of photosensitive polyimide, and the thickness of the first insulation layer being between 3μm and 20μm.

[0021] Optionally, the multilayer insulation structure includes at least one second insulation layer, the second insulation layer being made of Ajinomoto additive material, and the thickness of the second insulation layer being between 15μm and 50μm.

[0022] This application provides a semiconductor package, including: a chip, an interposer, multiple connectors and a molding compound, and also includes the above-mentioned package substrate;

[0023] The upper surface of the wiring structure is provided with a second connection pad;

[0024] The interposer layer is located between the packaging substrate and the chip, and the interposer layer has a vertical interconnect structure inside, which is electrically connected to the connector.

[0025] The connector extends through the interposer layer and connects the second connection pad to the chip.

[0026] The molding compound encapsulates the chip and partially covers the upper surface of the packaging substrate.

[0027] This application provides a semiconductor package, including: a chip, an interposer, multiple connectors and a molding compound, and also includes the above-mentioned package substrate;

[0028] The upper surface of the wiring structure is provided with a second connection pad;

[0029] The interposer layer is located between the packaging substrate and the chip, and the interposer layer has a vertical interconnect structure inside, which is electrically connected to the connector.

[0030] The connector extends through the interposer layer and connects the second connection pad to the chip.

[0031] The encapsulation structure encapsulates the chip and partially covers the upper surface of the packaging substrate.

[0032] This application completely encapsulates the core insulation structure within other insulating materials with insulating, oxygen-proof, and moisture-proof properties, preventing it from contacting the atmosphere. This effectively avoids the delamination problem in the wiring structure caused by moisture absorption of the core insulation structure, thus improving product reliability. The application employs a packaging technology that eliminates the need for board flipping, simplifying the process and making it more convenient than the existing six-sided packaging process that requires board flipping, thereby reducing packaging costs. It combines the advantage of the core insulation structure being able to have vias smaller than 10μm (suitable for fine-line wiring layers) with the characteristics of other dielectric materials, meeting the needs of different layers. By rationally designing the width of the encapsulating adhesive structure (greater than 25μm), sufficient sidewall protection is ensured, effectively insulating and isolating moisture, preventing the encapsulating adhesive structure from cracking due to excessive thinness, further improving product reliability. Attached Figure Description

[0033] One or more embodiments are illustrated by way of example with reference numerals in the accompanying drawings. These illustrations do not constitute a limitation on the embodiments. Elements with the same reference numerals in the drawings are denoted as similar elements. Unless otherwise stated, the figures in the drawings are not to be limited by scale.

[0034] Figure 1 This is a cross-sectional view of the semiconductor package described in Embodiment 3 of this application.

[0035] Figure 2 This is a cross-sectional view of the semiconductor package described in Embodiment 4 of this application. Detailed Implementation

[0036] The advantages of this application are further illustrated below with reference to the accompanying drawings and specific embodiments.

[0037] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numerals in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this disclosure. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this disclosure as detailed in the appended claims.

[0038] The terminology used in this disclosure is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. The singular forms “a,” “the,” and “the” as used in this disclosure and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the term “and / or” as used herein refers to and includes any and all possible combinations of one or more of the associated listed items.

[0039] It should be understood that although the terms first, second, third, etc., may be used in this disclosure to describe various information, such information should not be limited to these terms. These terms are used only to distinguish information of the same type from one another. For example, without departing from the scope of this disclosure, first information may also be referred to as second information, and similarly, second information may also be referred to as first information. Depending on the context, the word "if" as used herein may be interpreted as "when," "when," or "in response to determination."

[0040] In the description of this application, it should be understood that the numerical labels before the steps do not indicate the order of the steps, but are only used to facilitate the description of this application and to distinguish each step, and therefore should not be construed as a limitation of this application.

[0041] The following terms are used in this document.

[0042] FOPLP (Fanout panel level package): Fanout panel level package;

[0043] PSPI (Photosensitive Polyimide): Photosensitive polyimide;

[0044] ABF (Ajinomoto Build-up Film): Ajinomoto's build-up material.

[0045] RDL (redistribution layer): redistribution layer;

[0046] PLP (panel level package): Panel-level packaging;

[0047] Molding compound: molding compound / molding material.

[0048] Example 1

[0049] See Figure 1 As shown, a packaging substrate includes a core insulating structure 2, a first encapsulating adhesive structure 1, and multiple wiring structures 3.

[0050] The core insulating structure 2 has a first height a1 and includes at least one first insulating layer. The first insulating layer is made of a photosensitive polyimide material, which has excellent heat resistance, insulation, and mechanical strength. The thickness of the first insulating layer is between 3 μm and 20 μm, a thickness range that ensures the core insulating structure 2 has sufficient mechanical strength while maintaining good flexibility. In a preferred embodiment, the thickness of the first insulating layer is 5 μm, a thickness that reduces the overall thickness of the packaging substrate while ensuring insulation performance. In another preferred embodiment, the thickness of the first insulating layer is 10 μm, a moderate thickness that achieves a good balance between insulation performance and mechanical strength. In yet another preferred embodiment, the thickness of the first insulating layer is 18 μm, a larger thickness that provides higher mechanical strength and better insulation performance.

[0051] The first encapsulation structure 1 covers the lower surface and sidewalls of the core insulating structure 2, serving to protect and support the core insulating structure 2. The first encapsulation structure 1 has a first width b1, which is greater than a first height a1. This design provides the packaging substrate with better stability and more wiring space. The first encapsulation structure 1 is made of molding compound material, which has good flowability and moldability, enabling it to completely encapsulate the core insulating structure 2 and form a stable structure. The thickness c1 of the first encapsulation structure 1 is greater than 25 μm, ensuring sufficient mechanical strength and protective capability.

[0052] The first width b1 refers to the vertical distance between the sidewall of the core insulating structure 2 and the outer edge of the first encapsulating structure 1, and the first width b1 is greater than 25 μm. In a preferred embodiment, the first width b1 is 30 μm, which provides sufficient protection without excessively increasing the overall size of the encapsulation substrate. In another preferred embodiment, the first width b1 is 50 μm, which provides better protection and higher mechanical strength. In yet another preferred embodiment, the first width b1 is 40 μm, a moderate width that achieves a good balance between protection and size control.

[0053] Multiple wiring structures 3 run through the core insulation structure 2 and the first encapsulation structure 1 to achieve electrical connection functions. A first connection pad 31 is provided on the lower surface of the wiring structure 3, which is used for electrical connection with external circuits or components. The wiring structure 3 can be made of copper, aluminum, or other conductive materials, possessing good conductivity and reliability. The design of the wiring structure 3 enables the packaging substrate to achieve complex circuit connection functions, meeting the needs of various electronic products.

[0054] This packaging substrate features a rationally designed structure and a simple manufacturing process, enabling high-density wiring and excellent electrical performance. The combined design of the core insulation structure 2 and the first encapsulation structure 1 provides excellent mechanical protection and electrical insulation, while the design of multiple wiring structures 3 and the first connecting pad 31 ensures good electrical connectivity. The overall structure is compact and suitable for various microelectronic packaging applications.

[0055] In this embodiment, by completely encapsulating the PSPI within other insulating materials with insulating, oxygen- and moisture-proof properties, preventing it from contacting the atmosphere, the RDL delamination problem caused by PSPI moisture absorption is effectively avoided, thus improving product reliability. The adoption of a packaging technology that eliminates the need for board flipping simplifies the process flow, making it simpler and reducing packaging costs compared to existing six-sided packaging processes that require board unpacking and flipping. Combining the advantage of PSPI's ability to create vias smaller than 10μm (suitable for fine-line trace layers) with the characteristics of other dielectric materials, the requirements of different layers are met. By rationally designing the encapsulation structure width (greater than 25μm), sufficient sidewall protection is ensured, effectively insulating and isolating moisture, preventing the encapsulation structure from cracking due to excessive thinness, further improving product reliability.

[0056] Example 2

[0057] See Figure 2 As shown, this embodiment provides a packaging substrate, including a core insulating structure 2, a multilayer insulating structure 8, a second encapsulating adhesive structure 9, and multiple wiring structures 3.

[0058] The core insulating structure 2 has a first height a1 and includes at least one first insulating layer. The first insulating layer is made of photosensitive polyimide material and has a thickness between 3 μm and 20 μm. In a preferred embodiment, the thickness of the first insulating layer may be 5 μm, 10 μm, or 15 μm.

[0059] A multilayer insulating structure 8 is disposed on the lower surface of the core insulating structure 2, and includes at least one second insulating layer. The second insulating layer is made of Ajinomoto additive material, and its thickness is between 15 μm and 50 μm. In a preferred embodiment, the thickness c2 of the second insulating layer can be 20 μm, 30 μm, or 45 μm. The upper surface area of ​​the multilayer insulating structure 8 is larger than the lower surface area of ​​the core insulating structure 2, forming an edge region that extends around the periphery of the core insulating structure 2.

[0060] The second encapsulation structure 9 covers the sidewalls of the core insulating structure 2 and the edge region of the upper surface of the multilayer insulating structure 8. The second encapsulation structure 9 is made of molding compound material with a thickness greater than 25 μm. In a preferred embodiment, the thickness of the second encapsulation structure 9 can be 30 μm, 40 μm, or 50 μm. The second encapsulation structure 9 has a second width b2, which is the vertical distance between the sidewall of the core insulating structure 2 and the outer edge of the second encapsulation structure 9, and the second width b2 is greater than 25 μm. In a preferred embodiment, the second width b2 can be 30 μm, 40 μm, or 50 μm. The second width b2 is greater than the first height a1. This design allows the second encapsulation structure 9 to effectively protect the sidewalls of the core insulating structure 2 and enhance the structural stability of the entire encapsulation substrate.

[0061] Multiple wiring structures 3 penetrate the core insulating structure 2 and the multilayer insulating structure 8, used to transmit electrical signals between different layers of the package substrate. A first connection pad 31 is provided on the lower surface of the wiring structure 3 for electrical connection with external circuits or components. The wiring structure 3 can be made of copper, aluminum, or other conductive materials, and electrical interconnection is achieved through through-holes formed in the core insulating structure 2 and the multilayer insulating structure 8.

[0062] In this packaging substrate structure, the design of the second encapsulating structure 9 effectively protects the sidewalls of the core insulating structure 2 and the edge areas of the upper surface of the multilayer insulating structure 8, preventing external environmental erosion and damage to the internal structure of the packaging substrate. Simultaneously, the design that the second width b2 is greater than the first height a1 enhances the overall structural strength of the packaging substrate, improving product reliability and lifespan.

[0063] The core insulation structure 2 uses photosensitive polyimide material, which has excellent insulation performance and thermal stability, and can maintain good electrical properties in high-temperature environments. The multilayer insulation structure 8 uses Ajinomoto additive material, which has good dielectric properties and mechanical strength, and can provide stable support and protection for the wiring structure 3.

[0064] The wiring structure 3 runs through the core insulation structure 2 and the multilayer insulation structure 8, realizing the electrical interconnection function inside the packaging substrate. The first connection pad 31 provides an interface for the connection between the packaging substrate and external circuits. This multilayer structure design not only improves the integration of the packaging substrate, but also enhances its electrical performance and mechanical strength.

[0065] Example 3

[0066] See Figure 1 As shown, in this embodiment, a semiconductor package is provided. The semiconductor package includes a chip 5, an interposer 6, multiple connectors 7, a molding compound 4, and the packaging substrate of Embodiment 1.

[0067] The packaging substrate includes a core insulating structure 2, a first encapsulating adhesive structure 1, and multiple wiring structures 3. The core insulating structure 2 has a first height a1. The core insulating structure 2 includes at least one first insulating layer. The first insulating layer is made of photosensitive polyimide material. The thickness of the first insulating layer is between 3μm and 20μm, and can be a specific value such as 5μm, 10μm, or 15μm.

[0068] The first encapsulating structure 1 covers the lower surface and sidewalls of the core insulating structure 2. The first encapsulating structure 1 has a first width b1, which is greater than a first height a1. The first width b1 is the vertical distance between the sidewall of the core insulating structure 2 and the outer edge of the first encapsulating structure 1, and is greater than 25 μm, for example, it can be 30 μm, 40 μm, or 50 μm. The first encapsulating structure 1 is made of molding compound material, and its thickness is greater than 25 μm, for example, it can be 30 μm, 35 μm, or 40 μm.

[0069] Multiple wiring structures 3 penetrate the core insulation structure 2 and the first encapsulation structure 1. A first connecting pad 31 is provided on the lower surface of the wiring structure 3, and a second connecting pad is provided on the upper surface of the wiring structure 3. The wiring structure 3 is formed of electroplated copper material, which has good conductivity and reliability.

[0070] Interposer 6 is located between the packaging substrate and the chip 5. Interposer 6 contains a vertical interconnect structure for electrical connection of the connector 7. Interposer 6 is made of a filler material that provides good insulation and mechanical support.

[0071] Connector 7 extends through the interposer layer 6, connecting the second connection pad and the chip 5 to form an electrical connection path. Connector 7 uses either bumps or solder balls. When using bumps, the diameter is between 250μm and 300μm, for example, 255μm, 275μm, or 295μm. When using solder balls, the diameter is between 250μm and 300μm. The width of the vertical interconnect structure is less than 100μm, for example, 80μm, 90μm, or 95μm. This design allows connector 7 to reliably connect the chip 5 and the package substrate while ensuring the integrity of signal transmission.

[0072] The molding compound 4 encapsulates the chip 5 and partially covers the upper surface of the packaging substrate. The molding compound 4 serves to protect the chip 5 and the interconnect structure, preventing damage to the chip 5 from the external environment.

[0073] In a preferred embodiment, the semiconductor package further includes at least one surface-mount passive component. The surface-mount passive component is disposed on the upper surface of the core insulating structure 2 and is electrically connected to the wiring structure 3. The surface-mount passive component can be a resistor, capacitor, or inductor, etc., used to implement specific circuit functions, such as filtering, decoupling, or impedance matching.

[0074] This semiconductor packaging structure, through the rational design of the packaging substrate, interposer 6, and connector 7, achieves reliable connection between chip 5 and external circuits, while ensuring the overall stability and electrical performance of the packaging structure. The special design of the core insulating structure 2 and the first encapsulating structure 1 in the packaging substrate improves the mechanical strength of the package and reduces the impact of thermal stress on the packaging structure. The precise dimensional control of the vertical interconnect structure in the interposer 6 and the connector 7 ensures efficient and reliable signal transmission.

[0075] Example 4

[0076] See Figure 2 As shown, in this embodiment, a semiconductor package is provided. The semiconductor package includes a chip 5, an interposer 6, multiple connectors 7, a molding compound 4, and a packaging substrate as described in Embodiment 2.

[0077] The packaging substrate includes a core insulating structure 2, a multilayer insulating structure 8, a second encapsulating adhesive structure 9, and multiple wiring structures 3. The core insulating structure 2 has a first height a1. The core insulating structure 2 includes at least one first insulating layer, which is made of photosensitive polyimide and has a thickness between 3 μm and 20 μm. The multilayer insulating structure 8 is disposed on the lower surface of the core insulating structure 2, and the upper surface area of ​​the multilayer insulating structure 8 is larger than the lower surface area of ​​the core insulating structure 2. The multilayer insulating structure 8 includes at least one second insulating layer, which is made of Ajinomoto additive material and has a thickness between 15 μm and 50 μm. The second encapsulating adhesive structure 9 covers the sidewalls of the core insulating structure 2 and the edge region of the upper surface of the multilayer insulating structure 8. The second encapsulating adhesive structure 9 has a second width b2, which is greater than the first height a1. The second width b2 is the vertical distance between the sidewalls of the core insulating structure 2 and the outer edge of the second encapsulating adhesive structure 9, and the second width b2 is greater than 25 μm. The second encapsulation structure 9 is made of molding compound, and its thickness is greater than 25 μm. Multiple wiring structures 3 penetrate the core insulation structure 2 and the multilayer insulation structure 8. A first connection pad 31 is provided on the lower surface of each wiring structure 3, and a second connection pad is provided on the upper surface of each wiring structure 3. The wiring structure 3 is made of electroplated copper.

[0078] Interposer 6 is located between the package substrate and chip 5. Vertical interconnect structures are embedded within interposer 6 for electrical connection of connectors 7. Interposer 6 is filled with adhesive. The width of the vertical interconnect structure is less than 100 μm. This design allows for higher density electrical connections within a limited space, improving the integration of the package.

[0079] Connector 7 extends through the interposer layer 6 and connects the second bonding pad to the chip 5. Connector 7 uses bumps or solder balls, with the bump diameter between 250μm and 300μm and the solder ball diameter between 250μm and 300μm. This size of connector 7 provides sufficient mechanical strength and electrical connectivity while maintaining package compactness.

[0080] The molding compound 4 encapsulates the chip 5 and partially covers the upper surface of the packaging substrate. The molding compound 4 protects the chip 5 and the connectors 7 from the influence of the external environment, improving the reliability and lifespan of the package.

[0081] In a preferred embodiment, the semiconductor package further includes at least one surface-mount passive component disposed on the upper surface of the core insulating structure 2 and electrically connected to the wiring structure 3. The surface-mount passive component may be a resistor, capacitor, or inductor, etc., used to implement specific circuit functions and improve the integration and performance of the package.

[0082] This semiconductor packaging structure improves the mechanical strength and reliability of the package through the combined design of the core insulating structure 2 and the multilayer insulating structure 8, as well as the protection of the second encapsulation structure 9. The vertical interconnect structure and connectors 7 within the interposer 6 enable electrical connections between the chip 5 and the packaging substrate, while the molding compound 4 provides overall protection. The integration of surface-mount passive components further enhances the functionality and integration of the package. The overall design achieves a high-density, high-reliability semiconductor packaging solution.

[0083] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A packaging substrate, characterized in that, include: The core insulation structure has the highest height. A first encapsulating structure is applied to the lower surface and sidewalls of the core insulating structure. The first encapsulating structure has a first width, which is greater than the first height. Multiple wiring structures extend through the core insulation structure and the first encapsulating adhesive structure, and a first connecting pad is provided on the lower surface of the wiring structure.

2. The packaging substrate according to claim 1, characterized in that, The core insulation structure includes at least one first insulation layer.

3. The packaging substrate according to claim 2, characterized in that, The first insulating layer is made of photosensitive polyimide.

4. The packaging substrate according to claim 2 or 3, characterized in that, The thickness of the first insulating layer is between 3 μm and 20 μm.

5. The packaging substrate according to claim 1, characterized in that, The first encapsulating material structure is a molding compound, and the thickness of the first encapsulating material structure is greater than 25 μm.

6. A packaging substrate, characterized in that, include: The core insulation structure has the highest height. A multilayer insulation structure is disposed on the lower surface of the core insulation structure, wherein the upper surface area of ​​the multilayer insulation structure is larger than the lower surface area of ​​the core insulation structure; The second encapsulation structure covers the sidewall of the core insulation structure and the edge region of the upper surface of the multilayer insulation structure. The second encapsulation structure has a second width, which is greater than the first height. Multiple wiring structures extend through the core insulation structure and the multilayer insulation structure, and a first connection pad is provided on the lower surface of the wiring structure.

7. The packaging substrate according to claim 6, characterized in that, The core insulation structure includes at least one first insulation layer, which is made of photosensitive polyimide and has a thickness between 3 μm and 20 μm.

8. The packaging substrate according to claim 6, characterized in that, The multilayer insulation structure includes at least one second insulation layer, the second insulation layer is made of Ajinomoto additive material, and the thickness of the second insulation layer is between 15μm and 50μm.

9. A semiconductor package, comprising: A chip, an interposer, multiple connectors, and a molding compound, characterized in that it further includes the packaging substrate according to any one of claims 1-5; The upper surface of the wiring structure is provided with a second connection pad; The interposer layer is located between the packaging substrate and the chip, and the interposer layer has a vertical interconnect structure inside, which is electrically connected to the connector. The connector extends through the interposer layer and connects the second connection pad to the chip. The molding compound encapsulates the chip and partially covers the upper surface of the packaging substrate.

10. A semiconductor package, comprising: A chip, an interposer, multiple connectors, and a molding compound, characterized in that it further includes the packaging substrate according to any one of claims 6-8; The upper surface of the wiring structure is provided with a second connection pad; The interposer layer is located between the packaging substrate and the chip, and the interposer layer has a vertical interconnect structure inside, which is electrically connected to the connector. The connector extends through the interposer layer and connects the second connection pad to the chip. The encapsulation structure encapsulates the chip and partially covers the upper surface of the packaging substrate.

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