A circuit for suppressing glitches in digital signals
By using a circuit composed of a delay chain, logic modules, and latches, the problem of glitches and noise in digital signals is solved, achieving efficient glitch suppression, suitable for low-power scenarios, and improving system reliability.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- HEFEI XINCAN TECHNOLOGY CO LTD
- Filing Date
- 2025-07-18
- Publication Date
- 2026-05-26
AI Technical Summary
The glitches and noise present in digital signals can severely affect the logic of digital circuits, and existing technologies are unable to effectively suppress them.
A circuit consisting of a delay chain, AND logic module, OR logic module, and latches can filter out glitches through delay and logic transformation, suppressing high-level and low-level glitches without the need for a clock.
It effectively filters out high and low level glitches on digital signals, making it suitable for low-power scenarios and improving the system's functional reliability and stability.
Smart Images
Figure CN224289766U_ABST
Abstract
Description
Technical Field
[0001] This utility model relates to the field of electronic circuits, and in particular to a circuit for suppressing glitches in digital signals. Background Technology
[0002] In digital circuits, in addition to the required signal, transmitted signals are sometimes superimposed with unwanted noise, manifesting as spikes or short, narrow pulses coupled to the transmitted signal. These noises can be either high-level or low-level. This is a common but significant phenomenon, and its presence can severely impact the logic of digital circuits. For example, when noise appears on the clock signal, it can cause flip-flop sampling errors or timing violations; when noise appears on the interrupt signal, it can cause incorrect processor responses, affecting system functionality and reliability; and when noise appears on the trigger signal, it can cause false triggering. Therefore, it is necessary to perform noise filtering on these critical signals. Utility Model Content
[0003] The purpose of this invention is to overcome the shortcomings of the prior art and provide a circuit for suppressing glitches in digital signals, thus solving the deficiencies of the prior art.
[0004] The purpose of this utility model is achieved through the following technical solution: a circuit for suppressing glitches on digital signals, the circuit including a delay chain, an AND logic module, an OR logic module and a latch;
[0005] The input signals are respectively connected to the input terminals of the delay unit, the AND logic module, and the OR logic module, while the output terminal of the delay unit is connected to the input terminals of the AND logic module and the OR logic module; the output terminal of the AND logic module is connected to one input terminal of the latch, the output terminal of the OR logic module is connected to the other input terminal of the latch, and the output terminal of the latch outputs a signal.
[0006] The delay chain consists of multiple delay units cascaded in sequence, and the output of each delay unit is also connected to the input of the AND logic module and the OR logic module.
[0007] The AND logic module includes one or more AND logic blocks; when the AND logic module includes one AND logic block, the input signal and the output of the delay chain are connected to the input of the AND logic block, and the output of the AND logic block is connected to the input of the latch.
[0008] When an AND logic block includes multiple AND logic blocks, one input terminal of the first AND logic block is connected to the input signal, and the other input terminal is connected to the output terminal of the first delay unit. The output terminal of the last AND logic block is connected to one input terminal of the latch. The two input terminals of all other AND logic blocks are respectively connected to the output terminal of the previous AND logic block and the output terminal of the corresponding delay unit.
[0009] The OR logic module includes multiple OR logic blocks; when the OR logic module includes one OR logic block, the input signal and the output of the delay chain are connected to the input of the OR logic block, and the output of the OR logic block is connected to the input of the latch.
[0010] When an OR logic block includes multiple OR logic blocks, one input terminal of the first OR logic block is connected to the input signal, and the other input terminal is connected to the output terminal of the first delay unit. The output terminal of the last OR logic block is connected to the other input terminal of the latch. The two input terminals of all other OR logic blocks are respectively connected to the output terminal of the previous OR logic block and the output terminal of the corresponding delay unit.
[0011] When the latch is an SR latch, the system further includes an inverter. The output of the OR logic module is connected to the input of the inverter, the output of the inverter is connected to the R input of the SR latch, and the output of the AND logic module is connected to the S input of the SR latch.
[0012] This invention has the following advantages: a circuit for suppressing glitches on digital signals, implemented based on combinational logic gates and latches, can filter out high-level and low-level glitches on digital signals without a clock. It is particularly suitable for low-power scenarios where a clock is not required. Attached Figure Description
[0013] Figure 1 This is a schematic diagram of the structure of this utility model;
[0014] Figure 2 This is a timing diagram of the input signal IN of this utility model when there are no glitches;
[0015] Figure 3 This is a timing diagram of the input signal IN of this utility model when high and low level glitches are superimposed;
[0016] Figure 4 This is a timing diagram of the input signal IN of this utility model when two high and low level glitches are superimposed;
[0017] Figure 5 This is a schematic diagram of another embodiment of the present utility model;
[0018] Figure 6 This is a timing diagram of another embodiment of the present invention. Detailed Implementation
[0019] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of the embodiments. The components of the embodiments of this application described and shown in the accompanying drawings can be arranged and designed in various different configurations. Therefore, the detailed description of the embodiments of this application provided below with reference to the accompanying drawings is not intended to limit the scope of protection of the claimed application, but merely represents selected embodiments of this application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application. The present invention will be further described below with reference to the accompanying drawings.
[0020] This invention relates to a circuit for suppressing glitches in digital signals. This glitch-filtering circuit is implemented based on combinational logic gates and latches, and can filter out both high-level and low-level glitches in digital signals without a clock. It is particularly suitable for low-power scenarios where a clock is not required. A high-level glitch refers to a high-level pulse superimposed during the low-level period of the desired transmitted signal, with a pulse width less than or equal to the defined duration of the glitch. A low-level glitch refers to a low-level pulse superimposed during the high-level period of the desired transmitted signal, with a pulse width less than or equal to the defined duration of the glitch.
[0021] One implementation method is as follows Figure 1 As shown, it includes a delay chain, AND logic blocks, OR logic blocks, inverters, and latches. The delay chain consists of several cascaded delay units, meaning the input of the next delay unit is connected to the output of the previous delay unit. The function of the delay chain is to delay the input signal for which glitches need to be filtered. The input of the delay chain is the digital signal for which glitches need to be filtered, and the output is the output of each delay unit.
[0022] A delay unit is a digital logic device or circuit whose output equals its input, with a certain delay relative to the input. Since the delay of each delay unit is typically small, delay chains utilize multiple delay units. Assuming the delay of each delay unit in the delay chain to its input signal is denoted by Dt, then the total delay of a delay chain consisting of n cascaded delay units to its input signal is DT = n*Dt. The total delay of the delay chain is adjusted by changing the number of delay units. The total delay of the delay chain should be greater than the defined duration of the glitches and less than the duration of the required transmitted signal, with a certain margin.
[0023] Furthermore, the inputs to the AND logic block are the original input signal for which glitches need to be filtered and the output signal of each delay unit in the delay chain. The AND logic block has only one output, which is the result of ANDing all its input signals. The AND logic block is used to detect the moment when both the original input signal and the output signal of each delay unit in the delay chain are high. By performing different logical transformations on the implementation logic of this logic block, there are various forms and topologies for implementing this logic block.
[0024] Furthermore, the input to the OR logic block is the original input signal for which glitches need to be filtered and the output signal of each delay unit in the delay chain. The OR logic block has only one output, which is the result of ORing all its input signals. The OR logic block is used to detect the moment when both the original input signal and the output signal of each delay unit in the delay chain are low. By performing different logical transformations on the implementation logic of this logic block, there are various forms and topologies for implementing this logic block.
[0025] Furthermore, a latch is a level-sensitive device or circuit. Various types of latches exist to meet the requirements of this glitch filtering circuit, the simplest and most common being the SR latch. When both inputs S and R are zero, the latch is in a static state, and its Q output remains unchanged. When S is set to 1 and R is 0, the Q output is forced to 1. Conversely, when R is set to 1 and S is 0, the Q output becomes 0. When both S and R are 1, Q is forced to 0; this input mode is not allowed.
[0026] The circuit outputs a high level when the input signal and the outputs of all delay units are high. The circuit outputs a low level when the input signal and the delay outputs of all delay units are low. Otherwise, the circuit output remains unchanged.
[0027] Whether an inverter is needed in this circuit depends on the latch. In the glitch filtering circuit, the S input of the SR latch is active high, so the output of the OR logic block does not need to be inverted by an inverter and can be directly connected to the S input of the latch. The R input of the SR latch is active high, so the output of the OR logic block needs to be inverted by an inverter before being connected to the R input of the latch. The Q output of the latch is the final output of this glitch filtering circuit.
[0028] Figures 2-4These are the timing waveforms of the output OUT after different input signals IN pass through the glitch filtering circuit. After the input signal IN passes through a delay chain with n delay units, the output waveforms of each delay unit are IN_d1, IN_d2, ..., IN_dn, respectively. The delay of each delay unit is Dt, and the total delay is DT. The AND(S) signal waveform is the output of the AND logic block, connected to the S input of the SR latch. The OR signal waveform is the output of the OR logic block, and the NOR(R) signal waveform is the output of the OR signal after being inverted by an inverter, connected to the R input of the SR latch. The OUT signal waveform is the output waveform of the SR latch, that is, the final output result of the IN input after passing through the glitch filtering circuit.
[0029] When the input signal IN and the outputs of all delay units IN_d1, IN_d2, ..., IN_dn are all high, the OUT output is high. When the input signal IN and the delayed outputs of all delay units IN_d1, IN_d2, ..., IN_dn are all low, the OUT output is low. Otherwise, the OUT output remains unchanged.
[0030] Figure 2 The input signal IN has high and low level variations, but no coupling glitches. After the input signal IN passes through this glitch filter circuit, as can be seen from the timing diagram, the output signal OUT is the input signal IN after a delay of DT.
[0031] Figure 3 This is a timing diagram showing the input signal IN having both high-level and low-level glitches coupled to it, after passing through a glitch filtering circuit. The delay chain simultaneously delays both the desired signal and the glitches. After passing through the AND logic block, the high-level glitches are completely filtered out, as shown in the AND(S) waveform. After passing through the OR logic block, the low-level glitches are completely filtered out, as shown in the OR waveform. Finally, the latch output signal OUT no longer contains any high or low-level glitches; that is, the glitch filtering circuit has completely removed the glitches from the input signal.
[0032] Figure 4 The input signal IN contains two high-level glitches. There exists a situation where, after the delay chain, high-level glitches 1 on IN_dn coincide with high-level glitches 2 on IN. After passing through the AND logic block, the high-level glitches are completely filtered out, as shown in the AND(S) waveform. Finally, the output waveform OUT shows that the glitch filtering circuit completely removes the two high-level glitches from the IN signal.
[0033] Another embodiment of this utility model is as follows: Figure 5 As shown, the AND logic block in its glitch filtering circuit only performs an AND operation on the input signal IN and the final output IN_dn of the delay chain, and the OR logic block only performs an OR operation on the input signal IN and the final output IN_dn of the delay chain. Figure 5 The timing diagram corresponding to the glitch filtering circuit shown is as follows: Figure 6 As shown, assume that the waveform of its input signal IN is similar to... Figure 4 The same applies. Similarly, after the delay chain, the high-level glitches 1 and 2 of IN_dn coincide. After the AND logic block, the high-level glitches are not completely filtered out, as shown in the AND(S) waveform. Therefore, it can be seen from the final OUT output waveform that there is still one high-level glitch during the low-level period of the signal that has not been filtered out, that is, the input signal IN passes through... Figure 5 Even with the glitch filtering circuit shown, high-level glitches on the IN signal are not completely filtered out. Similarly, the same problem persists with low-level glitches on the IN input signal. However, the glitch filtering circuit of this invention does not have this issue. Figure 5 The problems with the circuit shown demonstrate that the burr filter circuit of this invention can better handle more complex application scenarios.
[0034] The above description is merely a preferred embodiment of this utility model. It should be understood that this utility model is not limited to the form disclosed herein and should not be construed as excluding other embodiments. It can be used in various other combinations, modifications, and improvements, and can be altered within the scope of the concept described herein through the above teachings or related technologies or knowledge. Modifications and variations made by those skilled in the art that do not depart from the spirit and scope of this utility model should be protected within the scope of the appended claims.
Claims
1. A circuit for suppressing glitches in digital signals, characterized in that: The circuit includes a delay chain, an AND logic module, an OR logic module, and a latch; The input signals are respectively connected to the input terminals of the delay unit, the AND logic module, and the OR logic module, while the output terminal of the delay unit is connected to the input terminals of the AND logic module and the OR logic module; the output terminal of the AND logic module is connected to one input terminal of the latch, the output terminal of the OR logic module is connected to the other input terminal of the latch, and the output terminal of the latch outputs a signal.
2. The circuit for suppressing glitches in digital signals according to claim 1, characterized in that: The delay chain consists of multiple delay units cascaded in sequence, and the output of each delay unit is also connected to the input of the AND logic module and the OR logic module.
3. The circuit for suppressing glitches in digital signals according to claim 2, characterized in that: The AND logic module includes one or more AND logic blocks; when the AND logic module includes one AND logic block, the input signal and the output of the delay chain are connected to the input of the AND logic block, and the output of the AND logic block is connected to the input of the latch. When an AND logic block includes multiple AND logic blocks, one input terminal of the first AND logic block is connected to the input signal, and the other input terminal is connected to the output terminal of the first delay unit. The output terminal of the last AND logic block is connected to one input terminal of the latch. The two input terminals of all other AND logic blocks are respectively connected to the output terminal of the previous AND logic block and the output terminal of the corresponding delay unit.
4. The circuit for suppressing glitches in digital signals according to claim 2, characterized in that: The OR logic module includes multiple OR logic blocks; when the OR logic module includes one OR logic block, the input signal and the output of the delay chain are connected to the input of the OR logic block, and the output of the OR logic block is connected to the input of the latch. When an OR logic block includes multiple OR logic blocks, one input terminal of the first OR logic block is connected to the input signal, and the other input terminal is connected to the output terminal of the first delay unit. The output terminal of the last OR logic block is connected to the other input terminal of the latch. The two input terminals of all other OR logic blocks are respectively connected to the output terminal of the previous OR logic block and the output terminal of the corresponding delay unit.
5. A circuit for suppressing glitches in digital signals according to any one of claims 1-4, characterized in that: When the latch is an SR latch, the circuit further includes an inverter. The output of the OR logic module is connected to the input of the inverter, the output of the inverter is connected to the R input of the SR latch, and the output of the AND logic module is connected to the S input of the SR latch.