Gate drive circuit

Abstract

The application provides a gate driving circuit, and belongs to the technical field of display. A pull-up control module outputs an n-level control signal according to an n-4-level trigger signal. A first end of a first transistor obtains a clock signal, and a second end of the first transistor obtains a first local clock signal. The n-4-level trigger signal is opposite to the clock signal CLK. A first end of a second transistor is connected with the pull-up control module and obtains the n-level control signal. A third end of the first transistor outputs a first reverse signal, and a third end of the second transistor obtains a first reference low voltage. Through the first transistor and the second transistor, the potential of the n-level control signal is opposite to the potential of the first reverse signal under the regulation of the clock signal, the first local clock signal and the n-level control signal, the function of the inverter module is realized, the number of transistors is reduced, and the problem that the frame of the display panel is large due to the large number of transistors in the inverter module of the traditional circuit is solved.

Description

Technical Field

[0001] This application belongs to the field of display technology, and in particular relates to a gate driving circuit. Background Technology

[0002] The Gate Driver on Array (GOA) circuit integrates the gate driver circuit of the display panel onto the glass substrate, forming a scanning driver for the display panel. The GOA driving circuit significantly reduces manufacturing costs and allows for a reduction in the bezel size of the display panel.

[0003] However, the inverter module of traditional circuits has a large number of thin-film transistors (TFTs), which results in a large bezel on the display panel, making it impossible to meet the requirements for narrow bezels. Utility Model Content

[0004] The purpose of this application is to provide a gate driving circuit that aims to solve the problem of large bezels on the display panel caused by an excessive number of TFTs in the inverter module of traditional circuits.

[0005] This application provides a gate driving circuit, including a multi-stage sub-driving circuit connected in cascades, wherein the nth stage sub-driving circuit includes:

[0006] The pull-up control module is used to output the nth level control signal based on the n-4th level trigger signal of the n-4th level sub-drive circuit; where n is an integer greater than 4.

[0007] A first transistor, wherein a first terminal of the first transistor is used to acquire a clock signal, and a second terminal of the first transistor is used to acquire a first local clock signal; wherein the (n-4)th stage trigger signal is opposite to the clock signal;

[0008] The second transistor has its first terminal connected to the pull-up control module for acquiring the nth level control signal, and its second terminal connected to the third terminal of the first transistor for outputting a first inverted signal. The third terminal of the second transistor is used to acquire a first reference low potential.

[0009] In one embodiment, the nth-level sub-driving circuit further includes:

[0010] A third transistor, wherein a first terminal of the third transistor is used to acquire the clock signal, and a second terminal of the third transistor is used to acquire a second local clock signal;

[0011] The fourth transistor has its first terminal connected to the pull-up control module for acquiring the nth level control signal, its second terminal connected to the third terminal of the third transistor for outputting a second inverted signal, and its third terminal for acquiring the first reference low potential.

[0012] The second local clock signal is opposite to the first local clock signal.

[0013] In one embodiment, the nth-level sub-driving circuit further includes:

[0014] A pull-down sustaining module is connected to the pull-up control module. The pull-down sustaining module is also connected to the third terminal of the first transistor or the third terminal of the third transistor. The pull-down sustaining module is used to pull down the potential of the nth level control signal and maintain it at the first reference low potential according to the first reverse signal or the second reverse signal.

[0015] In one embodiment, the nth-level sub-driving circuit further includes:

[0016] A pull-up module, connected to the pull-up control module, is used to output an nth-stage gate drive signal and an nth-stage trigger signal according to the nth-stage control signal and the clock signal;

[0017] The pull-down sustaining module is connected to the pull-up module and is used to pull down and maintain the potential of the nth stage gate drive signal to the second reference low potential according to the second reverse signal or the first reverse signal, and to pull down and maintain the potential of the nth stage trigger signal to the first reference low potential.

[0018] In one embodiment, the pull-down sustaining module includes:

[0019] The fifth transistor has a first terminal connected to the third terminal of the first transistor for acquiring the first inverted signal, a second terminal connected to the pull-up control module for acquiring the nth level control signal, and a third terminal for acquiring the first reference low potential.

[0020] The sixth transistor has a first terminal connected to the third terminal of the first transistor for acquiring the first inverted signal, a second terminal connected to the pull-up module for acquiring the nth stage trigger signal, and a third terminal for acquiring the first reference low potential.

[0021] The seventh transistor has a first terminal connected to the third terminal of the first transistor for acquiring the first inverted signal, a second terminal connected to the pull-up module for acquiring the nth gate drive signal, and a third terminal for acquiring the second reference low potential.

[0022] In one embodiment, the pull-down sustaining module includes:

[0023] The eighth transistor has its first terminal connected to the third terminal of the third transistor for acquiring the second inverted signal, its second terminal connected to the pull-up control module for acquiring the nth level control signal, and its third terminal for acquiring the first reference low potential.

[0024] The ninth transistor has its first terminal connected to the third terminal of the third transistor for acquiring the second inverted signal, its second terminal connected to the pull-up module for acquiring the nth stage trigger signal, and its third terminal for acquiring the first reference low potential.

[0025] The tenth transistor has its first terminal connected to the third terminal of the third transistor for acquiring the second inverted signal, its second terminal connected to the pull-up module for acquiring the nth gate drive signal, and its third terminal for acquiring the second reference low potential.

[0026] In one embodiment, the pull-up module includes:

[0027] The eleventh transistor has its first terminal connected to the pull-up control module for acquiring the nth level control signal, its second terminal for acquiring the clock signal, and its third terminal for outputting the nth level trigger signal.

[0028] The twelfth transistor has its first terminal connected to the pull-up control module for acquiring the nth stage control signal, its second terminal for acquiring the clock signal, and its third terminal for outputting the nth stage gate drive signal.

[0029] A capacitor, one end of which is connected to the first terminal of the twelfth transistor, and the other end of which is connected to the third terminal of the twelfth transistor.

[0030] In one embodiment, the pull-up control module includes:

[0031] The thirteenth transistor has its first and second terminals connected to acquire the (n-4)th stage trigger signal. The third terminal of the thirteenth transistor is connected to the first terminals of the eleventh transistor and the twelfth transistor to output the nth stage control signal.

[0032] In one embodiment, the nth-level sub-driving circuit further includes:

[0033] The fourteenth transistor has a first terminal for acquiring a reset signal, a second terminal connected to the third terminal of the thirteenth transistor for acquiring the nth stage control signal, and a third terminal for acquiring the first reference low potential.

[0034] In one embodiment, the nth-level sub-driving circuit further includes:

[0035] The fifteenth transistor has a first terminal for acquiring the (n+5)th stage trigger signal of the (n+5)th stage sub-driving circuit, a second terminal for connecting to the first terminal of the twelfth transistor for acquiring the nth stage control signal, and a third terminal for acquiring the first reference low potential.

[0036] The sixteenth transistor has a first terminal for acquiring the (n+4)th stage gate drive signal of the (n+4)th stage sub-drive circuit, a second terminal for connecting to the third terminal of the twelfth transistor for acquiring the nth stage gate drive signal, and a third terminal for acquiring the second reference low potential.

[0037] The beneficial effects of this utility model embodiment compared with the prior art are:

[0038] Multi-stage sub-driver circuits are cascaded to form a gate driver circuit. The (n-4)th stage trigger signal STn-4 of the (n-4)th stage sub-driver circuit is input to the pull-up control module as the start signal of the nth stage sub-driver circuit. The pull-up control module outputs the nth stage control signal Qn based on the (n-4)th stage trigger signal STn-4. The nth stage control signal Qn is used to control the output of the nth stage gate driver signal Gn to achieve functions such as progressive scan driving of pixels.

[0039] The clock signal CLK and the first local clock signal LC1 serve as the input signals to the first transistor, and the nth-stage control signal Qn serves as the input signal to the second transistor. The second terminal of the second transistor is connected to the third terminal of the first transistor to output the first inverted signal Kn.

[0040] The (n-4)th stage trigger signal STn-4 is opposite to the clock signal CLK. This can be understood as STn-4 being high while CLK is low. When the pull-up control module charges the nth stage control signal Qn at the high level of STn-4, Qn becomes high. At this time, the clock signal CLK at the first terminal of the first transistor is low, causing the first transistor to turn off (or not conduct). Consequently, the first terminal of the second transistor receives the nth stage control signal Qn at a high level, turning the second transistor on (or conducting), pulling the potential of the first inverting signal Kn low to the first reference low level VSSQ. Thus, the potential of the nth stage control signal Qn is opposite to the potential of the first inverting signal Kn. The first and second transistors together realize the function of the inverter module.

[0041] When the first terminal of the second transistor receives a low level input to the nth-stage control signal Qn, the second transistor is turned off, preventing the potential of the first inverting signal Kn from being pulled down to the first reference low potential VSSQ. Therefore, although the first transistor alternately turns on and off with the clock signal CLK, the potential of the first inverting signal Kn will not be pulled down to the first reference low potential VSSQ, maintaining a potential opposite to that of the nth-stage control signal Qn. This allows the inverter module formed by the first and second transistors to operate normally, fulfilling its function and ensuring the stable operation of the gate drive circuit.

[0042] Therefore, through the first and second transistors in the gate driving circuit provided in this application, under the control of the clock signal CLK, the first local clock signal LC1, and the nth-level control signal Qn, the potential of the nth-level control signal Qn can be made opposite to the potential of the first inverting signal Kn, thus realizing the function of the inverter module. Therefore, the gate driving circuit provided in this application can realize the function of the inverter module through only two transistors, the first and second transistors, reducing the number of transistors and thus enabling a smaller bezel on the display panel, meeting the requirement for a narrow bezel, and solving the problem of a large bezel on the display panel caused by the excessive number of TFTs in the inverter module of traditional circuits. Attached Figure Description

[0043] To more clearly illustrate the technical solutions in the embodiments of this application, the drawings used in the description of the embodiments or exemplary technologies will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0044] Figure 1The circuit structure diagrams of the gate drive circuits in some embodiments provided in this application are shown.

[0045] Figure 2 The diagram shows the specific circuit connection structure of the pull-down sustaining module in some embodiments provided in this application.

[0046] Figure 3 The diagram shows the specific circuit connection structure of the pull-up control module and the pull-up module in some embodiments provided in this application.

[0047] Figure 4 The following are schematic diagrams of signal input waveforms in some embodiments provided in this application.

[0048] Figure 5 The waveform diagrams of the nth level control signal and the first inverse signal in some embodiments provided in this application are shown. Detailed Implementation

[0049] To make the technical problems, technical solutions, and beneficial effects to be solved by this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and are not intended to limit the scope of this application.

[0050] It should be noted that when a component is referred to as being "fixed to" or "set on" another component, it can be directly on or indirectly on that other component. When a component is referred to as being "connected to" another component, it can be directly connected to or indirectly connected to that other component.

[0051] It should be understood that the terms "length", "width", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.

[0052] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined with "first" or "second" may explicitly or implicitly include one or more of that feature. Additionally, in the embodiments of this application, the terms "first" and "second" are used to distinguish identical or similar items that have substantially the same function and effect. Those skilled in the art will understand that the terms "first" and "second" do not limit the quantity or order of execution, and that "first" and "second" do not necessarily imply difference.

[0053] In the description of this application, unless otherwise stated, " / " indicates that the objects before and after it are in an "or" relationship. For example, A / B can mean A or B. "And / or" in this application is merely a description of the relationship between the related objects, indicating that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, and B alone, where A and B can be singular or plural. Furthermore, in the description of this application, unless otherwise stated, "multiple" means two or more. "At least one of the following" or similar expressions refer to any combination of these items, including any combination of single or plural items. For example, at least one of a, b, or c can represent: a, b, c, ab, ac, bc, or abc, where a, b, and c can be single or multiple.

[0054] Please see Figure 1 This application provides a gate driving circuit. The gate driving circuit includes cascaded multi-stage sub-driving circuits. The nth stage sub-driving circuit includes a pull-up control module 10, a first transistor 310, and a second transistor 320. The pull-up control module 10 is used to output an nth stage control signal Qn according to the (n-4)th stage trigger signal STn-4 of the (n-4)th stage sub-driving circuit; where n is an integer greater than 4.

[0055] The first terminal of the first transistor 310 is used to acquire the clock signal CLK, and the second terminal of the first transistor 310 is used to acquire the first local clock signal LC1. The (n-4)th stage trigger signal STn-4 is opposite to the clock signal CLK. The first terminal of the second transistor 320 is connected to the pull-up control module 10 and is used to acquire the nth stage control signal Qn. The second terminal of the second transistor 320 is connected to the third terminal of the first transistor 310 and is used to output the first inverted signal Kn. The third terminal of the second transistor 320 is used to acquire the first reference low potential VSSQ.

[0056] In this embodiment, multi-stage sub-driving circuits are cascaded to form a gate driving circuit. The (n-4)th stage trigger signal STn-4 of the (n-4)th stage sub-driving circuit is input to the pull-up control module 10 as the start signal of the nth stage sub-driving circuit. The pull-up control module 10 outputs the nth stage control signal Qn according to the (n-4)th stage trigger signal STn-4. The nth stage control signal Qn is used to control the output of the nth stage gate driving signal Gn to realize functions such as progressive scan driving of pixels.

[0057] The clock signal CLK and the first local clock signal LC1 serve as input signals to the first transistor 310, and the nth-stage control signal Qn serves as input signal to the second transistor 320. The second terminal of the second transistor 320 is connected to the third terminal of the first transistor 310 to output the first inverted signal Kn.

[0058] The (n-4)th stage trigger signal STn-4 is opposite to the clock signal CLK. This can be understood as STn-4 being high while CLK is low. When the pull-up control module 10 charges the nth stage control signal Qn at the high potential of STn-4, it causes Qn to become high. At this time, the clock signal CLK at the first terminal of the first transistor 310 is low, causing the first transistor 310 to turn off (or not conduct). Then, the first terminal of the second transistor 320 receives the nth stage control signal Qn at a high potential, causing the second transistor 320 to turn on (or conduct), pulling the potential of the first inverting signal Kn down to the first reference low potential VSSQ. Thus, the potential of the nth stage control signal Qn is opposite to the potential of the first inverting signal Kn. The first transistor 310 and the second transistor 320 achieve the function of the inverter module.

[0059] When the first terminal of the second transistor 320 receives a low-level control signal Qn, the second transistor 320 is turned off, preventing the potential of the first inverted signal Kn from being pulled down to the first reference low potential VSSQ. Consequently, although the first transistor 310 alternately turns on and off with the clock signal CLK, the potential of the first inverted signal Kn will not be pulled down to the first reference low potential VSSQ, maintaining a potential opposite to that of the nth-level control signal Qn. This allows the inverter module formed by the first transistor 310 and the second transistor 320 to operate normally, fulfilling the inverter module's function and ensuring the stable operation of the gate drive circuit.

[0060] Therefore, through the gate driving circuit provided in this application, the first transistor 310 and the second transistor 320, under the control of the clock signal CLK, the first local clock signal LC1, and the nth-level control signal Qn, can make the potential of the nth-level control signal Qn opposite to the potential of the first inverting signal Kn, thus realizing the function of the inverter module. Therefore, the gate driving circuit provided in this application can realize the function of the inverter module through only two transistors, the first transistor 310 and the second transistor 320, reducing the number of transistors and thus enabling a smaller bezel on the display panel, meeting the requirement for a narrow bezel, and solving the problem of a large bezel on the display panel caused by the excessive number of TFTs in the inverter module of traditional circuits.

[0061] In one embodiment, the nth-level sub-driving circuit further includes a third transistor 330 and a fourth transistor 340. The first terminal of the third transistor 330 is used to acquire the clock signal CLK, and the second terminal of the third transistor 330 is used to acquire the second local clock signal LC2.

[0062] The first terminal of the fourth transistor 340 is connected to the pull-up control module 10 to obtain the nth-level control signal Qn. The second terminal of the fourth transistor 340 is connected to the third terminal of the third transistor 330 to output the second inverted signal Pn. The third terminal of the fourth transistor 340 is used to obtain the first reference low potential VSSQ. The second local clock signal LC2 is opposite to the first local clock signal LC1.

[0063] In this embodiment, the first inverter module formed by the third transistor 330 and the fourth transistor 340, and the second inverter module formed by the first transistor 310 and the second transistor 320, are two symmetrical inverter modules, both capable of signal inversion or level conversion. The working principle of the third transistor 330 and the fourth transistor 340 is the same as that of the second inverter module.

[0064] When the pull-up control module 10 charges the nth-stage control signal Qn at a high potential in the (n-4)th-stage trigger signal STn-4, it causes the nth-stage control signal Qn to become high. At this time, the clock signal CLK at the first terminal of the third transistor 330 is at a low potential, causing the third transistor 330 to not conduct. Subsequently, the first terminal of the fourth transistor 340 receives the nth-stage control signal Qn at a high potential, causing the fourth transistor 340 to conduct and pull the potential of the second inverting signal Pn down to the first reference low potential VSSQ. Thus, the potential of the nth-stage control signal Qn is opposite to the potential of the second inverting signal Pn. The third transistor 330 and the fourth transistor 340 realize the function of the inverter module.

[0065] When the first terminal of the fourth transistor 340 receives a low-level input to the nth-stage control signal Qn, the fourth transistor 340 is not turned on, preventing the second inverted signal Pn from being pulled down to the first reference low-level VSSQ. Consequently, although the third transistor 330 alternately turns on and off with the clock signal CLK, the second inverted signal Pn is not pulled down to the first reference low-level VSSQ, maintaining a potential opposite to the nth-stage control signal Qn. This allows the inverter module formed by the third transistor 330 and the fourth transistor 340 to operate normally, fulfilling the inverter module's function and ensuring the stable operation of the gate drive circuit.

[0066] Therefore, through the gate driving circuit provided in this application, the third transistor 330 and the fourth transistor 340, under the control of the clock signal CLK, the second local clock signal LC2, and the nth-stage control signal Qn, can make the potential of the nth-stage control signal Qn opposite to the potential of the second inverting signal Pn, thus realizing the function of the inverter module. Therefore, the gate driving circuit provided in this application can also realize the function of the inverter module through just two transistors, the third transistor 330 and the fourth transistor 340, reducing the number of transistors and thus enabling a smaller bezel on the display panel, meeting the requirement for a narrow bezel, and solving the problem of a large bezel on the display panel caused by the excessive number of TFTs in the inverter module of traditional circuits.

[0067] Furthermore, the second local clock signal LC2 is opposite to the first local clock signal LC1. This can be understood as follows: when the first local clock signal LC1 is high, the second local clock signal LC2 is low; when the first local clock signal LC1 is low, the second local clock signal LC2 is high. By having the first local clock signal LC1 and the second local clock signal LC2 opposite, the first transistor 310 and the third transistor 330 can alternately output the first inverted signal Kn or the second inverted signal Pn to drive the pull-down sustaining module 40, thus achieving the pull-down sustaining function. Therefore, by having the first local clock signal LC1 and the second local clock signal LC2 opposite, the first inverter module formed by the third transistor 330 and the fourth transistor 340, and the second inverter module formed by the first transistor 310 and the second transistor 320, can operate alternately, avoiding the forward bias drift problem caused by the transistors always being in the on state.

[0068] In one embodiment, the nth-stage sub-driving circuit further includes a pull-down sustaining module 40. The pull-down sustaining module 40 is connected to the pull-up control module 10. The pull-down sustaining module 40 is also connected to the third terminal of the first transistor 310 or the third terminal of the third transistor 330. The pull-down sustaining module 40 is used to pull down and maintain the potential of the nth-stage control signal Qn to a first reference low potential VSSQ according to a first inverted signal Kn or a second inverted signal Pn.

[0069] In this embodiment, the pull-down sustaining module 40 is connected to the pull-up control module 10 and is used to acquire the nth-level control signal Qn output by the pull-up control module 10. The pull-down sustaining module 40 is also connected to the third terminal of the first transistor 310 or the third terminal of the third transistor 330 and is used to acquire the first inverted signal Kn or the second inverted signal Pn. Under the control of the first inverted signal Kn or the second inverted signal Pn, the transistors in the pull-down sustaining module 40 can be alternately turned on to realize the pull-down function, pull down the potential of the nth-level control signal Qn and maintain it at the first reference low potential VSSQ, avoiding the forward bias drift problem caused by some transistors being in a continuous on state, and ensuring the stability of the pull-down sustaining module 40.

[0070] Furthermore, the pull-down maintenance module 40 can pull down the nth-level control signal Qn to the first reference low potential VSSQ, so that the nth-level control signal Qn can be maintained at the first reference low potential VSSQ, preventing low potential fluctuations of the nth-level control signal Qn and improving the stability and reliability of the nth-level control signal Qn.

[0071] In one embodiment, the nth-stage sub-driving circuit further includes a pull-up module 20. The pull-up module 20 is connected to the pull-up control module 10 and is used to output the nth-stage gate drive signal Gn and the nth-stage trigger signal STn according to the nth-stage control signal Qn and the clock signal CLK.

[0072] The pull-down sustaining module 40 is connected to the pull-up module 20 and is used to pull down and maintain the potential of the nth stage gate drive signal Gn to the second reference low potential VSSG according to the second reverse signal Pn or the first reverse signal Kn, and to pull down and maintain the potential of the nth stage trigger signal STn to the first reference low potential VSSQ.

[0073] In this embodiment, the pull-up control module 10 outputs the nth-level control signal Qn of the control node according to the (n-4)th-level trigger signal STn-4, thereby activating the pull-up module 20. Then, the pull-up module 20 outputs the nth-level gate drive signal Gn and the nth-level trigger signal STn according to the nth-level control signal Qn and the clock signal CLK. The nth-level gate drive signal Gn, the nth-level trigger signal STn, and the nth-level control signal Qn can be understood as signals of the sub-drive circuit of the current level n.

[0074] Under the control of the second reverse signal Pn or the first reverse signal Kn, the transistors in the pull-down sustaining module 40 can be turned on alternately to realize the pull-down function, pull down the potential of the nth gate drive signal Gn and maintain it at the second reference low potential VSSG, and pull down the potential of the nth trigger signal STn and maintain it at the first reference low potential VSSQ. This avoids the forward bias drift problem caused by some transistors being in the on state all the time, and ensures the stability of the pull-down sustaining module 40.

[0075] Therefore, the pull-down maintenance module 40 can pull down and maintain the nth-stage gate drive signal Gn and the nth-stage trigger signal STn to the second reference low potential VSSG and the first reference low potential VSSQ, respectively, to prevent low-level fluctuations of the nth-stage gate drive signal Gn and the nth-stage trigger signal STn. This improves the stability and reliability of the nth-stage gate drive signal Gn and the nth-stage trigger signal STn, ensuring that the thin-film transistors of the display panel can be turned on or off normally, thus guaranteeing the normal display of the display panel and extending its lifespan.

[0076] Please see Figure 2 In one embodiment, the pull-down sustaining module 40 includes a fifth transistor 410, a sixth transistor 420, and a seventh transistor 430. The first terminal of the fifth transistor 410 is connected to the third terminal of the first transistor 310 to acquire a first inverted signal Kn. The second terminal of the fifth transistor 410 is connected to the pull-up control module 10 to acquire an nth-level control signal Qn. The third terminal of the fifth transistor 410 is used to acquire a first reference low potential VSSQ.

[0077] The first terminal of the sixth transistor 420 is connected to the third terminal of the first transistor 310 to obtain the first inverted signal Kn. The second terminal of the sixth transistor 420 is connected to the pull-up module 20 to obtain the nth stage trigger signal STn. The third terminal of the sixth transistor 420 is used to obtain the first reference low potential VSSQ.

[0078] The first terminal of the seventh transistor 430 is connected to the third terminal of the first transistor 310 to obtain the first inverted signal Kn. The second terminal of the seventh transistor 430 is connected to the pull-up module 20 to obtain the nth gate drive signal Gn. The third terminal of the seventh transistor 430 is used to obtain the second reference low potential VSSG.

[0079] In this embodiment, the fifth transistor 410, the sixth transistor 420, and the seventh transistor 430 are simultaneously turned on or simultaneously turned off. The fifth transistor 410, the sixth transistor 420, and the seventh transistor 430 form part of the pull-down sustaining module 40 and are connected to the third terminal of the first transistor 310 to acquire the first inverted signal Kn. When the first inverted signal Kn is at a high potential, the fifth transistor 410, the sixth transistor 420, and the seventh transistor 430 are controlled to be turned on simultaneously. When the first inverted signal Kn is at a low potential, the fifth transistor 410, the sixth transistor 420, and the seventh transistor 430 are controlled to be turned off simultaneously and not turned on.

[0080] When the first inverting signal Kn is high, the fifth transistor 410 is turned on, pulling down the nth stage control signal Qn to maintain it at the first reference low potential VSSQ. When the first inverting signal Kn is high, the sixth transistor 420 is turned on, pulling down the nth stage trigger signal STn to maintain it at the first reference low potential VSSQ. When the first inverting signal Kn is high, the seventh transistor 430 is turned on, pulling down the nth stage gate drive signal Gn to maintain it at the second reference low potential VSSG. Thus, the gate drive circuit provided in this application can ensure the stability of the nth stage control signal Qn, the nth stage trigger signal STn, and the nth stage gate drive signal Gn.

[0081] In one embodiment, the pull-down sustaining module 40 includes an eighth transistor 440, a ninth transistor 450, and a tenth transistor 460. The first terminal of the eighth transistor 440 is connected to the third terminal of the third transistor 330 to acquire a second inverted signal Pn. The second terminal of the eighth transistor 440 is connected to the pull-up control module 10 to acquire an nth-level control signal Qn. The third terminal of the eighth transistor 440 is used to acquire a first reference low potential VSSQ.

[0082] The first terminal of the ninth transistor 450 is connected to the third terminal of the third transistor 330 to obtain the second inverted signal. The second terminal of the ninth transistor 450 is connected to the pull-up module 20 to obtain the nth stage trigger signal STn. The third terminal of the ninth transistor 450 is used to obtain the first reference low potential VSSQ.

[0083] The first terminal of the tenth transistor 460 is connected to the third terminal of the third transistor 330 to obtain the second inverted signal Pn. The second terminal of the tenth transistor 460 is connected to the pull-up module 20 to obtain the nth gate drive signal Gn. The third terminal of the tenth transistor 460 is used to obtain the second reference low potential VSSG.

[0084] In this embodiment, the eighth transistor 440, the ninth transistor 450, and the tenth transistor 460 are simultaneously turned on or simultaneously turned off. The eighth transistor 440, the ninth transistor 450, and the tenth transistor 460 form another part of the pull-down sustaining module 40, and are connected to the third terminal of the third transistor 330 to obtain the second inverted signal Pn.

[0085] When the second inverting signal Pn is high, the eighth transistor 440 is turned on, pulling down the nth stage control signal Qn to maintain it at the first reference low level VSSQ. When the second inverting signal Pn is high, the ninth transistor 450 is turned on, pulling down the nth stage trigger signal STn to maintain it at the first reference low level VSSQ. When the second inverting signal Pn is high, the tenth transistor 460 is turned on, pulling down the nth stage gate drive signal Gn to maintain it at the second reference low level VSSG.

[0086] The eighth transistor 440, the ninth transistor 450, and the tenth transistor 460 can respectively pull down and maintain the nth-stage control signal Qn, the nth-stage trigger signal STn, and the nth-stage gate drive signal Gn at the first reference low potential VSSQ and the second reference low potential VSSG. Therefore, the gate drive circuit provided in this application can ensure the stability of the nth-stage control signal Qn, the nth-stage trigger signal STn, and the nth-stage gate drive signal Gn.

[0087] Therefore, under the control of the second reverse signal Pn or the first reverse signal Kn, the fifth transistor 410 and the eighth transistor 440 can be turned on alternately, the sixth transistor 420 and the ninth transistor 450 can be turned on alternately, and the seventh transistor 430 and the tenth transistor 460 can be turned on alternately to realize the pull-down function and prevent the device characteristics from drifting.

[0088] Please see Figure 3 In one embodiment, the pull-up module 20 includes an eleventh transistor 210, a twelfth transistor 220, and a capacitor 230. The first terminal of the eleventh transistor 210 is connected to the pull-up control module 10 and is used to acquire the nth level control signal Qn. The second terminal of the eleventh transistor 210 is used to acquire the clock signal CLK. The third terminal of the eleventh transistor 210 is used to output the nth level trigger signal STn.

[0089] The first terminal of the twelfth transistor 220 is connected to the pull-up control module 10 to obtain the nth stage control signal Qn. The second terminal of the twelfth transistor 220 is used to obtain the clock signal CLK. The third terminal of the twelfth transistor 220 is used to output the nth stage gate drive signal Gn.

[0090] One end of capacitor 230 is connected to the first end of twelfth transistor 220, and the other end of capacitor 230 is connected to the third end of twelfth transistor 220.

[0091] In this embodiment, the input signals of the pull-up module 20 are the nth-stage control signal Qn and the clock signal CLK, and the output signals are the nth-stage gate drive signal Gn and the nth-stage trigger signal STn. It is connected to the first and third terminals of the twelfth transistor 220 via capacitor 230, i.e., between the gate terminal and the source terminal, serving to store charge, stabilize voltage, and couple and transmit signals.

[0092] In one embodiment, the nth-stage control signal Qn input to the first terminal of the twelfth transistor 220 is pulled down to the first reference low potential VSSQ, and the nth-stage gate drive signal Gn output from the third terminal of the twelfth transistor 220 is pulled down to the second reference low potential VSSG. The first reference low potential VSSQ is less than the second reference low potential VSSG, and the Vgs of the twelfth transistor 220 = VSSQ - VSSG, which is less than zero. This makes the twelfth transistor 220 less prone to forward bias under negative stress. Therefore, the twelfth transistor 220 is less prone to forward bias under negative stress, ensuring that the nth-stage gate drive signal Gn can be stably maintained when a high potential is required. This ensures that the thin-film transistors of the display panel can be normally turned on or off, guaranteeing normal display operation and extending the lifespan of the display panel.

[0093] In one embodiment, the pull-up control module 10 includes a thirteenth transistor 110. The first terminal of the thirteenth transistor 110 is connected to the second terminal to acquire the (n-4)th stage trigger signal STn-4. The third terminal of the thirteenth transistor 110 is connected to the first terminal of the eleventh transistor 210 and the first terminal of the twelfth transistor 220 to output the nth stage control signal Qn.

[0094] In this embodiment, the thirteenth transistor 110 is connected in a diode configuration. The thirteenth transistor 110 is turned on by the (n-4)th stage trigger signal STn-4. The high potential of the (n-4)th stage trigger signal STn-4 charges the nth stage control signal Qn, causing the nth stage control signal Qn to become high. The nth stage control signal Qn serves as the input signal to the pull-up module 20, the input signal to the first terminal of the second transistor 320, and the input signal to the first terminal of the fourth transistor 340.

[0095] In one embodiment, the nth-stage sub-driving circuit further includes a fourteenth transistor 510. The first terminal of the fourteenth transistor 510 is used to acquire a reset signal Reset, the second terminal of the fourteenth transistor 510 is connected to the third terminal of the thirteenth transistor 110, and is used to acquire the nth-stage control signal Qn. The third terminal of the fourteenth transistor 510 is used to acquire a first reference low potential VSSQ.

[0096] In this embodiment, the fourteenth transistor 510 is connected to the reset signal Reset, and under the control of the reset signal Reset, the nth stage control signal Qn is pulled down to the first reference low potential VSSQ to achieve the reset function. When the reset signal Reset is high, the fourteenth transistor 510 is turned on, pulling the nth stage control signal Qn down to the first reference low potential VSSQ. When the reset signal Reset is low, the fourteenth transistor 510 is turned off and not turned on.

[0097] In one embodiment, the nth-level sub-driving circuit further includes a fifteenth transistor 610 and a sixteenth transistor 620. The first terminal of the fifteenth transistor 610 is used to acquire the (n+5)th-level trigger signal STn+5 of the (n+5)th-level sub-driving circuit. The second terminal of the fifteenth transistor 610 is connected to the first terminal of the twelfth transistor 220 and is used to acquire the nth-level control signal Qn. The third terminal of the fifteenth transistor 610 is used to acquire the first reference low potential VSSQ.

[0098] The first terminal of the sixteenth transistor 620 is used to obtain the gate drive signal Gn+4 of the (n+4)th stage of the sub-drive circuit. The second terminal of the sixteenth transistor 620 is connected to the third terminal of the twelfth transistor 220 and is used to obtain the gate drive signal Gn of the nth stage. The third terminal of the sixteenth transistor 620 is used to obtain the second reference low potential VSSG.

[0099] In this embodiment, when the (n+5)th stage trigger signal STn+5 is high, the fifteenth transistor 610 is turned on, pulling down the nth stage control signal Qn to the first reference low potential VSSQ. When the (n+5)th stage trigger signal STn+5 is low, the fifteenth transistor 610 is turned off and not turned on. When the (n+4)th stage gate drive signal Gn+4 is high, the sixteenth transistor 620 is turned on, pulling down the nth stage gate drive signal Gn to the second reference low potential VSSG. When the (n+4)th stage gate drive signal Gn+4 is low, the sixteenth transistor 620 is turned off and not turned on.

[0100] By forming a pull-down module using the fifteenth transistor 610 and the sixteenth transistor 620, the nth-level control signal Qn and the nth-level gate drive signal Gn can be pulled down. This ensures that when the nth-level control signal Qn and the nth-level gate drive signal Gn need to be at a low potential, they can be accurately set to a low potential and maintained stably. This prevents pixel malfunctions or leakage, and improves the stability and reliability of the gate drive circuit.

[0101] Furthermore, the gate drive signal Gn+4 of the (n+4)th stage and the trigger signal STn+5 of the (n+5)th stage are used to realize the interaction between the gate drive signals and the trigger signals in each cascaded circuit in the gate drive circuit, so as to realize line-by-line scanning drive, ensure the accuracy of the timing of the cascaded circuit, and realize the synchronization between the cascaded circuits.

[0102] In one embodiment, the first terminal of each transistor in the above embodiment is the gate terminal, the second terminal of each transistor is the drain terminal, and the third terminal of each transistor is the source terminal.

[0103] Please see Figure 4 In one embodiment, the input waveforms of the various signals of the gate drive circuit are as follows: Figure 4 As shown. The start signal STV is used to initialize the gate drive circuit. The clock signal CLK alternates between high and low levels. The first local clock signal LC1 and the second local clock signal LC2 are a set of opposite local clock signals. When the first local clock signal LC1 is low, the second local clock signal LC2 is high. When the first local clock signal LC1 is high, the second local clock signal LC2 is low.

[0104] When the (n-4)th stage trigger signal STn-4 is high, the corresponding clock signal CLK is low, and the two are opposite. When the thirteenth transistor 110 charges the nth stage control signal Qn at the high potential of the (n-4)th stage trigger signal STn-4, it causes the nth stage control signal Qn to become high. At this time, the clock signal CLK at the first terminal of the first transistor 310 is low, causing the first transistor 310 to be turned off (or not conducting). Subsequently, the first terminal of the second transistor 320 receives the nth stage control signal Qn at a high potential, causing the second transistor 320 to be turned on (or conducting), pulling the potential of the first inverting signal Kn low to the first reference low potential VSSQ. This achieves the effect of the inverter module, such as... Figure 5 As shown, the nth-stage control signal Qn is opposite to the first inverted signal Kn. The inverter module function is implemented using the first transistor 310 and the second transistor 320. Similarly, the inverter module function can also be implemented using the third transistor 330 and the fourth transistor 340.

[0105] This application provides a display panel including the gate driving circuit of any of the above embodiments. This application can be widely applied to various display panels and devices having display panels, such as mobile phones, laptop computers, and LCD TVs.

[0106] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the above-described division of functional units and modules is merely an example. In practical applications, the above functions can be assigned to different functional units and modules as needed, that is, the internal structure of the device can be divided into different functional units or modules to complete all or part of the functions described above. The functional units and modules in the embodiments can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit. Furthermore, the specific names of the functional units and modules are only for easy differentiation and are not intended to limit the scope of protection of this application. The specific working process of the units and modules in the above system can be referred to the corresponding process in the foregoing method embodiments, and will not be repeated here.

[0107] In the above embodiments, the descriptions of each embodiment have different focuses. For parts that are not described in detail or recorded in a certain embodiment, please refer to the relevant descriptions of other embodiments.

[0108] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0109] Furthermore, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0110] If the integrated module / unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, all or part of the processes in the methods of the above embodiments can also be implemented by a computer program instructing related hardware. The computer program can be stored in a computer-readable storage medium, and when executed by a processor, it can implement the steps of the various method embodiments described above. The computer program includes computer program code, which can be in the form of source code, object code, executable files, or certain intermediate forms. The computer-readable medium can include: any entity or device capable of carrying the computer program code, recording media, USB flash drives, portable hard drives, magnetic disks, optical disks, computer memory, read-only memory (ROM), random access memory (RAM), electrical carrier signals, telecommunication signals, and software distribution media, etc. It should be noted that the content included in the computer-readable medium can be appropriately added or removed according to the requirements of legislation and patent practice in the jurisdiction. For example, in some jurisdictions, according to legislation and patent practice, computer-readable media do not include electrical carrier signals and telecommunication signals.

[0111] The above-described embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application, and should all be included within the protection scope of this application.

Claims

1. A gate driving circuit, characterized in that, The nth-level sub-drive circuit includes cascaded sub-drive circuits. Pull-up control module (10) is used to output the nth level control signal according to the n-4th level trigger signal of the n-4th level sub-drive circuit; where n is an integer greater than 4; A first transistor (310) is used to acquire a clock signal at its first terminal and to acquire a first local clock signal at its second terminal; wherein the (n-4)th stage trigger signal is opposite to the clock signal. The second transistor (320) has its first terminal connected to the pull-up control module (10) for acquiring the nth level control signal, and its second terminal connected to the third terminal of the first transistor (310) for outputting a first inverted signal. The third terminal of the second transistor (320) is used to acquire a first reference low potential.

2. The gate driving circuit as described in claim 1, characterized in that, The nth-level sub-driving circuit also includes: A third transistor (330), the first terminal of which is used to acquire the clock signal, and the second terminal of which is used to acquire a second local clock signal; The fourth transistor (340) has its first terminal connected to the pull-up control module (10) for acquiring the nth level control signal, its second terminal connected to the third terminal of the third transistor (330) for outputting a second inverted signal, and its third terminal for acquiring the first reference low potential. The second local clock signal is opposite to the first local clock signal.

3. The gate driving circuit as described in claim 2, characterized in that, The nth-level sub-driving circuit also includes: A pull-down sustaining module (40) is connected to the pull-up control module (10). The pull-down sustaining module (40) is also connected to the third terminal of the first transistor (310) or the third terminal of the third transistor (330). The pull-down sustaining module (40) is used to pull down and maintain the potential of the nth level control signal to the first reference low potential according to the first reverse signal or the second reverse signal.

4. The gate driving circuit as described in claim 3, characterized in that, The nth-level sub-driving circuit also includes: Pull-up module (20), connected to the pull-up control module (10), is used to output the nth stage gate drive signal and the nth stage trigger signal according to the nth stage control signal and the clock signal; The pull-down sustaining module (40) is connected to the pull-up module (20) and is used to pull down and maintain the potential of the nth gate drive signal to the second reference low potential according to the second reverse signal or the first reverse signal, and to pull down and maintain the potential of the nth trigger signal to the first reference low potential.

5. The gate driving circuit as described in claim 4, characterized in that, The pull-down sustaining module (40) includes: The fifth transistor (410) has its first terminal connected to the third terminal of the first transistor (310) for acquiring the first reverse signal, and its second terminal connected to the pull-up control module (10) for acquiring the nth level control signal. The third terminal of the fifth transistor (410) is used to acquire the first reference low potential. The sixth transistor (420) has its first terminal connected to the third terminal of the first transistor (310) for acquiring the first reverse signal, its second terminal connected to the pull-up module (20) for acquiring the nth stage trigger signal, and its third terminal for acquiring the first reference low potential. The seventh transistor (430) has its first terminal connected to the third terminal of the first transistor (310) for acquiring the first inverted signal, its second terminal connected to the pull-up module (20) for acquiring the nth gate drive signal, and its third terminal for acquiring the second reference low potential.

6. The gate driving circuit as described in claim 4, characterized in that, The pull-down sustaining module (40) includes: The eighth transistor (440) has its first terminal connected to the third terminal of the third transistor (330) for acquiring the second inverted signal, its second terminal connected to the pull-up control module (10) for acquiring the nth level control signal, and its third terminal for acquiring the first reference low potential. The ninth transistor (450) has its first terminal connected to the third terminal of the third transistor (330) for acquiring the second inverted signal, its second terminal connected to the pull-up module (20) for acquiring the nth stage trigger signal, and its third terminal for acquiring the first reference low potential. The tenth transistor (460) has its first terminal connected to the third terminal of the third transistor (330) for acquiring the second inverted signal, its second terminal connected to the pull-up module (20) for acquiring the nth gate drive signal, and its third terminal for acquiring the second reference low potential.

7. The gate driving circuit as described in claim 5 or claim 6, characterized in that, The pull-up module (20) includes: The eleventh transistor (210) has its first terminal connected to the pull-up control module (10) for acquiring the nth level control signal, its second terminal for acquiring the clock signal, and its third terminal for outputting the nth level trigger signal. The twelfth transistor (220) has its first terminal connected to the pull-up control module (10) for acquiring the nth level control signal, its second terminal for acquiring the clock signal, and its third terminal for outputting the nth level gate drive signal. A capacitor (230) is provided, one end of which is connected to the first end of the twelfth transistor (220), and the other end of which is connected to the third end of the twelfth transistor (220).

8. The gate driving circuit as described in claim 7, characterized in that, The pull-up control module (10) includes: The thirteenth transistor (110) has its first and second terminals connected to obtain the n-4th stage trigger signal. The third terminal of the thirteenth transistor (110) is connected to the first terminal of the eleventh transistor (210) and the first terminal of the twelfth transistor (220) to output the nth stage control signal.

9. The gate driving circuit as described in claim 8, characterized in that, The nth-level sub-driving circuit also includes: The fourteenth transistor (510) has a first terminal for acquiring a reset signal, a second terminal for connecting to the third terminal of the thirteenth transistor (110) for acquiring the nth level control signal, and a third terminal for acquiring the first reference low potential.

10. The gate driving circuit as described in claim 7, characterized in that, The nth-level sub-driving circuit also includes: The fifteenth transistor (610) has a first terminal used to acquire the (n+5)th stage trigger signal of the (n+5)th stage sub-driving circuit, a second terminal of the fifteenth transistor (610) connected to the first terminal of the twelfth transistor (220) for acquiring the nth stage control signal, and a third terminal of the fifteenth transistor (610) for acquiring the first reference low potential. The sixteenth transistor (620) has a first terminal for acquiring the gate drive signal of the (n+4)th stage of the (n+4)th stage sub-driving circuit, a second terminal of the sixteenth transistor (620) connected to the third terminal of the twelfth transistor (220) for acquiring the gate drive signal of the nth stage, and a third terminal of the sixteenth transistor (620) for acquiring the second reference low potential.

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