Frequency division circuit, frequency divider, radio frequency chip and electronic device
By designing a sub-module containing a frequency division unit and a phase generation unit in the frequency divider circuit, high stability of the frequency divider output signal is achieved, solving the phase noise problem caused by multiple clock signal operations in the prior art.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- BEIJING X RING TECHNOLOGY CO LTD
- Filing Date
- 2025-05-28
- Publication Date
- 2026-05-29
AI Technical Summary
Existing frequency dividers perform multiple logical operations on the clock signal, resulting in high phase noise and poor stability of the output signal.
The design employs a frequency divider circuit, with each sub-module containing a frequency divider unit and a phase generation unit. It generates an output signal with a phase difference of π/n through a single operation, avoiding noise accumulation after multiple operations on the clock signal.
It improves the phase stability of the output signal, ensures signal quality, and reduces the accumulation of phase noise in the clock signal during the operation process.
Smart Images
Figure CN224305759U_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of radio frequency technology, and in particular to a frequency divider circuit, a frequency divider, a radio frequency chip, and an electronic device. Background Technology
[0002] Frequency dividers are core components in radio frequency communication systems. They can reduce or divide the frequency of the input signal into multiple frequency bands according to a certain ratio to meet the signal processing needs of different circuits or systems.
[0003] Existing frequency dividers achieve multi-phase waveform output by performing multiple logical operations on the clock signal, resulting in high phase noise and poor stability of the output signal. Utility Model Content
[0004] This application provides a frequency divider circuit, a frequency divider, an RF chip, and an electronic device.
[0005] The first aspect of this application provides a frequency divider circuit, the frequency divider circuit including a first submodule to a 2nth submodule, where n is a natural number greater than or equal to 3; the first submodule to the 2nth submodule are arranged sequentially in the circumferential direction along a first direction, and each submodule in the first submodule to the 2nth submodule includes a frequency divider unit and a phase generation unit;
[0006] The frequency division unit includes a first input terminal, a second input terminal, and a first output terminal; the phase generation unit includes a third input terminal, a fourth input terminal, a fifth input terminal, and a second output terminal; within the same submodule, the first output terminal is connected to the fourth input terminal; in every two adjacent submodules, the second output terminal of the submodule located on the front side in the first direction is connected to the first input terminal of the submodule located on the rear side; the third input terminal of each submodule is used to input a clock signal; the second output terminals of two adjacent submodules are used to output an output signal with a phase difference of π / n;
[0007] When k ≤ n, the second input terminal of the k-th submodule is connected to the first output terminal of the (k+n)-th submodule; when k > n, the second input terminal of the k-th submodule is connected to the first output terminal of the (kn)-th submodule; when k > n-2, the fifth output terminal of the k-th submodule is connected to the first output terminal of the (k-n+2)-th submodule; when k ≤ n-2, the fifth output terminal of the k-th submodule is connected to the first output terminal of the (k+n+2)-th submodule; where k is a natural number greater than or equal to 1 and less than or equal to 2n.
[0008] In some embodiments, the frequency divider unit includes a first logic gate, which has two input terminals and one output terminal. The two input terminals of the first logic gate are the first input terminal and the second input terminal of the frequency divider unit, respectively, and the output terminal of the first logic gate is the first output terminal of the frequency divider unit.
[0009] In some embodiments, when k≤n, the first logic gate in the k-th submodule is connected to the first logic gate in the (k+n)-th submodule to form a latch; when k>n, the first logic gate in the k-th submodule is connected to the first logic gate in the (kn)-th submodule to form a latch.
[0010] In some embodiments, the first logic gates are all NOR gates.
[0011] In some embodiments, the phase generation unit includes a second logic gate, which has three input terminals and one output terminal. The three input terminals of the second logic gate are the third, fourth, and fifth input terminals of the frequency division unit, respectively, and the output terminal of the second logic gate is the second output terminal of the phase generation unit.
[0012] In some embodiments, the second logic gate is a NOR gate.
[0013] In some embodiments, the clock signal input to the phase generation unit of the adjacent submodule is an inverted signal.
[0014] In some embodiments, n equals 4, and the second output terminals of two adjacent submodules are used to output output signals with a phase difference of π / 4.
[0015] A second aspect of this application provides a frequency divider, the frequency divider including the frequency divider circuit described above, the frequency divider including a first signal input terminal and a second signal input terminal, the first signal input terminal being used to input a first input signal, the second signal input terminal being used to input a second input signal, the first input signal and the second input signal being inverse signals; the first signal input terminal being connected to the third input terminal of the x-th submodule, where x is an odd number greater than or equal to 1 and less than 2n; the second signal input terminal being connected to the third input terminal of the y-th submodule, where y is an even number greater than 1 and less than or equal to 2n;
[0016] The frequency divider also includes a first signal output terminal to a 2nth signal output terminal, which are respectively connected to the second output terminals of the first submodule to the 2nth submodule.
[0017] A third aspect of this application provides a radio frequency chip, which includes the frequency divider circuit described above, or includes the frequency divider described above.
[0018] A fourth aspect of this application provides an electronic device comprising the radio frequency chip described above.
[0019] Each submodule of the frequency divider circuit provided in this application includes a frequency divider unit and a phase generation unit. The phase generation unit of each submodule, combined with the clock signal, the intermediate signal output by the frequency divider unit, and the feedback signal from another submodule, can generate an output signal with a phase difference of π / n. After the clock signal is input to the phase generation unit, it participates in one operation to output a multi-phase output signal, thereby avoiding noise accumulation after multiple operations on the clock signal, which helps to improve the phase stability of the output signal and ensure the signal quality of the output signal.
[0020] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and do not limit this application. Attached Figure Description
[0021] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.
[0022] Figure 1 and Figure 2 A schematic structural block diagram of a frequency divider circuit provided in an embodiment of this application;
[0023] Figure 3 and Figure 4 A circuit structure block diagram of a frequency divider circuit provided in an embodiment of this application;
[0024] Figure 5 Waveform diagram of the input and output signals of a frequency divider circuit provided in an embodiment of this application;
[0025] Figure 6 This is a schematic diagram of the structure of a frequency divider provided in an embodiment of this application. Detailed Implementation
[0026] The technical solutions in the embodiments (or "implementations") of this application will be clearly and completely described herein with reference to the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements.
[0027] If the embodiments of this application contain terms relating to directional indications or positional relationships (such as up, down, left, right, front, back, inside, outside, top, bottom, center, vertical, horizontal, longitudinal, transverse, length, width, counterclockwise, clockwise, axial, radial, circumferential, etc.), such terms are only used to explain the relative positional relationships and movements between components in a specific posture (as shown in the attached figures); if the specific posture changes, the directional indications or positional relationships will also change accordingly. Furthermore, the terms "first" and "second" used in the embodiments of this application are only for descriptive convenience and should not be construed as indicating or implying relative importance.
[0028] The frequency divider circuit, frequency divider, radio frequency chip, and electronic device according to embodiments of this application will be described in detail below with reference to the accompanying drawings. Unless otherwise specified, the features of the following embodiments and implementations can complement or combine with each other.
[0029] This application provides a frequency divider circuit, such as... Figure 1 and Figure 2 As shown, the frequency divider circuit includes a first submodule to a 2n-th submodule, where n is a natural number greater than or equal to 3. The first to 2n-th submodules are arranged sequentially along the first direction X in the circumferential direction. Each submodule in the first to 2n-th submodules includes a frequency divider unit a and a phase generation unit b.
[0030] Frequency divider unit a includes a first input terminal, a second input terminal, and a first output terminal. Phase generation unit b includes a third input terminal, a fourth input terminal, a fifth input terminal, and a second output terminal.
[0031] Within the same submodule A, the first output terminal is connected to the fourth input terminal. In every two adjacent submodules, the second output terminal of the submodule located in front in the first direction X is connected to the first input terminal of the submodule located behind. The third input terminal of each submodule is used to input the clock signal ck. The second output terminals of two adjacent submodules are used to output output signals P1 to Pn with a phase difference of π / n.
[0032] When k ≤ n, the second input of the k-th submodule is connected to the first output of the (k+n)-th submodule. When k > n, the second input of the k-th submodule is connected to the first output of the (kn)-th submodule. When k > n-2, the fifth output of the k-th submodule is connected to the first output of the (k-n+2)-th submodule. When k ≤ n-2, the fifth output of the k-th submodule is connected to the first output of the (k+n+2)-th submodule. Here, k is a natural number greater than or equal to 1 and less than or equal to 2n.
[0033] Each submodule A of the frequency divider circuit in this application includes a frequency divider unit a and a phase generation unit b. The phase generation unit b of each submodule A, combined with the clock signal ck, the intermediate signal output from the frequency divider unit a, and the feedback signal from another submodule, can generate output signals P1 to Pn with a phase difference of π / n. After the clock signal is input to the phase generation unit, it participates in a single operation to output a multi-phase output signal, thereby avoiding noise accumulation after multiple operations on the clock signal, which helps to improve the phase stability of the output signal and ensure the signal quality of the output signal.
[0034] exist Figure 1 and Figure 2 In the illustrated embodiment, the frequency divider circuit includes a first submodule A1 to an eighth submodule A8, which are arranged sequentially in the circumferential direction along a first direction X. The second output terminal of each submodule is used to output output signals P1 to P8 with a phase difference of π / 4.
[0035] The first output terminal of each submodule A is connected to the second input terminal of the submodule located behind it and spaced three submodules apart in the first direction X, and is also connected to the fifth input terminal of the submodule located behind it and spaced one submodule apart in the first direction.
[0036] It should be noted that, as Figure 1 and Figure 2 As shown, the first direction X refers to the counterclockwise direction, and the corresponding clockwise direction is the second direction. In other embodiments, the first direction X can be clockwise and the second direction can be counterclockwise. In two adjacent sub-modules, the sub-module located further forward in the first direction X is the front sub-module, and the sub-module located further back is the rear sub-module. Taking the first sub-module A1 as an example, the eighth sub-module A8, located before the first sub-module A1 in the first direction X, is the sub-module located before the first sub-module A1, and the second sub-module A2, located after the first sub-module A1, is the sub-module located behind the first sub-module A1.
[0037] Specifically, the second output terminal b14 of the first submodule A1 is connected to the first input terminal a21 of the second submodule A2, the second output terminal b24 of the second submodule A2 is connected to the first input terminal a31 of the third submodule A3, the second output terminal b34 of the third submodule A3 is connected to the first input terminal a41 of the fourth submodule A4, the second output terminal b44 of the fourth submodule A4 is connected to the first input terminal a51 of the fifth submodule A5, the second output terminal b54 of the fifth submodule A5 is connected to the first input terminal a61 of the sixth submodule A6, the second output terminal b64 of the sixth submodule A6 is connected to the first input terminal a71 of the seventh submodule A7, the second output terminal b74 of the seventh submodule A7 is connected to the first input terminal a81 of the eighth submodule A8, and the second output terminal b84 of the eighth submodule A8 is connected to the first input terminal a11 of the first submodule A1, thus forming a sequentially connected closed-loop circuit structure.
[0038] Specifically, for different submodules, the first output terminal a13 of the first submodule A1 is connected to the second input terminal a52 of the fifth submodule A5, and is also connected to the fifth input terminal b33 of the third submodule A3; the first output terminal a23 of the second submodule A2 is connected to the second input terminal a62 of the sixth submodule A6, and is also connected to the fifth input terminal b43 of the fourth submodule A4; the first output terminal a33 of the third submodule A3 is connected to the second input terminal a72 of the seventh submodule A7, and is also connected to the fifth input terminal b53 of the fifth submodule A5; the first output terminal a43 of the fourth submodule A4 is connected to the second input terminal a82 of the eighth submodule A8, and is also connected to the fifth input terminal b33 of the sixth submodule A6. b63 is connected; the first output terminal a53 of the fifth submodule A5 is connected to the second input terminal a12 of the first submodule A1, and to the fifth input terminal b73 of the seventh submodule A7; the first output terminal a63 of the sixth submodule A6 is connected to the second input terminal a22 of the second submodule A2, and to the fifth input terminal b83 of the eighth submodule A8; the first output terminal a73 of the seventh submodule A7 is connected to the second input terminal a32 of the third submodule A3, and to the fifth input terminal b13 of the first submodule A1; the first output terminal a83 of the eighth submodule A8 is connected to the second input terminal a42 of the fourth submodule A4, and to the fifth input terminal b23 of the second submodule A2.
[0039] When the frequency divider circuit includes eight sub-modules, it can generate output signals P1 to P8 with a phase difference of π / 4. After the clock signal is input to the phase generation unit, it participates in one operation to output an eight-phase output signal, which has high stability.
[0040] In one embodiment, such as Figure 3 and Figure 4As shown, frequency divider unit a includes a first logic gate, which has two input terminals and one output terminal. The two input terminals of the first logic gate are the first input terminal and the second input terminal of frequency divider unit a, respectively, and the output terminal of the first logic gate is the first output terminal of frequency divider unit a. Figure 4 As shown, taking the first submodule A1 as an example, the frequency divider unit a1 includes a first logic gate. The two input terminals of the first logic gate are the first input terminal a11 and the second input terminal a12 of the frequency divider unit a1, and the output terminal of the first logic gate is the first output terminal a13 of the frequency divider unit a1.
[0041] In one embodiment, when k ≤ n, the first logic gate in the k-th submodule is connected to the first logic gate in the (k+n)-th submodule to form a latch. When k > n, the first logic gate in the k-th submodule is connected to the first logic gate in the (kn)-th submodule to form a latch. Figure 3 and Figure 4 In the illustrated embodiment, the first logic gate in the first submodule A1 is connected to the first logic gate in the fifth submodule A5 to form a latch. The first logic gate in the second submodule A2 is connected to the first logic gate in the sixth submodule A6 to form a latch. The first logic gate in the third submodule A3 is connected to the first logic gate in the seventh submodule A7 to form a latch. The first logic gate in the fourth submodule A4 is connected to the first logic gate in the eighth submodule A8 to form a latch. The closed-loop structure of the latch ensures that the signal state is not affected by noise, keeps the intermediate signal output by the first logic gate stable, and thus improves the reliability of frequency division and phase generation.
[0042] When the frequency divider circuit includes eight sub-modules, the output of the first logic gate in the first sub-module A1 to the eighth sub-module A8 is used to output a divided-four frequency signal of the clock signal ck. That is, the intermediate signals E1 to E8 output by the first logic gate in the first sub-module A1 to the eighth sub-module A8 are all divided-four frequency signals of the clock signal ck.
[0043] In one embodiment, the first logic gates are all NOR gates.
[0044] In one embodiment, the phase generation unit b includes a second logic gate, which has three input terminals and one output terminal. The three input terminals of the second logic gate are the third, fourth, and fifth input terminals of the phase generation unit b, and the output terminal of the second logic gate is the second output terminal of the phase generation unit b. Taking the first submodule A1 as an example, the three input terminals of the second logic gate are the first input terminal b11, the second input terminal b12, and the third input terminal b13 of the phase generation unit b1, and the output terminal of the second logic gate is the output terminal b14 of the phase generation unit b1.
[0045] In one embodiment, the second logic gate is a NOR gate.
[0046] In one embodiment, such as Figure 3 and Figure 5 As shown, the clock signal ck input to the phase generation unit b of adjacent submodule A is an inverted signal. The clock signal ck includes a first clock signal ckn and a second clock signal ckp. The signals input to the third input terminals of the first submodule A1, the third submodule A3, the fifth submodule A5, and the seventh submodule A7 are all the first clock signal ckn, while the signals input to the third input terminals of the second submodule A2, the fourth submodule A4, the sixth submodule A6, and the eighth submodule A8 are all the second clock signal ckp. When the first clock signal ckn is high, the second clock signal ckp is low, and when the first clock signal ckn is low, the second clock signal ckp is high. The phase difference π between the first clock signal ckn and the second clock signal ckp can be used as a reference, enabling the phase generation unit to generate an output signal with an accurate phase difference of π / 4 through calculation.
[0047] like Figure 5 As shown, let the interval between two adjacent time nodes be T, for example, the time interval from t0 to t1 is T. The frequencies of the first clock signal ckn and the second clock signal ckp are both 2T.
[0048] According to the waveform diagram, during the time period t0 to t1, the first clock signal ckn is at a low level and the second clock signal ckp is at a high level. Among the intermediate signals E output by the NOR gate of the frequency division unit a, E1, E2, E7, and E8 are at a low level, while E3, E4, E5, and E6 are at a high level. At this time, the output signal P1 of the NOR gate of the phase generation unit b1 is at a high level, while the output signals of the other sub-modules are at a low level.
[0049] During the time interval t1 to t2, the first clock signal ckn is at a high level and the second clock signal ckp is at a low level. Among the intermediate signals E output by the NOR gate of the frequency division unit a, E1, E2, E3, and E8 are at a low level, while E4, E5, E6, and E7 are at a high level. At this time, the output signal P2 of the NOR gate of the phase generation unit b2 is at a high level, while the output signals of the other sub-modules are at a low level.
[0050] During the time interval t2 to t3, the first clock signal ckn is at a low level and the second clock signal ckp is at a high level. Among the intermediate signals E output by the NOR gate of the frequency division unit a, E1, E2, E3, and E4 are at a low level, while E5, E6, E7, and E8 are at a high level. At this time, the output signal P3 of the NOR gate of the phase generation unit b3 is at a high level, while the output signals of the other sub-modules are at a low level.
[0051] During the time interval t3 to t4, the first clock signal ckn is at a high level and the second clock signal ckp is at a low level. Among the intermediate signals E output by the NOR gate of the frequency division unit a, E2, E3, E4, and E5 are at a low level, while E1, E6, E7, and E8 are at a high level. At this time, the output signal P4 of the NOR gate of the phase generation unit b4 is at a high level, while the output signals of the other sub-modules are at a low level.
[0052] During the time interval t4 to t5, the first clock signal ckn is at a low level and the second clock signal ckp is at a high level. Among the intermediate signals E output by the NOR gate of the frequency division unit a, E3, E4, E5, and E6 are at a low level, while E1, E2, E7, and E8 are at a high level. At this time, the output signal P5 of the NOR gate of the phase generation unit b5 is at a high level, while the output signals of the other sub-modules are at a low level.
[0053] During the time interval t5 to t6, the first clock signal ckn is at a high level and the second clock signal ckp is at a low level. Among the intermediate signals E output by the NOR gate of the frequency division unit a, E4, E5, E6, and E7 are at a low level, while E1, E2, E3, and E8 are at a high level. At this time, the output signal P6 of the NOR gate of the phase generation unit b6 is at a high level, while the output signals of the other sub-modules are at a low level.
[0054] During the time interval t6 to t7, the first clock signal ckn is at a low level and the second clock signal ckp is at a high level. Among the intermediate signals E output by the NOR gate of the frequency division unit a, E5, E6, E7, and E8 are at a low level, while E1, E2, E3, and E4 are at a high level. At this time, the output signal P7 of the NOR gate of the phase generation unit b7 is at a high level, while the output signals of the other sub-modules are at a low level.
[0055] During the time interval t6 to t7, the first clock signal ckn is at a high level and the second clock signal ckp is at a low level. Among the intermediate signals E output by the NOR gate of the frequency division unit a, E1, E6, E7, and E8 are at a low level, while E2, E3, E4, and E5 are at a high level. At this time, the output signal P8 of the NOR gate of the phase generation unit b8 is at a high level, while the output signals of the other sub-modules are at a low level.
[0056] During the time interval t8 to t1', the first clock signal ckn is low and the second clock signal ckp is high. Among the intermediate signals E output by the NOR gate of the frequency divider unit a, E1, E2, E7, and E8 are low, while E3, E4, E5, and E6 are high. At this time, the output signal P1 of the NOR gate of the phase generation unit b1 is high, and the output signals of the other sub-modules are low, thus entering the next cycle.
[0057] Analysis of the waveform shows that the intermediate signal E output by the NOR gate of frequency divider unit a has a period of 8T, which is a 4-fold division of the clock signal. The phase difference between the intermediate signals E output by adjacent frequency divider units a is π / 4, ultimately generating eight output signals P1 to P8 with a phase difference of π / 4. The final output signal can be generated by participating the clock signal ck in a single NOR operation of the second logic gate, effectively reducing the phase noise generated by the clock signal ck during the operation.
[0058] Furthermore, according to the waveform diagram, the rising edges of the high levels of output signals P1, P3, P5, and P7 all correspond to the falling edges of the low levels of the first clock signal ckn, and the rising edges of the high levels of output signals P2, P4, P6, and P8 all correspond to the falling edges of the low levels of the second clock signal ckp. The output signals P1 to P8 are independent of the clock edges of the intermediate signals E1 to E8.
[0059] Therefore, the clock edge of the intermediate signal E does not directly determine the timing of the output signal P, eliminating the need for strict matching of routing delays between sub-modules, thus reducing routing requirements and layout complexity between sub-modules.
[0060] This application also provides a frequency divider, which includes the frequency divider circuit described above. For example... Figure 6 As shown, the frequency divider B also includes a first signal input terminal IN1 and a second signal input terminal IN2. The first signal input terminal IN1 is used to input a first input signal, and the second signal input terminal IN2 is used to input a second input signal. The first input signal and the second input signal are inverted signals. The first input signal is a first clock signal ckn, and the second input signal is a second clock signal ckp. In some embodiments, the first clock signal ckn can be a local oscillator differential signal LO-, and the first clock signal ckp can be a local oscillator differential signal LO+.
[0061] The first signal input terminal is connected to the third input terminal of the x-th submodule, where x is an odd number greater than or equal to 1 and less than 2n. The second signal input terminal is connected to the third input terminal of the y-th submodule, where y is an even number greater than 1 and less than or equal to 2n. For example, when the frequency divider circuit includes eight submodules, the first signal input terminal IN1 is connected to the third input terminals of the first submodule A1, the third submodule A3, the fifth submodule A5, and the seventh submodule A7, respectively. The second signal input terminal IN2 is connected to the third input terminals of the second submodule A2, the fourth submodule A4, the sixth submodule A6, and the eighth submodule A8, respectively.
[0062] The frequency divider also includes a first signal output terminal to a 2nth signal output terminal, which are respectively connected to the second output terminals of the first submodule to the 2nth submodule. For example, when the frequency divider circuit includes eight submodules, the frequency divider B also includes a first signal output terminal OUT1 to an eighth signal output terminal OUT8, which are respectively connected to the second output terminals of the first submodule A1 to the eighth submodule A8, for outputting output signals P1 to P8 with a phase difference of π / 4.
[0063] This application also provides a radio frequency chip, which includes the frequency divider circuit or frequency divider described above. It can be used in application scenarios that require frequency synthesis, signal conversion and other necessary radio frequency signal processing, such as mobile communication, satellite communication, etc.
[0064] This application also provides an electronic device, which includes the radio frequency chip described above. The electronic device may be, for example, a smartphone, a base station, a wireless router, a radar system, etc.
[0065] It should be noted that the technical solutions or features described in the above embodiments can be combined or supplemented with each other without conflict. The scope of protection of this application is not limited to the precise structures described in the above embodiments and shown in the accompanying drawings; all modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of protection of this application.
Claims
1. A frequency divider circuit, characterized in that, The frequency division circuit includes a first submodule to a 2nth submodule, where n is a natural number greater than or equal to 3; the first submodule to the 2nth submodule are arranged sequentially in the circumferential direction along a first direction, and each submodule in the first submodule to the 2nth submodule includes a frequency division unit and a phase generation unit; The frequency division unit includes a first input terminal, a second input terminal, and a first output terminal; the phase generation unit includes a third input terminal, a fourth input terminal, a fifth input terminal, and a second output terminal; in the same submodule, the first output terminal is connected to the fourth input terminal; in every two adjacent submodules, the second output terminal of the submodule located on the front side in the first direction is connected to the first input terminal of the submodule located on the rear side; the third input terminal of each submodule is used to input a clock signal; The second output terminals of two adjacent sub-modules are used to output output signals with a phase difference of π / n; When k ≤ n, the second input terminal of the k-th submodule is connected to the first output terminal of the (k+n)-th submodule; when k > n, the second input terminal of the k-th submodule is connected to the first output terminal of the (kn)-th submodule; when k > n-2, the fifth output terminal of the k-th submodule is connected to the first output terminal of the (k-n+2)-th submodule; when k ≤ n-2, the fifth output terminal of the k-th submodule is connected to the first output terminal of the (k+n+2)-th submodule; where k is a natural number greater than or equal to 1 and less than or equal to 2n.
2. The frequency divider circuit according to claim 1, characterized in that, The frequency divider unit includes a first logic gate, which has two input terminals and one output terminal. The two input terminals of the first logic gate are the first input terminal and the second input terminal of the frequency divider unit, respectively, and the output terminal of the first logic gate is the first output terminal of the frequency divider unit.
3. The frequency divider circuit according to claim 2, characterized in that, When k≤n, the first logic gate in the kth submodule is connected to the first logic gate in the (k+n)th submodule to form a latch; when k>n, the first logic gate in the kth submodule is connected to the first logic gate in the (kn)th submodule to form a latch.
4. The frequency divider circuit according to claim 3, characterized in that, The first logic gates are all NOR gates.
5. The frequency divider circuit according to claim 1, characterized in that, The phase generation unit includes a second logic gate, which has three input terminals and one output terminal. The three input terminals of the second logic gate are the third, fourth, and fifth input terminals of the phase generation unit, respectively, and the output terminal of the second logic gate is the second output terminal of the phase generation unit.
6. The frequency divider circuit according to claim 5, characterized in that, The second logic gate is a NOR gate.
7. The frequency divider circuit according to claim 1, characterized in that, The clock signal input to the phase generation unit of the adjacent submodule is an inverted signal.
8. The frequency divider circuit according to claim 1, characterized in that, When n equals 4, the second output terminals of two adjacent sub-modules are used to output output signals with a phase difference of π / 4.
9. A frequency divider, characterized in that, The frequency divider includes the frequency divider circuit according to any one of claims 1 to 8. The frequency divider includes a first signal input terminal and a second signal input terminal. The first signal input terminal is used to input a first input signal, and the second signal input terminal is used to input a second input signal. The first input signal and the second input signal are inverted signals. The first signal input terminal is connected to the third input terminal of the x-th submodule, where x is an odd number greater than or equal to 1 and less than 2n. The second signal input terminal is connected to the third input terminal of the y-th submodule, where y is an even number greater than 1 and less than or equal to 2n. The frequency divider also includes a first signal output terminal to a 2nth signal output terminal, which are respectively connected to the second output terminals of the first submodule to the 2nth submodule.
10. A radio frequency chip, characterized in that, The radio frequency chip includes the frequency divider circuit according to any one of claims 1 to 8, or includes the frequency divider according to claim 9.
11. An electronic device, characterized in that, The electronic device includes the radio frequency chip of claim 10.