Low on-resistance SJ MOSFET devices
By setting multiple vias and thickening the gate bottom oxide layer in the SJ MOSFET device, the problem of increased on-resistance caused by the long distance between the gate trench and the vias is solved, thereby improving the on-resistance and shock resistance of the device.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- HEFEI SIPU SEMICON TECH CO LTD
- Filing Date
- 2025-07-29
- Publication Date
- 2026-05-29
AI Technical Summary
In existing SJ MOSFET devices, the long distance between the gate trench and the connection hole leads to an increase in additional on-resistance, which affects device performance.
Multiple vias are incorporated into the SJ MOSFET device to reduce the distance between the gate trench and the vias, and the gate bottom oxide layer is thickened to reduce on-resistance and improve shock resistance.
By reducing the distance between the gate trench and the connection hole, the on-resistance is reduced, the current distribution uniformity and device reliability are improved, and the thickened gate bottom oxide layer improves the device's shock resistance.
Smart Images
Figure CN224306191U_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of semiconductor technology, specifically relating to an SJ MOSFET device with low on-resistance. Background Technology
[0002] SJ MOSFET, or Super Junction MOSFET (SJ-MOS), is a high-voltage power device that overcomes the "silicon limit" of traditional silicon-based power devices through charge compensation technology. Its core design lies in the special structure of the drift region, which optimizes the electric field through alternating P-type and N-type semiconductor pillars, thereby achieving a balance between low on-resistance (Rds(on)) and high breakdown voltage (BV).
[0003] Figure 1 As shown, an SJ MOSFET device includes a drift region formed by alternating N-type pillars 101 and P-type pillars 102, a gate trench 103 on the N-type pillars 101 of the drift region, a gate polysilicon layer 104, a gate oxide dielectric layer 105, a body region 106, a source region (N+) 107, an inter-dielectric layer (ILD) 108, a via 109, and a metal layer 110.
[0004] The SJ MOSFET device has a large cell size, and the size of the connection hole should not be too large in the process. However, there is only one connection hole between two adjacent gate trenches, which makes the distance between the gate trench and the connection hole very long, adding extra on-resistance to the SJ MOSFET device. Utility Model Content
[0005] To address the technical problem that the long distance between the gate trench and the connection hole in existing SJ MOSFET devices increases the on-resistance of the device, the purpose of this invention is to provide an SJ MOSFET device with low on-resistance.
[0006] The low on-resistance SJ MOSFET device of this invention includes:
[0007] An epitaxial layer, wherein the epitaxial layer is provided longitudinally with at least two first conductivity type pillars and at least one second conductivity type pillar, wherein the first conductivity type pillars and the second conductivity type pillars are arranged at intervals;
[0008] At least two gate trenches, the gate trenches being located on the epitaxial layer and corresponding to the upper part of the first conductivity type pillar;
[0009] At least two connection holes, with the at least two connection holes spaced apart between the two gate trenches.
[0010] Preferably, the low on-resistance SJ MOSFET device further includes:
[0011] A body region, wherein the body region is located on the epitaxial layer;
[0012] A source region, wherein the source region is located above the body region;
[0013] The gate trench passes through the source region and the body region and extends into the first conductivity type pillar of the epitaxial layer;
[0014] The connection hole passes through the source region and extends into the body region.
[0015] Preferably, there are three connecting holes instead of two, and more preferably, the three connecting holes are equidistantly spaced between the two grid trenches.
[0016] Preferably, the low on-resistance SJ MOSFET device further includes:
[0017] A dielectric isolation layer is located above the source region and the gate trench, and the connection hole also passes through the dielectric isolation layer.
[0018] Preferably, the low on-resistance SJ MOSFET device comprises:
[0019] The gate polysilicon is filled within the gate trench.
[0020] Preferably, the bottom of the gate trench is provided with a gate bottom oxide layer, and the sidewall of the gate trench is provided with a gate side oxide layer, wherein the thickness of the gate bottom oxide layer is greater than the thickness of the gate side oxide layer.
[0021] Preferably, the thickness of the gate bottom oxide layer to the thickness of the gate side oxide layer is 2 to 4.5:1, preferably 3 to 4:1, and more preferably 3.75:1.
[0022] Preferably, the low on-resistance SJ MOSFET device comprises:
[0023] A metal layer is located above the dielectric isolation layer and the connection hole.
[0024] Preferably, the first conductive type pillar and the second conductive type pillar have opposite conductivity types. Preferably, a thin drift layer is provided under the epitaxial layer. Or preferably, the first conductive type pillar is an N-type pillar and the second conductive type pillar is a P-type pillar.
[0025] Preferably, the body region is a P-type body region.
[0026] The shock-resistant SJ MOSFET device of this invention includes:
[0027] An epitaxial layer, wherein the epitaxial layer is provided longitudinally with at least two first conductivity type pillars and at least one second conductivity type pillar, wherein the first conductivity type pillars and the second conductivity type pillars are arranged at intervals;
[0028] At least two gate trenches are provided, each located on the epitaxial layer and corresponding to the upper part of the first conductivity type pillar. A gate bottom oxide layer is provided at the bottom of the gate trench, and a gate side oxide layer is provided on the sidewall of the gate trench. The thickness of the gate bottom oxide layer is greater than the thickness of the gate side oxide layer.
[0029] Preferably, the thickness of the gate bottom oxide layer to the thickness of the gate side oxide layer is 2 to 4.5:1, preferably 3 to 4:1, and more preferably 3.75:1.
[0030] Preferably, the shock-resistant SJ MOSFET device comprises:
[0031] A gate polysilicon is filled in the gate trench, and the gate polysilicon is located on the gate bottom oxide layer.
[0032] Preferably, the shock-resistant SJ MOSFET device comprises:
[0033] A body region, wherein the body region is located on the epitaxial layer;
[0034] A source region, wherein the source region is located above the body region;
[0035] The gate trench passes through the body region and the source region and extends into the first conductivity type pillar.
[0036] Preferably, the gate bottom oxide layer is located within the first conductivity type pillar of the epitaxial layer, and more preferably, the gate polysilicon also extends into the first conductivity type pillar of the epitaxial layer.
[0037] Preferably, the shock-resistant SJ MOSFET device comprises:
[0038] A dielectric isolation layer is located above the source region and the gate trench.
[0039] Preferably, the shock-resistant SJ MOSFET device comprises:
[0040] A connection hole is located between the two gate trenches, the connection hole passes through the dielectric isolation layer and the source region and extends into the body region.
[0041] Preferably, the shock-resistant SJ MOSFET device comprises:
[0042] A metal layer is located above the dielectric isolation layer and the connection hole.
[0043] Preferably, the first conductive type pillar and the second conductive type pillar have opposite conductivity types. Preferably, a thin drift layer is provided under the epitaxial layer. Or preferably, the first conductive type pillar is an N-type pillar and the second conductive type pillar is a P-type pillar.
[0044] Preferably, the body region is a P-type body region.
[0045] The method for fabricating the high FOM performance SJ MOSFET device of this invention includes the following steps:
[0046] Step S1: Etch pillar trenches on the epitaxial wafer and fill the pillar trenches to form alternating first conductivity type pillars and second conductivity type pillars;
[0047] Step S2: Etch a gate trench at the center of the upper part of the first conductive type pillar;
[0048] Step S3: Fill the gate trench with oxide and etch to form a gate bottom oxide layer;
[0049] Step S4: A gate oxide is grown on the bottom gate oxide layer in the gate trench and a gate side oxide layer is etched to form a gate side oxide layer, wherein the thickness of the bottom gate oxide layer is greater than the thickness of the gate side oxide layer.
[0050] Step S5: Grow gate polysilicon in the gate trench and etch it back;
[0051] Step S6: Ion implantation and well-pushing diffusion formation are performed on the upper part of the first and second conductive type columns;
[0052] Step S7: Continue ion implantation and well-pushing diffusion in the upper part of the body region to form a source region;
[0053] Step S8: A dielectric isolation layer is grown and etched back on the upper surface of the source region;
[0054] Step S9: Etch at least two connection holes between the dielectric isolation layer and the gate trench;
[0055] Step S10: Fill the connection hole and deposit a metal layer on the dielectric isolation layer and the connection hole.
[0056] Preferably, the pillar trench is formed by etching in the middle of the epitaxial layer, and two first-type pillars are formed on both sides of the pillar trench. A second-type pillar is formed by filling the pillar trench with polysilicon doped with heteroatoms. Preferably, the first-type pillar and the second-type pillar have opposite conductivity types. More preferably, the first-type pillar is an N-type pillar and the second-type pillar is a P-type pillar formed by filling with P-type polysilicon. Preferably, the wafer of the epitaxial layer is of the first conductivity type.
[0057] Preferably, in step S1, the opening size of the column groove is 2.80μm to 3.20μm, preferably 2.90μm to 3.10μm, more preferably 3.00μm; the depth of the column groove is 22.00μm to 26.00μm, preferably 23.00μm to 25.00μm, more preferably 24.00μm.
[0058] Preferably, in step S1, the doping concentration of the P-type pillar is higher than that of the N-type pillar. More preferably, the doping concentration of the P-type pillar is 2.8-3.2% higher than that of the N-type pillar, and more preferably, the doping concentration of the P-type pillar is 3% higher than that of the N-type pillar. The doping concentration of the N-type pillar is 1.1875E+16 to 1.3125E+16, preferably 1.2125E+16 to 1.2875E+16, and more preferably 1.25E+16. Preferably, the P-type pillar is doped with boron (B), and the N-type pillar is doped with phosphorus (P).
[0059] Preferably, in step S2, the opening width of the gate trench is 0.90μm to 1.10μm, preferably 0.95μm to 1.05μm, more preferably 1.00μm, and the depth of the gate trench is 1.40μm to 1.60μm, preferably 1.45μm to 1.55μm, more preferably 1.50μm.
[0060] Preferably, step S3 specifically includes:
[0061] Step S31, using a temperature of 800℃~950℃ (preferably 950℃) for thermo-oxidative growth to a thickness of [missing value]. Preferred Linear oxide layer;
[0062] Step S32: Fill SiO2 thin film by SACVD;
[0063] In step S33, after being smoothed by chemical mechanical polishing and grinding, a gate bottom oxide layer is formed at the bottom of the gate trench by wet etching. Preferably, the thickness of the gate bottom oxide layer is 0.25μm to 0.35μm, and more preferably 0.3μm.
[0064] Preferably, in step S4, the growth temperature of the gate oxide is 1000℃~1100℃, preferably 1050℃, and the thickness of the gate-side oxide layer after etching is... Preferably
[0065] Preferably, in step S6, the concentration of ion implantation in the body region is 2.5E+13, and more preferably, the ion implantation in the body region is B ion implantation; in step S7, the concentration of ion implantation in the source region is 5.0E+15, and more preferably, the ion implantation in the source region is As ion implantation.
[0066] Preferably, in step S9, the opening width of the connecting hole is 0.45μm to 0.80μm.
[0067] Preferably, in step S9, the spacing between the connecting hole and the edge of the gate trench is at least greater than 120 nm and less than 925 nm.
[0068] Preferably, in step S9, the connecting holes between the two gate trenches are symmetrically arranged at equal intervals.
[0069] The positive and progressive effects of this utility model are as follows:
[0070] 1) The SJ MOSFET device of this utility model has multiple connection holes between the gate trenches. On the one hand, it can reduce the distance between the gate trenches and the connection holes, thereby reducing the on-resistance Rdson. On the other hand, when the body diode of the device is forward freewheeling, the current can be more evenly distributed in the body, improving the freewheeling capability and thus improving the reliability of the device.
[0071] 2) The SJ MOSFET device of this invention has a thicker gate bottom oxide layer, which is 2 to 4.5 times thicker than the existing gate bottom oxide layer. This makes the thickness of the gate bottom oxide layer greater than the thickness of the gate side oxide layer, thereby reducing the junction capacitance. The bottom of the gate trench is the position where the electric field strength in the Y direction of the device is the highest. This thick gate bottom oxide layer can improve the device's shock resistance and thus improve the device's reliability. Attached Figure Description
[0072] The disclosure of this utility model will become more apparent with reference to the accompanying drawings. It should be understood that these drawings are for illustrative purposes only and are not intended to limit the scope of protection of this utility model. In the drawings:
[0073] Figure 1 This is a cross-sectional schematic diagram of an SJ MOSFET device in the prior art;
[0074] Figure 2 This is a cross-sectional schematic diagram of the present invention;
[0075] Figure 3 This is a process flow diagram of this utility model. Detailed Implementation
[0076] The following specific examples illustrate the implementation of this utility model. Those skilled in the art can easily understand other advantages and effects of this utility model from the content disclosed in this specification. This utility model can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of this utility model.
[0077] It should be noted that, unless otherwise specified, the following embodiments and features can be combined with each other.
[0078] In the description of this utility model, it should be noted that the directional terms such as "above", "above", "upper part", "inner", "outer", etc., indicate the orientation and positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this utility model and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. They should not be construed as limiting the specific protection scope of this utility model.
[0079] Reference Figure 2 This utility model provides an SJ MOSFET device, comprising:
[0080] At least two first conductivity type pillars 201, for example, N-type pillars (N-Pillar);
[0081] At least one second conductivity type pillar 202, such as a P-pillar, is arranged longitudinally alternately with the first conductivity type pillar 201 to form an epitaxial layer. The first and second conductivity type pillars have opposite conductivity types. In some embodiments (not shown), a thin drift layer, such as an N-type drift layer, is further provided below the epitaxial layer.
[0082] That is, there is a second conductive type post 202 between two adjacent first conductive type posts 201, or there is a first conductive type post between two adjacent second conductive type posts. The first conductive type post and the second conductive type post have the same width and depth, with a width of 2.80μm to 3.20μm, preferably 2.90μm to 3.10μm, more preferably 3.00μm; and a depth of 22.00μm to 26.00μm, preferably 23.00μm to 25.00μm, more preferably 24.00μm.
[0083] In some embodiments, refer to Figure 2Two first conductivity type pillars 201, such as N-type pillars, are arranged longitudinally on the outer side of the epitaxial layer, and two second conductivity type pillars 202 are arranged longitudinally between the two first conductivity type pillars 201. The P-type pillars are doped with boron (B), and the N-type pillars are doped with phosphorus (P). The doping concentration of the P-type pillars is higher than that of the N-type pillars. Preferably, the doping concentration of the P-type pillars is 2.8–3.2% higher than that of the N-type pillars; more preferably, the doping concentration of the P-type pillars is 3% higher than that of the N-type pillars. The doping concentration of the N-type pillars is 1.1875E+16–1.3125E+16, preferably 1.2125E+16–1.2875E+16, and more preferably 1.25E+16.
[0084] P-body 203, for example, is a P-type body region, and body region 203 is located on the epitaxial layer;
[0085] Source region 204, for example, is an N+ active region, and source region 204 is located above body region 203;
[0086] At least two gate trenches 205 are located on the epitaxial layer and correspondingly on the upper part of the first conductivity type pillar 201. Further, the gate trenches 205 pass through the source region 204 and the body region 203 and extend into the first conductivity type pillar 201. The opening width of the gate trenches 205 is 0.90 μm to 1.10 μm, preferably 0.95 μm to 1.05 μm, more preferably 1.00 μm, and the depth of the gate trenches is 1.40 μm to 1.60 μm, preferably 1.45 μm to 1.55 μm, more preferably 1.50 μm.
[0087] A gate bottom oxide layer 206 is provided at the bottom of the gate trench 205, and a gate side oxide layer 207 is provided on the sidewall of the gate trench 205. The gate bottom oxide layer 206 is located within the first conductivity type pillar 201 of the epitaxial layer. The thickness of the gate bottom oxide layer 206 is greater than the thickness of the gate side oxide layer 207, while the thickness of the gate side oxide layer 207 is approximately equivalent to the thickness of the gate oxide layer in the prior art.
[0088] In some embodiments, refer to Figure 2 The thickness of the gate bottom oxide layer 206 to the thickness of the gate side oxide layer 207 is 2–4.5:1, preferably 3–4:1, and more preferably 3.75:1. Specifically, the thickness of the gate bottom oxide layer 206 is 0.25 μm to 0.35 μm, preferably 0.3 μm. The thickness of the gate side oxide layer 207 is… Preferably
[0089] This invention increases the thickness of the gate bottom oxide layer 206 at the bottom of the gate trench 205 compared to the thickness of the gate oxide layer in the prior art (which is comparable to the thickness of the gate side oxide layer 207), thereby reducing the junction capacitance of the SJMOSFET device and improving the device's shock resistance and reliability.
[0090] The SJ MOSFET device also includes a gate polysilicon 208, which fills the gate trench 205 and is located on the bottom gate oxide layer 206 and within the gate side oxide layer 207. The gate polysilicon 208 may also extend into the first conductivity type pillar 201 of the epitaxial layer.
[0091] The SJ MOSFET device also includes a dielectric isolation layer (ILD) 209, which is located above the source region 204 and the gate trench 205.
[0092] The SJ MOSFET device also includes a connection hole (CT) 210, which is located between two gate trenches 205, passes through the dielectric isolation layer 209 and the source region 204 and extends into the body region 203.
[0093] In some embodiments, refer to Figure 2 At least two connection holes 210 are spaced apart between the two gate trenches 205. By providing multiple connection holes 210 between the two gate trenches 205, the distance between the gate trenches 205 and the connection holes 210 can be reduced, thereby reducing the on-resistance. On the other hand, when the device body diode is forward-biased, the current can be more evenly distributed within the device, improving the freewheeling capability and thus improving the reliability of the device.
[0094] In this invention, there are at least two connection holes 210, or three connection holes 210. Further, the three connection holes 210 are equidistantly spaced between the two gate trenches 205. Preferably, the connection holes (CT) 210 between the two symmetrical gate trenches 205 are symmetrically arranged. The opening width (CD) of the connection holes 210 is 0.45μm to 0.80μm. Too small an opening width will reduce the device's EAS capability, while too large an opening width will make subsequent W (tungsten) backfilling more difficult. The spacing between the connection holes 210 and the edge of the gate trench 205 must be at least greater than 120nm. Too close a distance will lead to leakage current and excessive current density, causing premature avalanche breakdown. To ensure process margin, a minimum distance must be maintained between the three connection holes 210, i.e., the spacing between the connection holes 210 and the edge of the gate trench 205 must be less than 925nm.
[0095] The SJ MOSFET device also includes a metal layer 211, which is located above the dielectric isolation layer 209 and the connection hole 210.
[0096] In some embodiments, refer to Figure 3 The following steps can be used to fabricate the high FOM performance SJ MOSFET device of this invention:
[0097] Step S1: A pillar trench 212 with an opening size of 3.00 μm and a depth of 24.00 μm is etched on the epitaxial layer wafer. The epitaxial layer is a pre-grown first-conductivity type epitaxial layer, such as an N-type epitaxial layer. After etching the pillar trench 212 in the middle of the first-conductivity type epitaxial layer, two first-conductivity type pillars 201, such as N-type pillars, are formed on both sides of the pillar trench 212. A second-conductivity type pillar 202 is formed by filling the pillar trench 212 between the two first-conductivity type pillars 201 with heteroatom-doped polysilicon, such as a P-type pillar formed by filling P-type polysilicon, thus forming alternating first-conductivity type pillars 201 and second-conductivity type pillars 202. The concentration of P-type pillars is 3% higher than that of N-type pillars.
[0098] Step S2: A gate trench 205 with an opening width of 1.00 μm and a depth of 1.50 μm is etched at the center of the upper part of the N-type pillar.
[0099] Step S3 involves filling the gate trench 205 with oxide and etching to form the gate bottom oxide layer 206. Specifically, this includes:
[0100] In step S31, a thermo-oxidative growth process is performed at a temperature of 800℃~950℃, preferably 950℃, to a thickness of [missing information]. Preferred For linear oxide layers, it is important to note that the growth temperature should not exceed 950℃ and the thickness should not be too thin, otherwise excessive stress may be introduced.
[0101] In step S32, SiO2 thin film is filled by SACVD.
[0102] In step S33, after being smoothed by chemical mechanical polishing, a gate bottom oxide layer 206 with a thickness of 0.3 μm is formed at the bottom of the gate trench 205 by wet etching.
[0103] Step S4: A gate oxide is grown on the gate bottom oxide layer 206 within the gate trench 205 at a temperature of 1000℃~1100℃, preferably 1050℃, and etched to form a thickness of... The gate-side oxide layer 207.
[0104] Step S5: Grow gate polysilicon 208 on the gate bottom oxide layer 206 and the gate side oxide layer 207 in the gate trench 205 and etch it back;
[0105] Step S6: Ion implantation and well-diffusion formation of body region 203 are performed on the upper part of the first conductivity type column 201 (e.g., N-type column) and the second conductivity type column 202 (e.g., P-type column). The body region is implanted with B ions and the ion implantation concentration is 2.5E+13.
[0106] Step S7: Continue ion implantation and well-diffusion in the upper part of the body region 203 to form the source region 204. The ion implantation in the source region is As ion implantation, and the ion implantation concentration is 5.0E+15.
[0107] Step S8: A dielectric isolation layer 209 is grown and etched back on the upper surface of the source region 204;
[0108] In step S9, three connecting holes 210 are symmetrically etched at equal intervals between the two gate trenches 205 on the dielectric isolation layer 209, wherein the opening width of the connecting holes is 0.45μm to 0.80μm.
[0109] Step S10: Fill the connection hole 210 and deposit a metal layer 211 on the dielectric isolation layer 209 and the connection hole 210.
[0110] The present invention has been described in detail above with reference to the accompanying drawings and embodiments. Those skilled in the art can make various modifications to the present invention based on the above description. Therefore, certain details in the embodiments should not be construed as limiting the present invention, and the scope of protection of the present invention shall be defined by the appended claims.
Claims
1. A low on-resistance SJ MOSFET device, characterized in that, The low on-resistance SJ MOSFET device includes: An epitaxial layer, wherein the epitaxial layer is provided longitudinally with at least two first conductivity type pillars and at least one second conductivity type pillar, wherein the first conductivity type pillars and the second conductivity type pillars are arranged at intervals; At least two gate trenches, the gate trenches being located on the epitaxial layer and corresponding to the upper part of the first conductivity type pillar; At least two connection holes, with the at least two connection holes spaced apart between the two gate trenches.
2. The low on-resistance SJ MOSFET device as described in claim 1, characterized in that, The low on-resistance SJ MOSFET device also includes: A body region, wherein the body region is located on the epitaxial layer; A source region, wherein the source region is located above the body region; The gate trench passes through the source region and the body region and extends into the first conductivity type pillar of the epitaxial layer; The connection hole passes through the source region and extends into the body region.
3. The low on-resistance SJ MOSFET device as described in claim 1, characterized in that, The at least two connection holes are three.
4. The low on-resistance SJ MOSFET device as described in claim 3, characterized in that, The three connecting holes are equidistantly spaced between the two gate trenches.
5. The low on-resistance SJ MOSFET device as described in claim 2, characterized in that, The low on-resistance SJ MOSFET device also includes: A dielectric isolation layer is located above the source region and the gate trench, and the connection hole also passes through the dielectric isolation layer.
6. The low on-resistance SJ MOSFET device as described in claim 1, characterized in that, The low on-resistance SJ MOSFET device includes: The gate polysilicon is filled within the gate trench.
7. The low on-resistance SJ MOSFET device as described in claim 6, characterized in that, The bottom of the gate trench is provided with a gate bottom oxide layer, and the sidewall of the gate trench is provided with a gate side oxide layer. The thickness of the gate bottom oxide layer is greater than the thickness of the gate side oxide layer.
8. The low on-resistance SJ MOSFET device as described in claim 7, characterized in that, The thickness of the gate bottom oxide layer is 2~4.5:1 compared to the thickness of the gate side oxide layer.
9. The low on-resistance SJ MOSFET device as described in claim 8, characterized in that, The thickness of the gate bottom oxide layer is 3~4:1 compared to the thickness of the gate side oxide layer.
10. The low on-resistance SJ MOSFET device as described in claim 8, characterized in that, The thickness of the gate bottom oxide layer is 3.75:1 compared to the thickness of the gate side oxide layer.
11. The low on-resistance SJ MOSFET device as described in claim 5, characterized in that, The low on-resistance SJ MOSFET device includes: A metal layer is located above the dielectric isolation layer and the connection hole.
12. The low on-resistance SJ MOSFET device as described in claim 1, characterized in that, The first and second conductivity type pillars have opposite conductivity types.
13. The low on-resistance SJ MOSFET device as described in claim 1, characterized in that, The epitaxial layer has a thin drift layer underneath.
14. The low on-resistance SJ MOSFET device as described in claim 12, characterized in that, The first conductive type column is an N-type column, and the second conductive type column is a P-type column.
15. The low on-resistance SJ MOSFET device as described in claim 2, characterized in that, The body region is a P-type body region.