PN shallow junction composite termination of silicon carbide vdmos
By introducing a PN shallow junction composite termination structure into silicon carbide VDMOS devices, the problem of electric field concentration is alleviated, the risk of breakdown is reduced, and the withstand voltage capability and compact structural design are achieved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- GLOBAL POWER TECH CO LTD
- Filing Date
- 2025-04-24
- Publication Date
- 2026-05-29
AI Technical Summary
Traditional silicon carbide VDMOS devices have a high risk of breakdown due to electric field concentration at the edges, and require many field limiting rings to achieve withstand voltage, resulting in wasted area.
A PN shallow junction composite termination structure is adopted, including a P+ well region, a first P+ doped region, a PN shallow junction, an insulating dielectric region, a capacitor metal layer, and a high resistivity conductor layer. By constructing the PN shallow junction and the insulating dielectric region, the electric field concentration is alleviated, and a uniform electric field distribution is achieved.
It effectively reduces the peak electric field at the device edge, avoids breakdown, saves the width of the terminal structure, and improves the withstand voltage capability.
Smart Images
Figure CN224306199U_ABST
Abstract
Description
Technical Field
[0001] This utility model relates to a PN shallow junction composite terminal of silicon carbide VDMOS. Background Technology
[0002] Silicon carbide VDMOS is a typical example of silicon carbide power devices, and it has wide applications in electric vehicles, aerospace, power conversion and other fields.
[0003] Based on the device structure design, the electric field concentration occurs in the lateral direction due to the lateral distribution of the electric field at the edge of the repeating cell, which leads to the breakdown phenomenon at the edge of the device. Traditional cells use field confinement ring structures with the same doping concentration to suppress the electric field concentration. Since the doping concentration and spacing of the field confinement rings are equal, the electric field intensity distribution gradually decreases, and there are still differences in the electric field distribution. The risk of breakdown is still high in the region near the P+ well region, and more field confinement rings are needed to achieve the withstand voltage of the device terminal, which requires sacrificing area for withstand voltage. Utility Model Content
[0004] The technical problem to be solved by this utility model is to provide a PN shallow junction composite terminal for silicon carbide VDMOS, which avoids the problem of high process difficulty in realizing deep trench terminals, and saves the width of the terminal structure while ensuring the voltage withstand capability of the terminal.
[0005] This invention provides a PN shallow junction recombination termination for a silicon carbide VDMOS, comprising:
[0006] silicon carbide substrate,
[0007] A drift layer is provided, the lower side of which is connected to the upper side of the silicon carbide substrate; the drift layer is provided with a P+ well region, a first P+ doped region, at least three PN shallow junctions and a cutoff ring contact region, the PN shallow junctions are located between the first P+ doped region and the cutoff ring contact region, and the left PN shallow junction is connected to the right side of the first P+ doped region, the right PN shallow junction is connected to the left side of the cutoff ring contact region, and the left side of the first P+ doped region is connected to the right side of the P+ well region; an insulating dielectric region is provided in the first P+ doped region.
[0008] An insulating layer, the lower side of which is connected to the insulating dielectric region, the first P+ doped region, and the PN shallow junction, and the insulating layer is provided with at least three trenches;
[0009] A capacitor metal layer is disposed within the trench and is located directly above the PN shallow junction.
[0010] A source metal layer, wherein the source metal layer is connected to the P+ well region and the first P+ doped region respectively;
[0011] A stop ring metal layer, the stop ring metal layer being connected to the stop ring contact area;
[0012] A high resistivity conductor layer is provided, which is connected to the insulating layer, the capacitor metal layer, the source metal layer, and the cutoff ring metal layer, respectively.
[0013] The advantages of this utility model are:
[0014] I. This utility model constructs a first P+ doped region next to the P+ well region, which surrounds the insulating dielectric region, pushing the electric field of the main junction into the device, thereby alleviating the concentration of the electric field of the main junction of the device.
[0015] II. This invention constructs a PN shallow junction, which includes a second P+ doped region and an N- doped region. The shallow junction constructed by the second P+ doped region and the drift layer can prevent the field confinement ring from being depleted prematurely, and after depletion, it provides more negative charge to share the electric field of the main junction and the previous PN shallow junction. The N- doped region reduces the doping concentration on the right side of the field confinement ring, thereby reducing the peak electric field on the right side of the PN shallow junction and preventing premature breakdown.
[0016] Third, this utility model constructs a high resistivity conductor layer and a capacitor metal layer. The high resistivity conductor layer realizes a uniform voltage distribution from the source metal layer to the cutoff ring metal layer, thereby realizing a uniform electric field distribution between the PN shallow junctions. The capacitor metal layer and the insulating layer can increase the capacitance effect through a thinner insulating layer, thereby improving the capacitance effect of the N-doped region. Attached Figure Description
[0017] The present invention will be further described below with reference to the accompanying drawings and embodiments.
[0018] Figure 1 This is a schematic diagram of a PN shallow junction composite terminal of a silicon carbide VDMOS according to the present invention.
[0019] Figure 2 This is a cross-sectional view of the process of a silicon carbide VDMOS PN shallow junction composite terminal according to the present invention. Figure 1 .
[0020] Figure 3 This is a cross-sectional view of the process of a silicon carbide VDMOS PN shallow junction composite terminal according to the present invention. Figure 2 .
[0021] Figure 4 This is a cross-sectional view of the process of a silicon carbide VDMOS PN shallow junction composite terminal according to the present invention. Figure 3 .
[0022] Figure 5 This is a cross-sectional view of the process of a silicon carbide VDMOS PN shallow junction composite terminal according to the present invention. Figure 4 .
[0023] Figure 6 This is a cross-sectional view of the process of a silicon carbide VDMOS PN shallow junction composite terminal according to the present invention. Figure 5 .
[0024] Figure 7 This is a cross-sectional view of the process of a silicon carbide VDMOS PN shallow junction composite terminal according to the present invention. Figure 6 .
[0025] Figure 8 This is a cross-sectional view of the process of a silicon carbide VDMOS PN shallow junction composite terminal according to the present invention. Figure 7 .
[0026] Figure 9 This is a cross-sectional view of the process of a silicon carbide VDMOS PN shallow junction composite terminal according to the present invention. Figure 8 .
[0027] Figure 10 This is a cross-sectional view of the process of a silicon carbide VDMOS PN shallow junction composite terminal according to the present invention. Figure 9 .
[0028] Figure 11 This is a cross-sectional view of the process of a silicon carbide VDMOS PN shallow junction composite terminal according to the present invention. Figure 10 .
[0029] Figure 12 This is a cross-sectional view of the process of a silicon carbide VDMOS PN shallow junction composite terminal according to the present invention. Figure 10 one.
[0030] Figure 13 This is a cross-sectional view of the process of a silicon carbide VDMOS PN shallow junction composite terminal according to the present invention. Figure 10 two. Detailed Implementation
[0031] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings, which illustrate embodiments of the present application. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of this application will be thorough and complete.
[0032] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.
[0033] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "in contact with," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, regions, layers, doping types, and / or portions, these elements, components, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type, or portion from another element, component, region, layer, doping type, or portion. Therefore, without departing from the teachings of this utility model, the first element, component, region, layer, doping type, or portion discussed below may be referred to as a second element, component, region, layer, or portion.
[0034] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein to describe the relationship between one element or feature shown in the figures and other elements or features. It should be understood that, in addition to the orientations shown in the figures, spatial relation terms also include different orientations of the device in use and operation. For example, if the device in the figures is flipped, an element or feature described as “below,” “under,” or “below” other elements or features would be oriented “above” other elements or features. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. Furthermore, the device may also include other orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptive terms used herein are interpreted accordingly.
[0035] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising / including” or “having,” etc., specify the presence of the stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not preclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. Meanwhile, in this specification, the term “and / or” includes any and all combinations of the associated listed items.
[0036] like Figure 1 As shown, this application embodiment provides a PN shallow junction recombination terminal for a silicon carbide VDMOS, including:
[0037] Silicon carbide substrate 1,
[0038] A drift layer 2 is provided, the lower side of which is connected to the upper side of the silicon carbide substrate 1. The drift layer 2 is provided with a P+ well region 21, a first P+ doped region 22, at least three PN shallow junctions 23, and a cutoff ring contact region 24. The PN shallow junctions 23 are located between the first P+ doped region 22 and the cutoff ring contact region 24, and the left PN shallow junction 23 is connected to the right side of the first P+ doped region 22, and the right PN shallow junction 23 is connected to the left side of the cutoff ring contact region 24. The left side of the first P+ doped region 22 is connected to the right side of the P+ well region 21. An insulating dielectric region 221 is provided in the first P+ doped region 22.
[0039] Insulating layer 3, the lower side of which is connected to insulating dielectric region 221, first P+ doped region 22 and PN shallow junction 23 respectively, and at least three trenches 31 are provided on the insulating layer;
[0040] A capacitor metal layer 4 is disposed in the trench 31 and is located directly above the PN shallow junction 23.
[0041] Source metal layer 5, which is connected to P+ well region 21 and first P+ doped region 22 respectively;
[0042] A stop ring metal layer 6 is connected to the stop ring contact area 24.
[0043] A high resistivity conductor layer 7 is connected to the insulating layer 3, the capacitor metal layer 4, the source metal layer 5, and the cutoff ring metal layer 6, respectively.
[0044] Drain metal layer 8, which is connected to the lower side of silicon carbide substrate 1.
[0045] In this embodiment, preferably, the PN shallow junction 23 includes a second P+ doped region 231 and an N- doped region 232. The left side of the second P+ doped region 231 of the leftmost PN shallow junction 23 is connected to the right side of the first P+ doped region 22, and the right side of the N- doped region 232 of the rightmost PN shallow junction 23 is connected to the left side of the cutoff ring contact region 24. The second P+ doped region 231 and the N- doped region 232 are not in contact. The capacitor metal layer 4 is located directly above the N- doped region 232.
[0046] In this embodiment, preferably, the width of the second P+ doped region 231 and the width of the N- doped region 232 are both equal.
[0047] In this embodiment, preferably, the doping concentration of the first P+ doped region 22 is greater than the doping concentration of the second P+ doped region 231, and the doping concentration of the second P+ doped region 231 is greater than the doping concentration of the N- doped region 232.
[0048] In this embodiment, preferably, the thickness of the PN shallow junction 23 is greater than the thickness of the P+ well region 21, and the thickness of the PN shallow junction 23 is less than the thickness of the first P+ doped region 22.
[0049] In this embodiment, preferably, the thickness of the first P+ doped region 22 is greater than the thickness of the P+ well region 21.
[0050] like Figures 1 to 13 As shown, the method for preparing the above-mentioned terminal includes the following steps:
[0051] Step 1: Epitaxial growth is performed on silicon carbide substrate 1 to form drift layer 2;
[0052] Step 2: Form a barrier layer 9 above the drift layer 2, etch the barrier layer 9 to form a via, and implant ions to form the first P+ doped region 22;
[0053] Step 3: Remove the barrier layer 9 from Step 2, reform the barrier layer 9, etch the barrier layer 9 to form a via, and implant ions to form the P+ well region 21 and the stop ring contact region 24, respectively.
[0054] Step 4: Remove the barrier layer 9 from Step 3, reform the barrier layer 9, etch the barrier layer 9 to form a via, and implant ions to form the second P+ doped region 231.
[0055] Step 5: Remove the barrier layer 9 from step 4, reform the barrier layer 9, etch the barrier layer 9 to form a via, implant ions to form an N-doped region 232, and the PN shallow junction 23 includes a second P+ doped region 231 and an N-doped region 232.
[0056] Step 6: Remove the barrier layer 9 from step 5, reform the barrier layer 9, etch the barrier layer to form a via, etch the first P+ doped region 22 to form a groove 222, and deposit the insulating medium to form the insulating medium region 221.
[0057] Step 7: Remove the barrier layer 9 from step 6, reform the barrier layer 9, etch the barrier layer 9 to form vias, and deposit to form the insulating layer 3;
[0058] Step 8: Remove the barrier layer 9 from step 7, reform the barrier layer 9, etch the barrier layer 9 to form a via, and etch the insulating layer 3 to form at least three trenches 31. Deposit metal to form a capacitor metal layer 4.
[0059] Step 9: Remove the barrier layer 9 from step 8, reform the barrier layer 9, etch the barrier layer 9 to form vias, and deposit to form a high resistivity conductor layer 7.
[0060] Step 10: Remove the barrier layer 9 from step 9, reform the barrier layer 9, etch the barrier layer 9 to form a via, deposit metal to form the source metal layer 5 and the cutoff ring metal layer 6, and remove the barrier layer 9.
[0061] In another embodiment of this invention, the doping concentration of the N-type silicon carbide substrate 1 is 2-8e18cm. -3 The doping concentration of the N-type drift layer 2 is 5-9e16cm. -3 The doping concentration of the first P+ doped region 22 is 1-5e18cm. -3 The doping concentration of P+ well region 21 is 5-8e18cm. -3 The doping concentration of the stop ring contact region 24 is 5-8e18cm. -3 The doping concentration of the second P+ doped region 231 is 1-5e17cm. -3 The doping concentration of the N-doped region 232 is 1-5e15cm. -3 The insulating layer 3 can be made of silicon dioxide, the insulating dielectric region 221 can be made of silicon dioxide or a certain insulating material with a dielectric constant less than silicon dioxide, the high resistivity conductor layer 7 can be made of SIPOS material or low-doped polycrystalline silicon, and the source metal layer 5, the stop ring metal 6 and the capacitor metal layer 4 can be made of one or an alloy of several metals, such as Al, Cu and Ni.
[0062] Among them, the doping concentration of N-type silicon carbide substrate 1, N-type drift layer 2, and P+ well region 21 is considered in the traditional design structure of planar gate silicon carbide VDMOS device. The doping concentration of the second P+ doped region 231 and N- doped region 232 is the basis for realizing the voltage divider standard cell. The doping concentration of the first P+ doped region 22 is to ensure that the main junction is not broken down and to avoid defects caused by etching and deposition of insulating medium that lead to device reliability.
[0063] In the terminal structure, the width (d1+w1) of the first P+ doped region 22 is 5μm, the maximum depth of the P+ well region 21 is 600nm, and the depth of the first P+ doped region 22 is 2μm, where w1 is 500nm. This is to avoid separation of the two regions due to process errors, which would affect the terminal breakdown voltage characteristics of the device. The widths of the first P+ doped regions 22 on both sides of the insulating dielectric region 221 are equal. This is because the electric field concentration at the main junction is the most severe, and the risk of breakdown is the highest. It is necessary to laterally extend the electric field strength of the main junction through the first P+ doped region 22. The width of the insulating dielectric region 221 is 4μm, and the thickness is 1.5μm. The width w of the second P+ doped region 231 and the N- doped region 232 are both 1μm, and the depth is 800nm. The distance from the second P+ doped region 231 to the N- doped region 232 (and from the N- doped region 232 to the first P+ doped region 232) is 5μm. The distance w2 between the two P+ doped regions 231 (equidistant) is 500nm-1μm. The width of the second P+ doped region 231 and the distance between the N- doped region 232 are to ensure a minimum voltage division and withstand voltage characteristics of 200V. The maximum thickness of the insulating layer 3 is 200nm. The thickness of the insulating layer 3 below the capacitor metal layer 4 is 100nm. This is to achieve a large capacitance effect while ensuring the withstand voltage characteristics of the insulating layer. The thickness of the capacitor metal layer 4 is 100nm and the width is 1.1μm. It is distributed directly above the N- doped region 232. This is to improve the capacitance effect of the N- doped region 232 and reduce the electric field concentration of the N- doped region 232. The number of voltage divider standard units can be increased or decreased according to different withstand voltage requirements. Increasing the number of voltage divider standard units can improve the withstand voltage. However, the change in withstand voltage requirements needs to be simulated and designed according to the overall structure of the device terminal.
[0064] The source metal layer 5 and the cutoff ring metal layer 6 are both 800 nm thick, and the high resistivity conductor layer 7 is 300 nm thick.
[0065] In this embodiment, a first P+ doped region 22 is constructed next to the P+ well region 21. The first P+ doped region 22 surrounds the insulating dielectric region 221, pushing the electric field of the main junction into the device, thereby alleviating the concentration of the electric field of the main junction of the device.
[0066] In this embodiment, a PN shallow junction 23 is constructed. The PN shallow junction 23 includes a second P+ doped region 231 and an N- doped region 232. The shallow junction constructed by the second P+ doped region 231 and the drift layer 2 can prevent the field confinement ring from being depleted prematurely and provide more negative charge after depletion to share the electric field of the main junction and the previous PN shallow junction 23. The N- doped region 232 reduces the doping concentration on the right side of the field confinement ring, thereby reducing the peak electric field on the right side of the PN shallow junction 23 and preventing premature breakdown.
[0067] In this embodiment, a high resistivity conductor layer 7 and a capacitor metal layer 4 are constructed. The high resistivity conductor layer 7 achieves a uniform voltage distribution from the source metal layer 5 to the cutoff ring metal layer 6, thereby achieving a uniform electric field distribution in the PN shallow junction 23. The capacitor metal layer 4 and the insulating layer 3 can increase the capacitance effect through the thinner insulating layer 3, thereby improving the capacitance effect of the N-doped region 232.
[0068] While specific embodiments of the present invention have been described above, those skilled in the art should understand that the specific embodiments described are merely illustrative and not intended to limit the scope of the present invention. Equivalent modifications and variations made by those skilled in the art in accordance with the spirit of the present invention should be covered within the scope of protection of the claims of the present invention.
Claims
1. A PN shallow junction recombination terminator for silicon carbide VDMOS, characterized in that: include: silicon carbide substrate, A drift layer, wherein the lower side of the drift layer is connected to the upper side of the silicon carbide substrate; The drift layer is provided with a P+ well region, a first P+ doped region, at least three PN shallow junctions, and a cutoff ring contact region. The PN shallow junctions are located between the first P+ doped region and the cutoff ring contact region, with the left PN shallow junction connected to the right side of the first P+ doped region and the right PN shallow junction connected to the left side of the cutoff ring contact region. The left side of the first P+ doped region is connected to the right side of the P+ well region. An insulating dielectric region is provided within the first P+ doped region. An insulating layer, the lower side of which is connected to the insulating dielectric region, the first P+ doped region, and the PN shallow junction, and the insulating layer is provided with at least three trenches; A capacitor metal layer is disposed within the trench and is located directly above the PN shallow junction. A source metal layer, wherein the source metal layer is connected to the P+ well region and the first P+ doped region respectively; A stop ring metal layer, the stop ring metal layer being connected to the stop ring contact area; A high resistivity conductor layer is provided, which is connected to the insulating layer, the capacitor metal layer, the source metal layer, and the cutoff ring metal layer, respectively.
2. The PN shallow junction recombination termination of a silicon carbide VDMOS as described in claim 1, characterized in that: The PN shallow junction includes a second P+ doped region and an N- doped region. The left side of the second P+ doped region of the leftmost PN shallow junction is connected to the right side of the first P+ doped region, and the right side of the N- doped region of the rightmost PN shallow junction is connected to the left side of the cutoff ring contact region. The second P+ doped region and the N- doped region are not in contact. The capacitor metal layer is located directly above the N- doped region.
3. The PN shallow junction recombination termination of a silicon carbide VDMOS as described in claim 2, characterized in that: The width of the second P+ doped region and the width of the N- doped region are both equal.
4. The PN shallow junction recombination termination of a silicon carbide VDMOS as described in claim 2, characterized in that: The doping concentration of the first P+ doped region is greater than that of the second P+ doped region, and the doping concentration of the second P+ doped region is greater than that of the N- doped region.
5. The PN shallow junction recombination termination of a silicon carbide VDMOS as described in claim 1, characterized in that: The thickness of the PN shallow junction is greater than the thickness of the P+ well region, and the thickness of the PN shallow junction is less than the thickness of the first P+ doped region.
6. The PN shallow junction recombination termination of a silicon carbide VDMOS as described in claim 1, characterized in that: The thickness of the first P+ doped region is greater than the thickness of the P+ well region.