Wake-up circuit and communication module

Abstract

The utility model relates to the field of circuit control provides a kind of wake-up circuit and communication module. By setting up MOS tube to cut off power supply circuit at power supply, to reduce the power consumption when battery management system is not plugged in charging gun;In the state of plugging charging gun, realize pulse wake-up function by low-power reset chip, low-power reset chip can effectively improve the delay time of wake-up pulse signal, ensure the success rate of battery management system being woken up in time, improve charging efficiency.

Description

Technical Field

[0001] This utility model relates to the field of circuit control technology, and in particular to a wake-up circuit and a communication module. Background Technology

[0002] In existing battery management system (BMS) designs, a resistor-based voltage divider combined with capacitor isolation is typically used to detect whether the charging gun is inserted. However, this approach has several significant drawbacks. First, when the charging gun is not inserted, the voltage divider resistor continuously consumes power from the vehicle's small battery, resulting in current consumption even with a relatively high resistance value. While a capacitor is introduced to assist in detection after the charging gun is inserted, the overall circuit still consumes current, which remains a considerable power burden for scenarios where charging is not performed for extended periods. Second, the capacitor pulse duration in the capacitor isolation scheme is affected by the capacitor's capacitance and the resistance of the cooperating resistor, and is typically short. However, the capacitor's capacitance is significantly affected by temperature and its lifespan. This short and uncertain pulse duration may prevent the BMS from being effectively woken up during the BMS's sleep cycle. Utility Model Content

[0003] This invention aims to at least partially solve one of the technical problems in related technologies. Therefore, the first objective of this invention is to provide a wake-up circuit that, when the battery is not plugged in, cuts off the power supply circuit by placing a MOSFET at the power supply point, reducing the power consumption of the battery management system. When the battery is plugged in, a low-power reset chip is used to implement a pulse wake-up function. The low-power reset chip can effectively improve the delay time of the wake-up pulse signal, ensuring the success rate of timely wake-up of the battery management system and improving charging efficiency.

[0004] The second objective of this invention is to provide a communication module.

[0005] To achieve the above objectives, the first aspect of this utility model proposes a wake-up circuit, comprising: a first switching unit, including a first MOSFET, the first MOSFET including a first gate, a first source, a first drain and a first pull-up resistor, the first gate being connected to a plug-in port for connecting a ground resistor, the first pull-up resistor being disposed between the first source and the first gate for pulling up the voltage of the first gate; a reset unit, including a reset input terminal, a reset output terminal and a ground terminal; the reset input terminal being connected to the first drain; a second switching unit, including a second MOSFET, the second MOSFET including a second gate, a second source, a second drain and a second pull-up resistor, the second gate being connected to the reset output terminal, the second pull-up resistor being disposed between the second source and the second gate for pulling up the voltage of the second gate; and a power management unit, including a wake-up input terminal and a power supply output terminal, the wake-up input terminal being connected to the second drain for receiving a high-level wake-up pulse, and the power supply output terminal being connected to the first source and the second source for providing a wake-up standby voltage to the first source and the second source.

[0006] In addition, the wake-up circuit according to the above embodiments of the present invention may also have the following additional technical features:

[0007] According to some embodiments of the present invention, when the plug-in port is not connected to a ground resistor, the first pull-up resistor is used to pull up the voltage of the first gate to be the same as the voltage of the first source, so as to turn off the first switching unit.

[0008] According to some embodiments of the present invention, when the first switching unit is turned off, the second pull-up resistor is used to pull up the voltage of the second gate to the same level as the voltage of the second source, so as to turn off the second switching unit.

[0009] According to some embodiments of the present invention, when a ground resistor is connected to the plug-in port, the ground resistor is used to control the first gate voltage to be less than the first source voltage so that the first switching unit is turned on; the first switching unit is used to supply power to the reset unit.

[0010] According to some embodiments of the present invention, when the reset unit is powered, the reset unit is used to control the reset output terminal to output zero voltage so that the voltage of the second gate is less than the voltage of the second source; the reset unit is also used to control the second switching unit to be turned on; the second switching unit is used to control the second drain to output a high-level wake-up pulse.

[0011] According to some embodiments of this utility model, when the time for the reset output terminal to output zero voltage reaches a preset time interval, the reset output terminal is used to control the reset output terminal to stop grounding; the reset output terminal is used to control the second switching unit to turn off; the second switching unit is used to control the second drain to stop outputting a high-level wake-up pulse.

[0012] According to some embodiments of the present invention, when the wake-up input terminal receives a high-level wake-up pulse, the wake-up input terminal is used to wake up the power management unit.

[0013] According to some embodiments of the present invention, a first protective resistor is provided between the first switching unit and the plug-in port.

[0014] According to some embodiments of the present invention, a second protection resistor is provided between the second switching unit and the reset unit.

[0015] According to the wake-up circuit provided by this utility model, the power supply circuit is cut off by setting a MOS transistor at the power supply point, thereby reducing the power consumption of the battery management system. In the plug-in state, the pulse wake-up function is realized by a low-power reset chip. The low-power reset chip can effectively improve the delay time of the wake-up pulse signal, ensuring the success rate of timely wake-up of the battery management system and improving charging efficiency.

[0016] To achieve the above objectives, a second aspect of this utility model provides a communication module, which includes the aforementioned wake-up circuit.

[0017] According to the communication module provided by this utility model, the power supply circuit is cut off by setting a MOS transistor at the power supply point, thereby reducing the power consumption of the battery management system. In the plug-in state, the pulse wake-up function is realized by a low-power reset chip. The low-power reset chip can effectively improve the delay time of the wake-up pulse signal, ensuring the success rate of timely wake-up of the battery management system and improving charging efficiency.

[0018] Additional aspects and advantages of this invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. Attached Figure Description

[0019] To more clearly illustrate the technical solutions in this utility model or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only for this utility model. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0020] Figure 1 The circuit diagram of the wake-up circuit provided by this utility model.

[0021] Figure 2 A schematic diagram of the reset unit pulse provided by this utility model.

[0022] Figure 3 This is a schematic diagram of the communication module provided by this utility model.

[0023] Reference numerals: 10-First switching unit; 11-First gate; 12-First source; 13-First drain; 20-Reset unit; 21-Reset input; 22-Reset output; 23-Ground; 30-Second switching unit; 31-Second gate; 32-Second source; 33-Second drain; 40-Power management unit; 41-Wake-up input; 42-Power supply output; 50-Plug-in port; Q1-First MOSFET; Q2-Second MOSFET; R1-First protection resistor; R2-First pull-up resistor; R3-Second protection resistor; R4-Second pull-up resistor; R5-Third protection resistor; R6-Resistance to ground; D1-Diode; 100-Wake-up circuit; 200-Communication module. Detailed Implementation

[0024] To make the objectives, technical solutions, and advantages of this utility model clearer, the present utility model will be further described in detail below with reference to specific embodiments and accompanying drawings.

[0025] It should be noted that, unless otherwise defined, the technical or scientific terms used in this utility model should have the ordinary meaning understood by one of ordinary skill in the art to which this utility model pertains. The terms "first," "second," and similar terms used in this utility model do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as "comprising" or "including" mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. Terms such as "connected" or "linked" are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. Terms such as "upper," "lower," "left," and "right" are used only to indicate relative positional relationships; when the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0026] As described in the background section, in conventional designs of existing battery management systems (BMS), when the charging connection circuit is plugged into the CC2 ground resistor (approximately 970–1030 Ω), the BMS is continuously awakened and waits for subsequent charging operations. This design complies with relevant standards and ensures a smooth charging process. However, in practical applications, a common scenario exists where charging does not begin immediately after the charging gun is plugged in, but may be delayed for a period of time. In this case, the BMS needs to remain awake to wait for charging instructions, but this behavior causes the BMS to continuously consume the power of the vehicle's small battery. If this state persists for too long, in the worst case, it may deplete the small battery's power, leading to the vehicle's inability to start and charge normally, causing inconvenience to the user.

[0027] In developing this utility model, the applicant discovered that existing battery management system (BMS) designs typically employ a resistor voltage divider combined with capacitor isolation to detect whether a charging gun is inserted. However, this approach has several significant drawbacks. First, when the charging gun is not inserted, the voltage divider resistor continuously consumes power from the vehicle's small battery, resulting in a current consumption (approximately 200uA) even with a relatively high resistance value (e.g., 100K). While an RC capacitor is introduced to assist in detection after the charging gun is inserted, the overall circuit still experiences a certain current consumption (approximately 120uA), which remains a considerable power burden for scenarios where charging is not performed for extended periods.

[0028] Secondly, the capacitor pulse time in the capacitor isolation scheme is affected by the capacitance value and the resistance value of the matching resistor, and is usually short (<10ms). However, the capacitance value is affected by temperature and time lifespan, resulting in significant changes (approximately 30% error over its entire lifespan). This short and uncertain pulse time may lead to the inability to effectively wake up the BMS during its sleep process. Specifically, if the charging gun is inserted at a certain stage of the BMS sleep process (e.g., after the ASW sends a sleep signal to the BSW, but before the PMIC detects the ENA / WAK wake-up signal), the BMS may not detect the insertion action due to the short pulse time and its potential disappearance before detection, thus continuing to enter sleep mode. In this case, the vehicle will not be able to be woken up and charged normally, causing great inconvenience to the user.

[0029] Therefore, in order to solve the above problems, a new technical solution is needed to optimize the charging gun detection mechanism of the BMS, reduce unnecessary power consumption, and ensure that the BMS can be accurately woken up in various charging scenarios to ensure the normal start-up and charging of the vehicle.

[0030] The technical solution of this utility model will be further described in detail below through specific embodiments.

[0031] refer to Figure 1 This is a schematic diagram of the wake-up circuit 100 provided in an embodiment of the present utility model.

[0032] A wake-up circuit 100 according to an embodiment of the present invention includes: a first switching unit 10, including a first MOS transistor Q1, the first MOS transistor Q1 including a first gate 11, a first source 12, a first drain 13 and a first pull-up resistor R2, the first gate 11 being connected to a plug-in port 50, the plug-in port 50 being used to connect a ground resistor R6, the first pull-up resistor R2 being disposed between the first source 12 and the first gate 11, and being used to pull up the voltage of the first gate 11; a reset unit 20, including a reset input terminal 21, a reset output terminal 22 and a ground terminal 23; the reset input terminal 21 being connected to the first drain 13; and a second switching unit 10. Unit 30 includes a second MOSFET Q2, which includes a second gate 31, a second source 32, a second drain 33, and a second pull-up resistor R4. The second gate 31 is connected to the reset output terminal 22, and the second pull-up resistor R4 is disposed between the second source 32 and the second gate 31 to pull up the voltage of the second gate 31. Power management unit 40 includes a wake-up input terminal 41 and a power supply output terminal 42. The wake-up input terminal 41 is connected to the second drain 33 to receive a high-level wake-up pulse, and the power supply output terminal 42 is connected to the first source 12 and the second source 32 to provide wake-up standby voltage to the first source 12 and the second source 32.

[0033] Specifically, the first switching unit 10 includes a first MOSFET Q1, which can be a PMOS transistor (P-channel type). The second switching unit 30 includes a second MOSFET Q2, which can also be a PMOS transistor.

[0034] Among them, the MOSFET is a field-effect transistor that can realize the switching control function in the circuit. When a voltage is applied to the MOSFET, an electric field is formed in the oxide layer of the MOSFET. This electric field affects the charge distribution in the semiconductor material below the oxide layer. When the voltage increases, the strength of the electric field also increases, which causes the charge distribution in the semiconductor to change, so that a charge channel is formed on the semiconductor surface. The conductive properties of the channel change with the change of the electric field strength.

[0035] The charge carriers of a PMOS transistor are holes. The drain is the current output terminal of the PMOS transistor, and current flows from the source to the drain when the PMOS transistor is operating. The source is the current input terminal of the PMOS transistor, and it is generally connected to a higher potential (such as a positive power supply) to provide a channel for holes. The switching state of the PMOS transistor is related to the voltage between the source and the gate. The gate is used to control the switching state of the PMOS transistor, that is, to control the formation of the channel. When the gate voltage is less than the source voltage (generally, the difference between the gate voltage and the source voltage, VGS, needs to be greater than a threshold voltage VGS), the current will be lower than the current. thWhen the PMOS transistor is turned on, holes form a channel between the source and drain to allow current to pass through. When the gate voltage is not less than the source voltage, the PMOS transistor is not turned on, and no channel is formed between the source and drain.

[0036] The first gate 11 is connected to the plug-in port 50, which is used to connect the ground resistor R6. When the charging gun is not plugged in, the ground resistor R6 is not connected to the plug-in port 50. The first pull-up resistor R2 is set between the first source 12 and the first gate 11. When the ground resistor R6 is not connected, there is no current loop in the wake-up circuit 100, and the voltage across the first pull-up resistor R2 is the same, that is, the voltage of the first gate 11 is the same as the voltage of the first source 12.

[0037] It should be noted that the resistance value of the ground resistor R6 can be 1kΩ (±30Ω) according to the requirements of the national standard GB / T 18487.1-2023.

[0038] The reset unit 20 includes a reset input terminal 21, a reset output terminal 22, and a ground terminal 23. The reset input terminal 21 is connected to the first drain 13, which is used to supply power to the reset unit 20 when the first switch unit is turned on.

[0039] The reset unit 20 can be a reset chip. When the voltage at the reset input terminal 21 of the reset chip is greater than the reset threshold voltage, the timer inside the reset chip starts counting. At this time, the reset chip will output a reset signal (RESET signal). The reset signal remains in an active state (such as a low level state) during the timer delay period so that the circuit can perform a reset operation. When the time interval ends, the timer stops counting, and the reset signal returns to an inactive state (such as a high level state), thereby completing the reset process.

[0040] The reset output terminal 22 of the reset unit 20 can be an open-drain pin. When the reset output terminal 22 is set to a low level, the internal transistor is turned on, pulling the pin low to ground level (ground). When the reset output terminal 22 is set to a high level, the internal transistor is turned off, and the pin enters a high-impedance state. At this time, the level on the pin is determined by the external circuit.

[0041] The reset output terminal 22 is connected to the second gate 31, and the reset output terminal 22 is used to control the voltage of the second gate 31. The second pull-up resistor R4 is set between the second source 32 and the second gate 31. When the ground resistor R6 is not connected, there is no current loop in the wake-up circuit 100, and the voltage across the second pull-up resistor R4 is the same, that is, the voltage of the second gate 31 is the same as the voltage of the second source 32.

[0042] The power management unit 40 includes a wake-up input terminal 41 and a power supply output terminal 42. The wake-up input terminal 41 is connected to the second drain 33. When the second switching unit 30 is turned on, the wake-up input terminal 41 can receive a high-level wake-up pulse input from the second drain 33, thereby waking up the BMS and enabling the power management unit 40 to start working. The power supply output terminal 42 of the power management unit 40 can be connected to the first source 12 and the second source 32 to provide wake-up standby voltage to the first source 12 and the second source 32. The wake-up standby voltage can be a 5V_Standby voltage, which is a 5V voltage continuously output by the power management unit 40. When the BMS system is in sleep mode, this voltage continues to output to the first source 12 and the second source 32. By using the power supply output port 42 of the power management unit 40 to supply power to the first source 12 and the second source 32, the number of external power supply interfaces is effectively reduced, and the integration of the circuit is improved.

[0043] When the plug-in port 50 is not connected to the ground resistor R6, the first pull-up resistor R2 is used to pull up the voltage of the first gate 11 to the same level as the voltage of the first source 12, so as to turn off the first switching unit 10.

[0044] As an optional embodiment, when the plug-in port 50 is not connected to the ground resistor R6, the voltage of the first gate 11 is pulled up by the first pull-up resistor R2 to be the same as the voltage of the first source 12, and the first switching unit 10 is turned off.

[0045] Specifically, when the plug-in port 50 is not connected to the ground resistor R6, the voltage of the first gate 11 is pulled up by the first pull-up resistor R2 to be the same as the voltage (5V) of the first source 32. The voltage difference between the first gate 11 and the first source 12 is less than the conduction threshold voltage of the first MOS transistor Q1. At this time, the first MOS transistor Q1 is turned off, that is, the first switching unit 10 is turned off.

[0046] When the first switching unit 10 is turned off, the second pull-up resistor R4 is used to pull up the voltage of the second gate 31 to the same level as the voltage of the second source 32, so that the second switching unit 30 is turned off.

[0047] As an optional embodiment, when the first switching unit 10 is turned off, the voltage of the second gate 31 is pulled up by the second pull-up resistor R4 to be the same as the voltage of the second source 32, and the second switching unit 30 is turned off.

[0048] Specifically, when the first switching unit 10 is turned off, the wake-up circuit 100 is not turned on, and no current flows through the reset unit 20. Since the second pull-up resistor R4 connects the second gate 31 and the second source 32, the voltage of the second gate 31 is the same as the voltage of the second source 32 (5V). The voltage difference between the second gate 31 and the second source 32 is less than the turn-on threshold voltage of the second MOS transistor Q2. At this time, the second MOS transistor is turned off, that is, the second switching unit 30 is turned off.

[0049] By setting a first MOSFET Q1 and a second MOSFET Q2 in the power supply circuit of the wake-up circuit 100, the current consumed in the circuit of the wake-up circuit 100 when the charging gun is not plugged in is close to zero, so that the power consumption of the wake-up circuit 100 is low when the charging gun is not plugged in, thereby reducing the risk that the vehicle cannot start or charge due to the exhaustion of the power supply of the wake-up circuit 100.

[0050] When the plug-in port 50 is connected to the ground resistor R6, the ground resistor R6 is used to control the voltage of the first gate 11 to be less than the voltage of the first source 12, so that the first switching unit 10 is turned on; the first switching unit 10 is used to supply power to the reset unit 20.

[0051] As an optional embodiment, when the plug-in port 50 is connected to the ground resistor R6, the voltage of the first gate 11 is less than the voltage of the first source 12, the first switching unit 10 is turned on, and power is supplied to the reset unit 20.

[0052] Specifically, when the plug-in port 50 is connected to the ground resistor R6 (in the plug-in state), the ground resistor R6 acts as a voltage divider in the circuit, causing the voltage of the first gate 11 to decrease. At this time, the voltage of the first source 12 is greater than the voltage of the first gate 11. The voltage difference between the first gate 11 and the first source 12 is greater than the conduction threshold voltage of the first MOS transistor Q1, so that the first MOS transistor Q1 is turned on, allowing current to flow to the reset unit 20 to supply power to the reset unit 20.

[0053] refer to Figure 2 This is a schematic diagram of the reset unit pulse provided in an embodiment of the present invention.

[0054] When the reset unit 20 is powered, the reset unit 20 is used to control the reset output terminal 22 to output zero voltage so that the voltage of the second gate 31 is less than the voltage of the second source 32; the reset unit 20 is also used to control the second switching unit 30 to be turned on; the second switching unit 30 is used to control the second drain 33 to output a high-level wake-up pulse.

[0055] As an optional embodiment, when the reset unit 20 is powered, the reset output terminal 22 outputs zero voltage, the voltage of the second gate 31 is less than the voltage of the second source 32, the second switching unit 30 is turned on, and the second drain 33 outputs a high-level wake-up pulse.

[0056] When the time for the reset output terminal 22 to output zero voltage reaches a preset time interval, the reset output terminal 22 is used to control the reset output terminal 22 to stop grounding; the reset output terminal 22 is used to control the second switching unit 30 to turn off; the second switching unit 30 is used to control the second drain 33 to stop outputting a high-level wake-up pulse.

[0057] As an optional embodiment, when the time for the reset output terminal 22 to output zero voltage reaches a preset time interval, the reset output terminal 22 stops grounding, the second switching unit 30 is turned off, and the second drain 33 stops outputting high-voltage wake-up pulses.

[0058] Specifically, when the reset unit 20 is powered, the voltage of the reset input terminal 21 gradually rises. The reset output terminal 22 is grounded through an internal transistor so that the reset output terminal 22 outputs zero voltage to the outside within a preset time interval. Further, at this time, the voltage of the second gate 31 is less than the voltage of the second source 32. The voltage difference between the second gate 31 and the second source 32 is greater than the conduction threshold voltage of the second MOSFET Q2. The second MOSFET Q2 is turned on, and the second drain 33 can output a high-level wake-up pulse to the power management unit 40. When the time for the reset output terminal 22 to output zero voltage reaches the preset time interval, the reset output terminal 22 stops being grounded. At this time, the voltage of the second gate 31 is pulled up again to match the voltage of the second source 32. The second MOSFET Q2 is turned off, and the second drain 33 stops outputting a high-level wake-up pulse.

[0059] It should be noted that the reset chip used in this invention can be a TPS3809-Q1 chip. The TPS3809-Q1 chip has a power supply current of 9μA, resulting in low power consumption and effectively reducing the power consumption of the wake-up circuit 100. When the voltage at the reset input terminal 21 of the reset chip rises to the first threshold voltage, the reset output terminal 22 begins to output zero voltage. When the voltage at the reset input terminal 21 rises to the second threshold voltage, the timer in the reset unit 20 starts, maintaining the zero voltage output at the reset output terminal 22 for a preset time interval. After the preset time interval is reached, the reset output terminal 22 outputs a high level. During this process, when the voltage at the reset input terminal 21 reaches the first threshold voltage, the reset output terminal 22 can begin to output zero voltage, thereby reducing the delay in outputting zero voltage when the timer starts, or ensuring that the reset unit 20 can still output the correct signal when the power supply voltage is unstable.

[0060] It should be noted that the preset time interval is related to the reset chip used in the reset unit 20, and the time interval can be in the hundreds of milliseconds range. For example, the preset time interval Td of the TPS3809-Q1 chip is 200ms. When using other models of reset chips as the reset unit 20, the preset time interval can be set. If a reset chip that cannot have its preset time interval set is used, the appropriate reset chip can be replaced according to the required preset time interval.

[0061] When the wake-up input terminal 41 receives a high-level wake-up pulse, the wake-up input terminal 41 is used to wake up the power management unit 40.

[0062] As an optional embodiment, when the wake-up input terminal 41 receives a high-level wake-up pulse, the power management unit 40 is woken up.

[0063] Specifically, when the wake-up input terminal 41 receives a high-level wake-up pulse, it wakes up the power management unit 40, thereby enabling the power management unit 40 to wake up the BMS system for power supply.

[0064] As an optional embodiment, when the ground resistor R6 is plugged in (in the plug-in state), since the ground resistor R6 acts as a voltage divider in the circuit, the voltage of the first gate 11 is reduced. The voltage of the first gate 11 is less than the voltage of the first source 12. At this time, the first switching unit 10 is turned on. Further, the current flows through the first drain 13 to the reset input terminal 21 of the reset unit 20, and the voltage of the reset input terminal 21 increases, so that the reset output terminal 22 outputs zero voltage to the second gate 31. The voltage of the second gate 31 decreases. At this time, the voltage of the second gate 31 is less than the voltage of the second source 32, and the second switching unit 30 is turned on. Further, so that the second drain 33 can input a high-level wake-up pulse to the wake-up input terminal 41 of the power management unit 40, further waking up the BMS system. When the time for outputting the high-level wake-up pulse reaches the preset time interval, the reset output terminal 22 stops outputting the high-level wake-up pulse.

[0065] By setting a reset unit 20 in the wake-up circuit 100, the pulse wake-up function of the BMS system can be realized when the ground resistor R6 is connected (in the plug-in state). The reset unit 20 can effectively improve the delay time of the wake-up pulse signal, ensuring the success rate of timely wake-up of the battery management system and improving charging efficiency.

[0066] As an optional embodiment, a first protection resistor R1 is provided between the first switching unit 10 and the plug-in port 50.

[0067] As an optional embodiment, a second protection resistor R3 is provided between the second switching unit 30 and the reset unit 20.

[0068] As an optional embodiment, the second drain 33 and the ground terminal 23 may also be provided with a third protection resistor.

[0069] Specifically, by setting a protective resistor in the wake-up circuit 100, the current of the circuit can be limited, preventing excessive current from damaging the components in the wake-up circuit 100, effectively protecting the circuit components of the wake-up circuit 100, and improving the stability and reliability of the wake-up circuit 100.

[0070] As an optional embodiment, a diode D1 is also provided between the first gate 11 and the plug-in port. The diode D1 has high impedance characteristics when reverse biased. When a reverse voltage occurs at the plug-in port, the diode will be in a reverse cut-off state, preventing current from flowing through, thereby protecting other components in the circuit from damage.

[0071] As can be seen from the above, the wake-up circuit provided by this utility model reduces the power consumption of the battery management system by cutting off the power supply circuit through a MOS transistor at the power supply point when the charging gun is not inserted; when the charging gun is inserted, the pulse wake-up function is realized through a low-power reset chip. The low-power reset chip can effectively improve the delay time of the wake-up pulse signal, ensuring the success rate of timely wake-up of the battery management system and improving charging efficiency.

[0072] It should be noted that the above description describes some embodiments of the present invention. Other embodiments are within the scope of the appended claims. In some cases, the actions or steps described in the claims can be performed in a different order than that shown in the above embodiments and still achieve the desired result. Furthermore, the processes depicted in the drawings do not necessarily require a specific or sequential order to achieve the desired result. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.

[0073] Based on the same inventive concept, corresponding to the method provided in any of the above embodiments, this utility model also provides a communication module 200, which includes the wake-up circuit 100 of any of the above embodiments and has the same beneficial effects as the wake-up circuit 100, which will not be described again here.

[0074] Furthermore, although the operation method of this utility model is described in a specific order in the accompanying drawings, this does not require or imply that the operations must be performed in that specific order, or that all the operations shown must be performed to achieve the desired result. On the contrary, the steps depicted in the flowchart can be executed in a different order. Additionally or alternatively, certain steps may be omitted, multiple steps may be combined into one step, and / or one step may be broken down into multiple steps.

[0075] It should be noted that, unless otherwise defined, the technical or scientific terms used in the embodiments of this utility model should have the ordinary meaning understood by one of ordinary skill in the art to which this utility model pertains. The terms "first," "second," and similar words used in the embodiments of this utility model do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as "comprising" or "including" mean that the element or object preceding the word covers the element or object listed after the word and its equivalents, without excluding other elements or objects. Terms such as "connected" or "linked" are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. Terms such as "upper," "lower," "left," and "right" are only used to indicate relative positional relationships; when the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0076] While the spirit and principles of this invention have been described with reference to several specific embodiments, it should be understood that this invention is not limited to the disclosed specific embodiments, and the division of aspects does not imply that features in these aspects cannot be combined for benefit; such division is merely for ease of description. This invention is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims. The scope of the appended claims is to be interpreted in the broadest sense, thereby encompassing all such modifications and equivalent structures and functions.

Claims

1. A wake-up circuit, characterized in that, include: The first switching unit (10) includes a first MOS transistor (Q1), which includes a first gate (11), a first source (12), a first drain (13), and a first pull-up resistor (R2). The first gate (11) is connected to a plug-in port (50), which is used to connect a ground resistor (R6). The first pull-up resistor (R2) is disposed between the first source (12) and the first gate (11) and is used to pull up the voltage of the first gate (11). The reset unit (20) includes a reset input terminal (21), a reset output terminal (22), and a ground terminal (23); the reset input terminal (21) is connected to the first drain (13); The second switching unit (30) includes a second MOS transistor (Q2), which includes a second gate (31), a second source (32), a second drain (33), and a second pull-up resistor (R4). The second gate (31) is connected to the reset output terminal (22), and the second pull-up resistor (R4) is disposed between the second source (32) and the second gate (31) to pull up the voltage of the second gate (31). The power management unit (40) includes a wake-up input terminal (41) and a power supply output terminal (42). The wake-up input terminal (41) is connected to the second drain (33) and is used to receive a high-level wake-up pulse. The power supply output terminal (42) is connected to the first source (12) and the second source (32) and is used to provide wake-up standby voltage to the first source (12) and the second source (32).

2. The wake-up circuit according to claim 1, characterized in that, When the plug-in port (50) is not connected to the ground resistor (R6), the first pull-up resistor (R2) is used to pull up the voltage of the first gate (11) to the same voltage as the first source (12) so that the first switching unit (10) is turned off.

3. The wake-up circuit according to claim 2, characterized in that, When the first switching unit (10) is turned off, the second pull-up resistor (R4) is used to pull up the voltage of the second gate (31) to the same voltage as the second source (32) so that the second switching unit (30) is turned off.

4. The wake-up circuit according to claim 1, characterized in that, When the plug-in port (50) is connected to a ground resistor (R6), the ground resistor (R6) is used to control the voltage of the first gate (11) to be less than the voltage of the first source (12) so that the first switching unit (10) is turned on. The first switching unit (10) is used to supply power to the reset unit (20).

5. The wake-up circuit according to claim 4, characterized in that, When the reset unit (20) is powered, the reset unit (20) is used to control the reset output terminal (22) to output zero voltage so that the voltage of the second gate (31) is less than the voltage of the second source (32); The reset unit (20) is also used to control the second switch unit (30) to be turned on; The second switching unit (30) is used to control the second drain (33) to output a high-level wake-up pulse.

6. The wake-up circuit according to claim 5, characterized in that, When the time for which the reset output terminal (22) outputs zero voltage reaches a preset time interval, the reset output terminal (22) is used to control the reset output terminal (22) to stop grounding; The reset output terminal (22) is used to control the second switching unit (30) to be turned off; The second switching unit (30) is used to control the second drain (33) to stop outputting a high-level wake-up pulse.

7. The wake-up circuit according to claim 1, characterized in that, When the wake-up input terminal (41) receives a high-level wake-up pulse, the wake-up input terminal (41) is used to wake up the power management unit (40).

8. The wake-up circuit according to claim 1, characterized in that, A first protection resistor (R1) is provided between the first switch unit (10) and the plug-in port (50).

9. The wake-up circuit according to claim 1, characterized in that, A second protection resistor (R3) is provided between the second switching unit (30) and the reset unit (20).

10. A communication module, characterized in that, The communication module includes a wake-up circuit as described in any one of claims 1 to 9.

Images