A packaging structure
By stacking chips along a first direction and using silicon bridges and interposers for electrical connection, the problems of miniaturization and high cost of optoelectronic packaging products are solved, achieving miniaturization of the packaging structure and integrity of signal transmission.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- AMQ INTELLIGENT TECH LTD
- Filing Date
- 2025-05-16
- Publication Date
- 2026-06-02
AI Technical Summary
Existing optoelectronic packaging products are large in size in the horizontal direction, making miniaturization difficult, and are also costly, have low yield rates, and incomplete signal transmission.
The chips are stacked along a first direction and electrically connected through silicon bridges and interposers, which reduces the area occupied on the substrate. The combination of silicon bridges and organic materials is used for signal transmission, which reduces costs and improves signal integrity.
This achieved miniaturization of the packaging structure, reduced production costs, and improved the integrity and stability of signal transmission.
Smart Images
Figure CN224319879U_ABST
Abstract
Description
Technical Field
[0001] This utility model relates to the field of semiconductor technology, and in particular to a packaging structure. Background Technology
[0002] With the development of emerging technologies such as artificial intelligence, big data, and cloud computing, higher requirements are being placed on optoelectronic packaging products. In related technologies, chips within optoelectronic packaging products are typically arranged horizontally on a substrate and interconnected via the substrate. This results in a relatively large horizontal size for the packaging products, hindering their miniaturization. Furthermore, the large interconnection distances also compromise signal transmission integrity. Alternatively, while multiple chips may be stacked vertically, a large silicon interposer is required as an interconnecting interposer to connect them to the substrate, leading to higher costs and lower yield rates for optoelectronic packaging products. Utility Model Content
[0003] This invention provides a packaging structure, the purpose of which is to reduce the area and cost of the packaging structure.
[0004] To achieve the above objectives, this utility model provides a packaging structure, comprising:
[0005] substrate;
[0006] A chip assembly includes a first chip and a second chip stacked along a first direction, the first direction being arranged intersecting the plane of the substrate.
[0007] An interposer component includes a silicon bridge and an interposer layer electrically connected to each other, the interposer layer being electrically connected to the substrate, the silicon bridge being disposed between the first chip and the second chip along the first direction, the first chip and the second chip being electrically connected through the silicon bridge.
[0008] In one embodiment, the first chip is electrically connected to the silicon bridge via a first micro-bonding post, and the first chip is electrically connected to the interposer via a second micro-bonding post, wherein the interposer is configured as an organic material.
[0009] In one embodiment, the interposer further includes an energy absorber, through which the interposer and the silicon bridge are connected, such that the energy absorber can absorb thermal deformation of the interposer relative to the silicon bridge.
[0010] In one embodiment, the interlayer has a groove, and the energy-absorbing element is disposed within the groove.
[0011] In one embodiment, the second chip is disposed between the first chip and the substrate along the first direction, and the packaging structure further includes a heat sink disposed between the second chip and the substrate along the first direction.
[0012] In one embodiment, the heat sink is configured as a thermal interface material.
[0013] In one embodiment, the chip assembly further includes a third chip connected to the substrate to enable the third chip to communicate with the second chip.
[0014] The above-mentioned solution of this utility model has the following beneficial effects:
[0015] In this embodiment, the first chip and the second chip are stacked along a first direction. Compared to an arrangement where the first chip and the second chip are laid flat on the substrate, this arrangement reduces the area occupied by the chip components on the substrate, thus reducing the projected area of the chip components on the substrate along the first direction. This reduces the area of the substrate and consequently the area of the packaging structure, facilitating miniaturization. Furthermore, the shorter electrical connection distance between the first and second chips improves the integrity of signal transmission between them. Moreover, compared to an arrangement where multiple chips are stacked along the first direction but require a large silicon interconnect layer as an intermediary layer connected to the substrate, with multiple chips stacked on the same side of the intermediary layer, this arrangement places a silicon bridge between the first and second chips along the first direction, electrically connecting them. This reduces the area of the silicon bridge, thereby reducing the material usage of the intermediary components and ultimately lowering the production cost of the packaging structure.
[0016] Other beneficial effects of this invention will be described in detail in the following detailed description section. Attached Figure Description
[0017] Figure 1 This is a schematic diagram of the packaging structure in one embodiment of the present invention;
[0018] Figure 2 This is a top view of the assembly of the chip component and the substrate in one embodiment of the present invention.
[0019] [Explanation of Labels in the Attached Image]
[0020] 1. Substrate; 2. Chip assembly; 21. First chip; 212. First micro-bonding post; 213. Second micro-bonding post; 22. Second chip; 23. Third chip; 3. Intermediate component; 31. Silicon bridge; 32. Intermediate layer; 321. Groove; 33. Energy absorber; 4. Heat sink; 5. Optical fiber. Detailed Implementation
[0021] To make the technical problems, solutions, and advantages of this utility model clearer, a detailed description will be provided below with reference to the accompanying drawings and specific embodiments. Obviously, the described embodiments are only some, not all, of the embodiments of this utility model. All other embodiments obtained by those skilled in the art based on the embodiments of this utility model without creative effort are within the scope of protection of this utility model. Furthermore, the technical features involved in the different embodiments of this utility model described below can be combined with each other as long as they do not conflict with each other.
[0022] In the description of this utility model, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicating the orientation or positional relationship, are based on the orientation or positional relationship shown in the accompanying drawings and are only for the convenience of describing this utility model and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this utility model. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.
[0023] In the description of this utility model, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "joining" should be interpreted broadly. For example, they can refer to a locking connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this utility model based on the specific circumstances.
[0024] This application provides a packaging structure; please refer to [link / reference]. Figure 1 and Figure 2The packaging structure includes a substrate 1, a chip assembly 2, and an interposer 3. The substrate 1 provides electrical connection, protection, support, heat dissipation, and assembly functions for the chip assembly 2, enabling multi-pin configuration, reduced package size, improved electrical performance and heat dissipation, ultra-high density, or multi-chip modularization. The chip assembly 2 includes a first chip 21 and a second chip 22 stacked along a first direction. This arrangement reduces the area of the package structure projected onto the substrate 1 along the first direction. The first chip 21 can be a PIC (Photonic Integrated Circuit), which integrates various optical or optoelectronic devices, such as lasers, electro-optic modulators, photodetectors, optical attenuators, optical multiplexers / demultiplexers, and optical amplifiers. The PIC converts optical signals into electrical signals. The second chip 22 can be an EIC (Electronic Integrated Circuit), which amplifies electrical signals. For example, please refer to [link to relevant documentation]. Figure 1 The first chip 21, which is a PIC, can be connected to the optical fiber 5. The PIC can convert the optical signal in the optical fiber 5 into an electrical signal and transmit the converted electrical signal to the second chip 22, which is an EIC, so that the converted electrical signal can be amplified in the EIC to achieve related functions. The first direction intersects with the plane where the substrate 1 is located. For example, please refer to... Figure 1 , Figure 1 The direction indicated by R1 is the first direction, which can be arranged perpendicular to the plane of substrate 1. The interposer component 3 includes a silicon bridge 31 and an interposer layer 32 that are electrically connected to each other. For example, the silicon bridge 31 and the interposer layer 32 can be connected via microbumps. The interposer layer 32 is electrically connected to substrate 1. For example, the interposer layer 32 and the substrate can be connected via microbumps. The silicon bridge 31 is disposed between the first chip 21 and the second chip 22 along the first direction, so that the first chip 21 and the second chip 22 can be electrically connected via the silicon bridge 31. For example, the first chip 21 and the second chip 22 can be electrically connected to the silicon bridge 31 via microbumps. The silicon bridge 31 has a better signal transmission speed, so that the signal transmission speed between the first chip 21 and the second chip 22 is faster.
[0025] In this embodiment, the first chip 21 and the second chip 22 are stacked along a first direction. Compared to the arrangement where the first chip 21 and the second chip 22 are laid flat on the substrate 1, this arrangement reduces the area occupied by the chip assembly 2 on the substrate 1, which helps to reduce the projected area of the chip assembly 2 on the substrate 1 along the first direction, thus reducing the area of the substrate 1 and consequently the area of the packaging structure, facilitating the miniaturization of the packaging structure. Furthermore, the shorter electrical connection distance between the first chip 21 and the second chip 22 improves the integrity of signal transmission between them. Moreover, compared to the arrangement where multiple chips are stacked along the first direction, but require a large silicon interposer as an intermediate interconnect layer connected to the substrate 1, and multiple chips are stacked on the same side of the intermediate interconnect layer, this application places the silicon bridge 31 along the first direction between the first chip 21 and the second chip 22, and the first chip 21 and the second chip 22 are electrically connected through the silicon bridge 31. This reduces the area of the silicon bridge 31, thereby reducing the material usage of the intermediate assembly 3 and thus lowering the production cost of the packaging structure.
[0026] In one embodiment, please refer to Figure 1 The first chip 21 is electrically connected to the silicon bridge 31 via the first micro-bond post 212, and to the interposer 32 via the second micro-bond post 213. The interposer 32 is configured with an organic material. It should be noted that in the packaging structure, some signals require high transmission speeds, while others do not. The silicon bridge 31 has strong signal transmission capabilities and high speeds, but its cost is high. The interposer 32, configured with an organic material, has slower signal transmission speeds but lower costs. The arrangement density of the first micro-bond post 212 can be greater than that of the second micro-bond post 213. That is, there are more signal transmission channels between the first chip 21 and the silicon bridge 31. For example, the first chip 21 can transmit multiple signals. The first chip 21, the first micro-bond pillar 212, and the silicon bridge 31 form a faster signal transmission channel to transmit signals to the second chip 22 more quickly. The first chip 21, the second micro-bond pillar 213, and the interposer layer 32 configured as an organic material form a slower signal transmission channel for signals with low transmission speed requirements. This allows the packaging structure of this application to reduce the waste of the performance of each component and to make full use of the capabilities of each component, thereby helping to further reduce the production cost of the packaging structure.
[0027] In one embodiment, please refer to Figure 1The interposer 3 also includes an energy absorber 33. The interposer 32 and the silicon bridge 31 are connected through the energy absorber 33, so that the energy absorber 33 can absorb the thermal deformation of the interposer 32 relative to the silicon bridge 31, thereby improving the stability of the electrical connection between the interposer 32 and the silicon bridge 31. It should be noted that silicon and organic materials have significantly different coefficients of thermal expansion. During the operation of the encapsulation structure, the temperature will rise, making it more likely that the interposer 32 will undergo thermal deformation relative to the silicon bridge 31. The energy absorber 33 can be a shape memory metal or a material that can absorb thermal stress to absorb the thermal deformation of the interposer 32 relative to the silicon bridge 31, which is beneficial to improving the stability of the electrical connection between the interposer 32 and the silicon bridge 31.
[0028] In one embodiment, please refer to Figure 1 The intermediate layer 32 has a groove 321, and the energy-absorbing element 33 is disposed in the groove 321, so that the energy-absorbing element 33 is more firmly connected to the intermediate layer 32.
[0029] In one embodiment, please refer to Figure 1 The second chip 22 is disposed between the first chip 21 and the substrate 1 along the first direction. The package structure also includes a heat sink 4, which is disposed between the second chip 22 and the substrate 1 along the first direction to improve the heat dissipation performance of the second chip 22. It should be noted that the second chip 22 can transmit signals through the intermediary component 3, so that the second chip 22 does not need to be electrically connected to the substrate 1. The space saved can be used to set up the heat sink 4, expanding the heat dissipation channel inside the package structure. This allows the heat generated by the second chip 22 during normal operation to be quickly transferred to the substrate 1 through the heat sink 4, and then dissipated to the PCB (Printed Circuit Board) and the external environment, thereby improving the heat dissipation performance of the second chip 22.
[0030] In one embodiment, the heat sink 4 is configured as a thermal interface material to reduce the contact thermal resistance between the second chip 22 and the substrate 1. By filling micro-gaps and replacing the air layer, an efficient heat conduction path is established, thereby improving heat dissipation efficiency.
[0031] In one embodiment, please refer to Figure 1 and Figure 2 The chip assembly 2 also includes a third chip 23, which is connected to the substrate 1 to enable communication between the third chip 23 and the second chip 22. For example, the third chip 23 can be an ASIC (Application Specific Integrated Circuit), which is an integrated circuit designed for a specific purpose. The forwarding performance between ASICs can typically reach 1Gbps or even higher, thus providing an excellent material basis for the switching matrix. The ASIC is electrically connected to the substrate 1 through bumps, thereby communicating with the EIC to realize its design functions.
[0032] The above description is the preferred embodiment of this utility model. It should be noted that for those skilled in the art, several improvements and modifications can be made without departing from the principle of this utility model, and these improvements and modifications should also be considered within the protection scope of this utility model.
Claims
1. A packaging structure, characterized in that, include: substrate; A chip assembly includes a first chip and a second chip stacked along a first direction, the first direction being arranged intersecting the plane of the substrate. An interposer component includes a silicon bridge and an interposer layer electrically connected to each other, the interposer layer being electrically connected to the substrate, the silicon bridge being disposed between the first chip and the second chip along the first direction, the first chip and the second chip being electrically connected through the silicon bridge.
2. The packaging structure according to claim 1, characterized in that, The first chip is electrically connected to the silicon bridge via a first micro-bonding post, and the first chip is electrically connected to the interposer via a second micro-bonding post, the interposer being configured as an organic material.
3. The packaging structure according to claim 2, characterized in that, The interposer also includes an energy absorber, through which the interposer and the silicon bridge are connected, such that the energy absorber can absorb thermal deformation of the interposer relative to the silicon bridge.
4. The packaging structure according to claim 3, characterized in that, The intermediate layer has a groove, and the energy-absorbing element is disposed within the groove.
5. The packaging structure according to claim 1, characterized in that, The second chip is disposed between the first chip and the substrate along the first direction, and the packaging structure further includes a heat sink disposed between the second chip and the substrate along the first direction.
6. The packaging structure according to claim 5, characterized in that, The heat sink is configured as a thermal interface material.
7. The packaging structure according to any one of claims 1 to 6, characterized in that, The chip assembly also includes a third chip connected to the substrate to enable the third chip to communicate with the second chip.