Chip power supply mode intelligent detection circuit

Abstract

The utility model discloses a kind of intelligent detection circuit of chip power supply mode, the circuit includes: LDO overall module, timing module and power supply mode judging module;LDO overall module, output target voltage and power signal VCC;Timing module, output timing signal;Power supply mode judging module, the order of rising of detection timing signal and target signal determines power supply mode, when the rising of timing signal first arrives, determine the power supply mode of chip as external VOUT power supply mode, LDO power stage unit is disabled;When the rising of target signal first arrives, determine the power supply mode of chip as self-power supply mode and output ModeDone signal, LDO overall module continues to work, according to ModeDone signal adjustment target voltage is the target voltage of circuit normal operation.This scheme can realize the intelligent detection and judgment of chip power supply mode, with the characteristics of reducing power consumption, improve system efficiency.

Description

Technical Field

[0001] This utility model relates to the field of power supply and charging technology, and in particular to an intelligent detection circuit for chip power supply mode. Background Technology

[0002] With the continuous improvement of the performance of various electronic devices, the demand for charging power in electronic products is becoming increasingly higher. Among these, flyback power supply topologies, as a common AC-DC charging solution, are increasingly being used with synchronous rectification chips to improve charging efficiency. In synchronous rectification chip applications, there are two main power supply modes: one is self-powered, using a built-in LDO (Low Drop-Out Regulator) to supply power to VCC via the VD pin. VCC typically has an external 0.1uF or 1uF capacitor to ensure a stable power supply voltage. The other power supply mode is where the system directly connects the VOUT voltage to the chip's VCC pin, using an external VOUT to power the synchronous rectification chip without requiring an internal LDO. In self-powered mode, customers can flexibly decide between the two connection methods of the synchronous rectification chip, such as high-side connection (input side) or low-side connection (output side), as described in the reference. Figure 1 and Figure 2 To better address the system's EMI (Electromagnetic Interference) problem, this approach is employed. However, because the chip uses an LDO power supply, the VD supply voltage is high, and the LDO's efficiency is low, resulting in high chip power consumption and low efficiency. In a VOUT power supply topology, synchronous rectification can only be placed on the low side to ensure a stable DC voltage VOUT to power the chip, as described above. Figure 3 .

[0003] In practical applications, all three connection methods mentioned above are widely used due to differences in EMI, efficiency, and cost considerations. For ease of production and management, a single synchronous rectifier chip needs to be compatible with all three connection methods. Ideally, the chip should automatically determine whether it should be self-powered or powered by an external power supply (VOUT) to achieve optimal chip operation. However, most products on the market cannot automatically determine the power supply mode, and the LDO operates continuously in all three scenarios. When customers use external power, the continuous operation of the internal LDO leads to additional losses and sacrifices efficiency. Another approach is to set the target stable voltage of the LDO at a lower level. When customers use external power, the LDO stops operating because the external power supply voltage is higher than the LDO's target voltage, achieving high efficiency in this connection method. However, this introduces the problem that when customers use a self-powered connection, the lower target voltage of the LDO prevents the MOSFET from conducting sufficiently, resulting in higher MOSFET conduction losses. Therefore, the system efficiency is lower in the self-powered connection method.

[0004] In view of this, it is necessary to propose improvements to the circuit structure of the current power supply mode of chips. Utility Model Content

[0005] To solve at least one of the above-mentioned technical problems, the main objective of this utility model is to provide an intelligent detection circuit with a chip power supply mode.

[0006] To achieve the above objectives, the present invention provides a technical solution as follows: an intelligent detection circuit for chip power supply mode, comprising: an LDO overall module, a timing module, and a power supply mode determination module, wherein the LDO overall module is electrically connected to the timing module, the timing module is electrically connected to the power supply mode determination module, and the power supply mode determination module is electrically connected to the LDO module.

[0007] The LDO module includes an LDO power stage unit, a comparator, and a voltage adjustment unit. The LDO power stage unit is electrically connected to the voltage adjustment unit. The negative input terminal of the comparator is electrically connected to the voltage adjustment unit. The positive input terminal of the comparator is connected to a resistor-divided voltage. The output terminal of the comparator outputs the target voltage. The LDO power stage unit is used to output a power signal VCC based on the VD signal.

[0008] The timing module is used to acquire the power signal VCC, start timing when the power signal VCC reaches the preset reference voltage, set the target time, and output a timing signal according to the relationship between the timing and the target time.

[0009] The power supply mode determination module is used to synchronously acquire timing signals and target signals, and detect the order of the rising edges of the timing signals and target signals to determine the power supply mode.

[0010] Specifically, when the rising edge of the timing signal arrives first, the chip's power supply mode is determined to be external VOUT power supply mode, and the LDO power stage unit is disabled; when the rising edge of the target signal arrives first, the chip's power supply mode is determined to be self-powered mode and a ModeDone signal is output, the LDO module continues to work, and the target voltage is adjusted to the target voltage for normal circuit operation according to the ModeDone signal.

[0011] The voltage adjustment unit includes a switch group and a voltage divider resistor. The switch group includes a first switch and a second switch connected in parallel for selection according to the ModeDone signal. The voltage divider resistor includes a first resistor, a second resistor, and a third resistor connected in series. The first switch is connected to the common node where the first resistor and the second resistor are connected, and the second switch is connected to the common node where the second resistor and the third resistor are connected.

[0012] Specifically, when the first switch is turned on, the voltage at the negative input terminal of the comparator is at a high potential, and when the second switch is turned on, the voltage at the negative input terminal of the comparator is at a low potential.

[0013] Specifically, when the ModeDone signal is high, the first switch is activated to adjust the target voltage to the target voltage for normal circuit operation; when the ModeDone signal is low, the second switch is activated to set the target output voltage to a higher value.

[0014] The resistor voltage divider has two components: a first resistor voltage divider and a second resistor voltage divider. The first resistor voltage divider is located between the first resistor and the second resistor, and the second resistor voltage divider is located between the second resistor and the third resistor. When the ModeDone signal is high, the first resistor voltage divider is activated by a first switch; when the ModeDone signal is low, the second resistor voltage divider is activated by a second switch. The first resistor voltage divider is higher than the second resistor voltage divider.

[0015] The timing module counts the number of pulses in the VD signal.

[0016] When the number of pulses in the VD signal is less than the number of pulses in the target time, the output timing signal is low; when the number of pulses in the VD signal is equal to the number of pulses in the target time, the output timing signal is high.

[0017] The timing module counts the duration of the effective high level of the VD signal.

[0018] When the effective high-level time of the VD signal is less than the target time, the output timing signal is low; when the effective high-level time of the VD signal is equal to the target time, the output timing signal is high.

[0019] The technical solution of this utility model mainly adopts an LDO overall module, a timing module, and a power supply mode determination module. The LDO overall module outputs the target voltage and the power supply signal VCC; the timing module outputs a timing signal; and the power supply mode determination module detects the rising edge order of the timing signal and the target signal to determine the power supply mode. Specifically, if the rising edge of the timing signal arrives first, the chip's power supply mode is determined to be external VOUT power supply mode, in which case the LDO power stage unit is disabled, reducing power consumption and improving system efficiency. If the rising edge of the target signal arrives first, the chip's power supply mode is determined to be self-powered mode, and a ModeDone signal is output. The LDO overall module continues to operate, adjusting the target voltage according to the ModeDone signal to the normal operating voltage of the circuit, avoiding efficiency loss due to an excessively low target voltage. In summary, this solution can achieve intelligent detection and determination of the chip's power supply mode, with the advantages of reducing power consumption and improving system efficiency. Attached Figure Description

[0020] To more clearly illustrate the technical solutions in the embodiments of this utility model or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this utility model. For those skilled in the art, other drawings can be obtained based on the structures shown in these drawings without creative effort.

[0021] Figure 1 This is a schematic diagram of a circuit in the prior art where synchronous rectification is located on the high side and the chip is self-powered;

[0022] Figure 2 This is a schematic diagram of a circuit in the prior art where synchronous rectification is located on the low side and the chip is self-powered;

[0023] Figure 3 A schematic diagram of a circuit in the prior art where synchronous rectification is located on the low side and powered by an external VOUT.

[0024] Figure 4 This is a circuit diagram of an intelligent detection circuit with chip power supply mode according to an embodiment of the present invention;

[0025] Figure 5 A waveform diagram of the intelligent detection circuit in the self-powered mode of the chip power supply mode according to an embodiment of the present invention;

[0026] Figure 6This is a waveform diagram of the intelligent detection circuit in the chip power supply mode of an embodiment of the present invention under the external VOUT power supply mode;

[0027] Figure 7 This is a flowchart of a detection method for an intelligent detection circuit with a chip power supply mode according to an embodiment of the present invention.

[0028] Label Explanation:

[0029] 100. LDO Overall Module:

[0030] 110. LDO power stage unit; 120. Comparator; 130. Voltage regulation unit;

[0031] 200. Timing module;

[0032] 300. Power supply mode determination module.

[0033] The realization of the purpose, functional features and advantages of this utility model will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation

[0034] The technical solutions of the present utility model will be clearly and completely described below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are only some embodiments of the present utility model, and not all embodiments. Based on the embodiments of the present utility model, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of the present utility model.

[0035] It should be noted that the descriptions involving "first," "second," etc., in this utility model are for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined with "first" or "second" may explicitly or implicitly include at least one of those features. Furthermore, the technical solutions of the various embodiments can be combined with each other, but this must be based on the ability of those skilled in the art to implement them. If the combination of technical solutions is contradictory or impossible to implement, such a combination of technical solutions should be considered non-existent and not within the scope of protection claimed by this utility model.

[0036] Unlike existing synchronous rectifier chips that use self-powered or externally powered systems, resulting in low system efficiency and high power consumption, this solution proposes a chip-powered intelligent detection circuit to reduce power consumption and improve system efficiency. The specific structure of this chip-powered intelligent detection circuit is described in the following embodiment.

[0037] Please refer to Figure 4 , Figure 4This is a circuit diagram of an intelligent detection circuit for chip power supply mode according to an embodiment of the present invention. In this embodiment, the intelligent detection circuit for chip power supply mode includes: an LDO module 100, a timing module 200, and a power supply mode determination module 300. The LDO module 100 is electrically connected to the timing module 200, the timing module 200 is electrically connected to the power supply mode determination module 300, and the power supply mode determination module 300 is electrically connected to the LDO module.

[0038] The LDO module 100 includes an LDO power stage unit 110, a comparator 120, and a voltage adjustment unit 130. The LDO power stage unit 110 is electrically connected to the voltage adjustment unit 130. The negative input terminal of the comparator 120 is electrically connected to the voltage adjustment unit 130, and the positive input terminal of the comparator 120 is connected to a resistor-divided voltage. The output terminal of the comparator 120 outputs the target voltage. The LDO power stage unit 110 is used to output a power supply signal VCC based on the VD signal. The target voltage is selected by the ModeDone signal. When ModeDone is low (0), it indicates that the power supply mode determination is not complete. In this case, a higher LDO output voltage can be set, which is higher than the target voltage required for normal operation. When ModeDone is high (1), it indicates that the power supply mode determination is complete. In this case, the LDO output voltage is adjusted to the target voltage required for normal operation. The output of the comparator 120 is set as the LDOhigh signal. When LDOhigh=0, it means that the LDO output voltage is lower than the target voltage; when LDOhigh=1, it means that the LDO output voltage reaches or exceeds the target voltage. The voltage adjustment unit 130 can adjust the target voltage.

[0039] The timing module 200 is used to acquire the power signal VCC, start timing when the power signal VCC reaches a preset reference voltage, set a target time, and output a timing signal according to the relationship between the timing and the target time. The input of the timing module 200 is the power signal VCC or the power signal VCC and the VD signal. The target time is the TIMEOUT time. When the timing has not reached the TIMEOUT time, TIMEOUT=0, that is, the timing signal is low level; when the timing has reached the TIMEOUT time, TIMEOUT=1, that is, the timing signal is high level.

[0040] The power supply mode determination module 300 is used to synchronously acquire timing signals and target signals, and determine the power supply mode by detecting the order of the rising edges of the timing signals and target signals. The power supply mode determination module 300 is used to determine the chip's power supply mode. Its input signals are TIMEOUT and LDOhigh. The power supply mode is determined by judging the order in which the high levels of the TIMEOUT and LDOhigh signals arrive, and then the module outputs ModeDone, SelfMode, and ExtMode based on the power supply mode.

[0041] Specifically, when the rising edge of the timing signal arrives first, the chip's power supply mode is determined to be external VOUT power supply mode. At this time, ModeDone=1, SelfMode=0, ExtMode=1 are output, and the LDO power stage unit 110 is disabled to save power consumption. When the rising edge of the target signal arrives first, the chip's power supply mode is determined to be self-powered mode, and ModeDone=1, SelfMode=1, ExtMode=0 are output. The LDO module 100 continues to work, and the target voltage is adjusted according to the ModeDone signal to the target voltage for normal circuit operation to avoid the problem of low system efficiency caused by the target voltage being too low.

[0042] In summary, this solution, by introducing a timing module 200 and a power supply mode determination module 300, and in conjunction with the target output voltage adjustment mechanism of the LDO overall module 100, can achieve intelligent determination of the chip's power supply mode.

[0043] In one specific embodiment, the voltage adjustment unit 130 includes a switch group and voltage divider resistors. The switch group includes a first switch k1 and a second switch k2 connected in parallel. One end of the first switch k1 and the second switch k2 are connected to the negative input terminal of the comparator 120, and the other end are respectively connected to different nodes of the voltage divider resistors for selection according to the ModeDone signal. The voltage divider resistors include a first resistor R1, a second resistor R2, and a third resistor R3 connected in series. The first switch k1 is connected to the common node connecting the first resistor R1 and the second resistor R2, and the second switch k2 is connected to the common node connecting the second resistor R2 and the third resistor R3. The first resistor R1 is connected to the LDO power stage unit 110, and the third resistor R3 is grounded.

[0044] Specifically, when the first switch k1 is turned on, the voltage at the negative input terminal of the comparator 120 is at a high potential, and when the second switch k2 is turned on, the voltage at the negative input terminal of the comparator 120 is at a low potential.

[0045] Understandably, when the first switch k1 is turned on, the second switch k2 is off, and the negative input of comparator 120 is at a high potential, which is the potential of the second resistor R2 and the third resistor R3 relative to ground. When the second switch k2 is turned on and the first switch k1 is off, the negative input of comparator 120 is at a low potential, which is the potential of the third resistor R3 relative to ground. The positive input of comparator 120 is connected to a resistor divider voltage, and the negative input is connected to the turn-on potential of the switch group. When the voltage value of the resistor divider voltage is greater than the turn-on potential, the output LDOhigh of comparator 120 is 1; when the voltage value of the resistor divider voltage is less than the turn-on potential, the output LDOhigh of comparator 120 is 0.

[0046] Specifically, when the ModeDone signal is high, the first switch k1 is turned on, and the target voltage is adjusted to the target voltage for normal circuit operation; when the ModeDone signal is low, the second switch k2 is turned on, and the target output voltage is set to a higher value.

[0047] In one specific embodiment, different resistor voltage dividers can be set to adjust the target voltage. There are two resistor voltage dividers: a first resistor voltage divider and a second resistor voltage divider. The first resistor voltage divider is located between the first resistor R1 and the second resistor R2, and the second resistor voltage divider is located between the second resistor R2 and the third resistor R3. When the ModeDone signal is high, the first resistor voltage divider is selected by the first switch k1; when the ModeDone signal is low, the second resistor voltage divider is selected by the second switch k2. The first resistor voltage divider is higher than the second resistor voltage divider. In this embodiment, the resistor voltage divider selected by the first switch k1 is higher than the voltage divider selected by the second switch k2, therefore the target VCC voltage corresponding to k1 is relatively low. Because the first switch k1 selects a relatively high voltage divider, it means that when the VCC voltage is relatively low, the voltage divider value corresponding to the first switch k1 is equal to the reference voltage Vref.

[0048] In one specific embodiment, the timing module 200 times a fixed duration.

[0049] When the fixed duration is less than the target time, the output timing signal is low; when the fixed duration is equal to the target time, the output timing signal is high. In this solution, the timing module 200 does not need to be connected to the VD signal.

[0050] In one parallel scheme, the timing module 200 counts the number of pulses of the VD signal.

[0051] When the number of pulses in the VD signal is less than the number of pulses in the target time, the output timing signal is low; when the number of pulses in the VD signal is equal to the number of pulses in the target time, the output timing signal is high. In this scheme, the timing module 200 needs to be connected to the VD signal.

[0052] In one parallel scheme, the timing module 200 times the duration of the effective high level of the VD signal.

[0053] When the duration of the effective high level of the VD signal is less than the target time, the output timing signal is low; when the duration of the effective high level of the VD signal is equal to the target time, the output timing signal is high. In this scheme, the timing module 200 needs to be connected to the VD signal.

[0054] Please refer to Figure 5 , Figure 5 A waveform diagram of the intelligent detection circuit in the self-powered mode of the chip power supply mode according to an embodiment of the present invention;

[0055] According to the circuit implementation principle of this scheme, when the chip is connected in self-powered mode, since the VCC pin is connected to a capacitor and not to VOUT, the LDO circuit can charge the VCC voltage to a preset higher target voltage before the TIMEOUT time ends. At this time, LDOhigh=1. When the preset TIMEOUT time width is encountered, the chip will determine that it is in self-powered mode. Therefore, SelfMode=1, ExtMode=0, and the LDO continues to work. Subsequently, the target voltage of the LDO is readjusted to the voltage required for normal operation. The key signal is the waveform shown below. Figure 5 As shown.

[0056] Please refer to Figure 6 , Figure 6 This is a waveform diagram of the intelligent detection circuit for chip power supply mode in an embodiment of this utility model under external VOUT power supply mode. When the chip is connected to external VOUT power supply, the VCC voltage is equal to VOUT. The VOUT voltage is the output voltage of the system operation. The LDO cannot raise it higher, as this voltage is lower than the preset higher voltage value of the LDO. Therefore, LDOhigh=0. When TIMEOUT=1, the chip will determine that it is in external VOUT power supply mode. Therefore, SelfMode=0, ExtMode=1, and the LDO will stop working to reduce power consumption and improve efficiency. Key signals and waveforms are as follows. Figure 6 As shown.

[0057] Please refer to Figure 7 , Figure 7This is a flowchart illustrating a detection method for an intelligent detection circuit of chip power supply mode according to an embodiment of the present invention. In this embodiment, the intelligent detection circuit of chip power supply mode includes: an LDO module 100, a timing module 200, and a power supply mode determination module 300. The LDO module 100 is electrically connected to the timing module 200, the timing module 200 is electrically connected to the power supply mode determination module 300, and the power supply mode determination module 300 is electrically connected to the LDO module. The detection method includes the following steps:

[0058] S110. Obtain the target voltage and power signal VCC output by the LDO module 100 based on the VD signal;

[0059] S120: Start timing when the power signal VCC reaches the preset reference voltage, set the target time, and output a timing signal according to the relationship between the timing and the target time;

[0060] S130. The power supply mode is determined by detecting the rising edges of the timing signal and the target signal in sequence.

[0061] Specifically, when the rising edge of the timing signal arrives first, the chip's power supply mode is determined to be the external VOUT power supply mode, and the LDO power stage unit 110 is disabled; when the rising edge of the target signal arrives first, the chip's power supply mode is determined to be the self-powered mode and the ModeDone signal is output, the LDO module 100 continues to work, and the target voltage is adjusted to the target voltage for normal circuit operation according to the ModeDone signal.

[0062] In the various embodiments of this application, the functional modules can be integrated into one processing module, or each module can exist physically separately, or two or more modules can be integrated into one module. It should be noted that, for the foregoing method embodiments, for the sake of simplicity, they are all described as a series of actions. However, those skilled in the art should understand that this application is not limited to the described order of actions, because according to this application, some steps can be performed in other orders or simultaneously. Furthermore, those skilled in the art should also understand that the embodiments described in the specification are all preferred embodiments, and the actions and modules involved are not necessarily essential to this application.

[0063] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions of other embodiments.

[0064] The above description is only a preferred embodiment of the present utility model and does not limit the patent scope of the present utility model. All equivalent structural transformations made under the inventive concept of the present utility model using the contents of the present utility model specification and drawings, or direct / indirect applications in other related technical fields, are included within the patent protection scope of the present utility model.

Claims

1. A smart detection circuit with a chip-powered mode, characterized in that, include: The LDO module comprises an overall module, a timing module, and a power supply mode determination module. The overall LDO module is electrically connected to the timing module, the timing module is electrically connected to the power supply mode determination module, and the power supply mode determination module is electrically connected to the LDO module. The LDO module includes an LDO power stage unit, a comparator, and a voltage adjustment unit. The LDO power stage unit is electrically connected to the voltage adjustment unit. The negative input terminal of the comparator is electrically connected to the voltage adjustment unit. The positive input terminal of the comparator is connected to a resistor-divided voltage. The output terminal of the comparator outputs the target voltage. The LDO power stage unit is used to output a power signal VCC based on the VD signal. The timing module is used to acquire the power signal VCC, start timing when the power signal VCC reaches a preset reference voltage, set a target time, and output a timing signal according to the relationship between the timing and the target time. The timing of the timing module is a fixed duration. When the fixed duration is less than the target time, the output timing signal is low level; when the fixed duration is equal to the target time, the output timing signal is high level. The power supply mode determination module is used to synchronously acquire timing signals and target signals, and detect the order of the rising edges of the timing signals and target signals to determine the power supply mode. Specifically, when the rising edge of the timing signal arrives first, the chip's power supply mode is determined to be external VOUT power supply mode, and the LDO power stage unit is disabled; when the rising edge of the target signal arrives first, the chip's power supply mode is determined to be self-powered mode and a ModeDone signal is output, the LDO module continues to work, and the target voltage is adjusted to the target voltage for normal circuit operation according to the ModeDone signal.

2. The intelligent detection circuit with chip power supply mode as described in claim 1, characterized in that, The voltage adjustment unit includes a switch group and a voltage divider resistor. The switch group includes a first switch and a second switch connected in parallel for selection according to the ModeDone signal. The voltage divider resistor includes a first resistor, a second resistor, and a third resistor connected in series. The first switch is connected to the common node where the first resistor and the second resistor are connected, and the second switch is connected to the common node where the second resistor and the third resistor are connected. Specifically, when the first switch is turned on, the voltage at the negative input terminal of the comparator is at a high potential, and when the second switch is turned on, the voltage at the negative input terminal of the comparator is at a low potential.

3. The intelligent detection circuit with chip power supply mode as described in claim 2, characterized in that, When the ModeDone signal is high, the first switch is activated to adjust the target voltage to the target voltage for normal circuit operation; when the ModeDone signal is low, the second switch is activated to set the target output voltage to a higher value.

4. The intelligent detection circuit with chip power supply mode as described in claim 2, characterized in that, The resistor divider voltage has two components: a first resistor divider voltage and a second resistor divider voltage. The first resistor divider voltage is located between the first resistor and the second resistor, and the second resistor divider voltage is located between the second resistor and the third resistor. When the ModeDone signal is high, the first resistor divider voltage is selected by a first switch; when the ModeDone signal is low, the second resistor divider voltage is selected by a second switch. The first resistor divider voltage is higher than the second resistor divider voltage.

5. The intelligent detection circuit for chip power supply mode as described in claim 1, characterized in that, The timing module counts the number of pulses in the VD signal. When the number of pulses in the VD signal is less than the number of pulses in the target time, the output timing signal is low; when the number of pulses in the VD signal is equal to the number of pulses in the target time, the output timing signal is high.

6. The intelligent detection circuit with chip power supply mode as described in claim 1, characterized in that, The timing module counts the duration of the effective high level of the VD signal. When the effective high-level time of the VD signal is less than the target time, the output timing signal is low; when the effective high-level time of the VD signal is equal to the target time, the output timing signal is high.

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