Link average based precision instrument sampling noise suppression circuit

Abstract

The utility model discloses a kind of precision instrument sampling noise suppression circuit based on link average, belong to sensor noise suppression technical field, signal source connects operational amplifier, operational amplifier carries out conditioning to the signal from signal source, then input to ADC driver, ADC driver is connected with analog-digital converter by multiple independent channels formed by different signal lines of multiple paths, ADC driver converts signal source signal into the reference voltage range of analog-digital converter;Analog-digital converter is accessed FPGA chip by signal line, and the data of multiple paths are received by FPGA chip simultaneously;FPGA chip is transmitted to host computer by communication connector after data processing. Compared with the noise index of the sampling average technology without using signal link, the scheme of the utility model is under different sampling rate conditions, noise is greatly attenuated. It is shown that the scheme of the utility model can realize better noise suppression effect.

Description

Technical Field

[0001] This utility model belongs to the field of signal acquisition and processing technology, specifically relating to a precision instrument sampling noise suppression circuit based on link averaging. Background Technology

[0002] In the process of modern digital development, condition monitoring and data analysis are crucial for equipment operation and maintenance. Condition monitoring and data analysis is a technology that monitors the operating status of equipment through real-time data acquisition and analysis. It can provide an accurate assessment of the equipment's health status and help predict potential failures and optimize maintenance plans. By continuously monitoring equipment operating parameters such as temperature, vibration, pressure, and displacement, condition monitoring systems can promptly detect anomalies and potential failures, allowing for timely maintenance measures. This avoids unexpected downtime and production interruptions, minimizes production losses and costs, and thus improves equipment reliability and production efficiency.

[0003] The realization of condition monitoring and data analysis is inseparable from precision instruments. Among precision instruments, noise pollution is one of the issues that must be taken seriously. Noise pollution can hinder the entire system's understanding and analysis of the received signal source information, ultimately leading to the monitoring system's incorrect judgment of the signal source information and incorrect execution of instructions, which greatly reduces the reliability of the monitoring system.

[0004] Noise is an unpredictable random signal that can only be understood using probability and statistics. Noise is generally divided into external noise and internal noise. External noise, also known as system noise, is mainly caused by noise pollution from various system components such as sensor input, acquisition, and processing. Internal noise, also known as equipment noise, is mainly caused by noise pollution from analog circuits, digital circuits, mixed analog-digital noise, and analog-digital quantization noise within the monitoring equipment. Only by properly handling both external and internal noise pollution can the entire data acquisition and monitoring system operate more reliably and effectively over the long term.

[0005] Given that the inherent noise of precision instrument circuits, power supply noise, spatial interference, and digital system interference cannot be further optimized, but the actual application environment is extremely sensitive to noise, how to further improve the noise performance of precision instruments has become an urgent problem to be solved. Summary of the Invention

[0006] The technical problem solved by this utility model is: by redesigning the signal link and using the sampling averaging technology of the signal link, this utility model can further improve the noise index of precision instruments.

[0007] Technical solution: To solve the above-mentioned technical problems, the technical solution adopted by this utility model is as follows:

[0008] A precision instrument sampling noise suppression circuit based on link averaging includes a signal source, an operational amplifier, an ADC driver, an analog-to-digital converter (ADC), an FPGA chip, and a communication connector connected in sequence. The FPGA chip is connected to the ADC via multiple signal lines, driving the ADC. The signal source is connected to the operational amplifier, which conditions the signal from the source before inputting it to the ADC driver. The ADC driver is connected to the ADC via multiple independent channels formed by different signal lines, converting the source signal into a voltage range within the ADC's reference voltage range. The ADC is connected to the FPGA chip via signal lines, allowing the FPGA chip to simultaneously receive data from multiple channels. After processing the data, the FPGA chip transmits it to a host computer via the communication connector.

[0009] Furthermore, the multiple signal lines connecting the FPGA chip to the analog-to-digital converter include DCLK, DRDY, and DOUT[3:0] signal lines.

[0010] Furthermore, the FPGA chip drives the analog-to-digital converter, converting the analog signal source into a digital signal through the DCLK, DRDY, and DOUT signal lines. Data from multiple channels is simultaneously received by the FPGA chip. Although the multiple signals exist independently in the circuit, they are connected to the same source signal. The instantaneous expressions of the signals are correlated, while the instantaneous expressions of the noise are uncorrelated. The FPGA chip performs a right shift operation of 3 bits on the actual data to recover the original signal.

[0011] Furthermore, each channel of the analog-to-digital converter (ADC) shares a single source signal, which is then connected in parallel with resistors at the output of the ADC driver.

[0012] Furthermore, the operational amplifier and ADC driver constitute a minimalist precision signal conditioning chain.

[0013] Furthermore, the operational amplifier used is the ADA4898-2 operational amplifier, with a noise level of 0.9 nV / Hz.

[0014] Furthermore, it includes a power supply circuit, which uses a low-noise LDO regulator with a noise level of 0.8uVrms.

[0015] Beneficial effects: Compared with the prior art, the present invention has the following advantages:

[0016] This invention relates to a precision instrument sampling noise suppression circuit based on link averaging. Addressing the limitation of existing circuits where noise cannot be optimized, it uses a single-chip analog-to-digital converter (ADC) to acquire one signal. The signal, after passing through an ADC driver, enters four channels of the ADC for simultaneous sampling. The data from all four channels is simultaneously received by the FPGA chip. While the four signals exist independently in the circuit, they are all connected to the same source signal. The instantaneous expressions of the signals are correlated, while the instantaneous expressions of the noise are uncorrelated. Therefore, the FPGA chip only needs to right-shift the actual data by 3 bits to recover the original signal. Because the instantaneous expressions of the noise are uncorrelated, the amplitude is significantly attenuated.

[0017] A comparison of noise performance without and with the sampling averaging technique using the signal link shows that noise is significantly reduced under different sampling rates. This demonstrates that the solution of this invention can achieve good noise suppression. Attached Figure Description

[0018] Figure 1 This is a schematic diagram illustrating the principle of the present invention.

[0019] Figure 2 This is a schematic diagram of the signal conditioning link of this utility model.

[0020] Figure 3 is a schematic diagram of the analog-to-digital converter of this utility model. Figure 3(a) is a circuit schematic diagram of the analog-to-digital converter U8, and Figure 3(b) is a power supply circuit schematic diagram of the analog-to-digital converter.

[0021] Figure 4 This is a schematic diagram of the FPGA chip acquisition part of the present invention.

[0022] Figure 5 This is a schematic diagram of the gigabit network communication principle of this utility model.

[0023] Figure 6 The noise index diagram is for a sampling rate of 102.4KHz without the use of the technology of this utility model.

[0024] Figure 7 The noise index diagram is shown for the application of this invention at a sampling rate of 102.4 kHz. Detailed Implementation

[0025] The present invention will be further illustrated below with reference to specific embodiments. The embodiments are implemented based on the technical solution of the present invention. It should be understood that these embodiments are only used to illustrate the present invention and are not intended to limit the scope of the present invention.

[0026] like Figure 1As shown, the present invention provides a precision instrument sampling noise suppression circuit based on link averaging, which lays out and constructs a precision signal link and introduces the sampling averaging technology of the signal link into the precision signal link.

[0027] like Figure 1 The diagram shown is a circuit block diagram of this utility model. Figure 1 As shown, the sampling and averaging technology framework of the signal link mainly consists of a precision signal link that cannot be further optimized, an XC7A35T-2FGG484I FPGA chip, and an RTL8211 gigabit network PHY chip. Specifically, it includes the signal source (sensor signal) CH1+, CH1-, operational amplifier UA6, ADC driver U5, analog-to-digital converter U8, FPGA chip U23D, communication connector U23D, and multiple power supply circuits, etc.

[0028] The signal source (sensor signal) CH1+, CH1-, operational amplifier UA6, ADC driver U5, analog-to-digital converter U8, FPGA chip U23D, and communication connector U29 are connected in sequence. FPGA chip U23D is connected to ADC U8 via DCLK, DRDY, and DOUT[3:0] signal lines, driving ADC U8. The signal source is connected to operational amplifier UA6, which conditions the incoming signal and then inputs it to ADC driver UA6. ADC driver UA6 is connected to ADC U8 via multiple independent channels formed by different signal lines (four in this embodiment), converting the full-scale signal source signal into a voltage range within the reference range of ADC U8. ADC U8 is connected to FPGA chip U23D via DOUT[3:0] signal lines, and the data from the four channels is simultaneously received by FPGA chip U23D. After processing, FPGA chip U23D transmits the processed data to the host computer via communication connector U29.

[0029] In this embodiment, the FPGA chip U23D is model XC7A35T-2FGG484I, the analog-to-digital converter U8 is model AD7771BCPZ, the ADC driver U5 is model ADA4945-1ACPZ-R7, the communication connector U29 uses a gigabit network PHY chip of model RTL8211, and the operational amplifier UA6 is model ADA4898-2.

[0030] like Figure 2The diagram shows the schematic of the precision signal conditioning link of this invention. The operational amplifier UA6 and the ADC driver U5 constitute a very simple precision signal conditioning link. The operational amplifier UA6 conditions the signal from the source (sensor signal), and the ADC driver U5 converts the full-scale source signal into the reference voltage range of the analog-to-digital converter.

[0031] The sensor signal CH1 is connected to the non-inverting input 3 of operational amplifier UA6 via transient voltage suppression diode D1, capacitor C25, inductor L1, capacitor C26, and capacitor C22. The non-inverting input 3 of operational amplifier UA6 is grounded via resistor R11. Output 1 is directly fed back to the inverting input 2. Output 1 is connected to the input IN of ADC driver U5 via resistor R9, and further connected to the -FB port of ADC driver U5 via resistors R9 and R8. ADC driver U5 outputs two differential signals. The output +OUT of ADC driver U5 is connected to the input of analog-to-digital converter U8 via resistor R13 and grounded via capacitor C24. The output -OUT of ADC driver U5 is connected to the input of analog-to-digital converter U8 via resistor R10 and grounded via filter capacitor C21. Capacitor C23 is connected in parallel between the two differential signal lines CH1OUTN and CH1OUTP. The output of ADC driver U5 first passes through two buffer resistors, so that the ADC driver is not affected by the switching quantization during the ADC sampling process. Then, the differential signal after passing through the buffer resistors is connected to the ADC's eight input ports for sampling and averaging.

[0032] After the sensor signal enters the link, it undergoes the first stage of tracking through the ADA4898-2 operational amplifier UA6. The tracked signal then enters the ADA4945-1ACPZ-R7 low-noise ADC driver U5 and is converted into two pairs of differential signals adapted to the analog-to-digital converter U8.

[0033] The ADA4898-2 operational amplifier is an ultra-low noise operational amplifier with a noise level of 0.9 nV / Hz. It is a unity-gain, voltage-feedback operational amplifier with a built-in linear, low-noise input stage and internal compensation, enabling high slew rate and low noise. The ADA4945-1ACPZ-R7 ADC driver is an ultra-low noise ADC driver with a noise level of 1.8 nV / Hz, low harmonic distortion, and low power analog-to-digital converter driver.

[0034] like Figure 2As shown, the power supply for the precision signal conditioning link includes power supply circuits U1, U2, and U3. Power supply circuit U1 uses an ADI LT3045EDD#PBF LDO to step down a 15V DC voltage to a 12V DC voltage, with a noise level of 0.8uVrms. Power supply circuit U3 uses an ADI LT3094EDD#PBF LDO to step down a -15V DC voltage to a -12V DC voltage, with a noise level of 0.8uVrms. Power supply circuit U2 uses an LT3045EDD#PBF to step down a 12V voltage to a 3.3V voltage. The ±12V low-noise power supply mainly supplies the ADA4898-2 low-noise operational amplifier UA6, and the 3.3V low-noise power supply supplies the ADA4945-1ACPZ-R7 low-noise ADC driver U5.

[0035] Since the noise signal is a random signal and the noise vector takes the form of Gaussian, this invention utilizes the inherent signal characteristics of noise to acquire one signal. After passing through the ADC driver, the signal enters the eight channels of the analog-to-digital converter for simultaneous sampling.

[0036] As shown in Figure 3, Figure 3(a) is the circuit schematic diagram of the analog-to-digital converter U8 of this utility model. The AIN[3:0] input port of the analog-to-digital converter U8 is simultaneously connected to 8 signals CH1 N and CH1 P. The DOUT[3:0] output port of the analog-to-digital converter U8 is connected to the input terminal of the FPGA chip U23D.

[0037] Figure 3(b) shows the power supply circuit schematic of the analog-to-digital converter. The power supply circuit U7 uses an LT3045EDD#PBF type LDO to step down the 3.3V voltage provided by the power supply circuit U2 to a voltage of 1.8V to supply the analog-to-digital converter U8. The noise level of the LT3045EDD#PBF is 0.8uVrms. The reference reference REF is provided by an LTC6655BHMS8-2.5#TRPBF.

[0038] like Figure 4The diagram shows the circuit schematic of the FPGA chip acquisition section of this utility model. The AD7771BCPZ analog-to-digital converter U8 is driven by the FPGA chip U23D. The main driving signal lines are DCLK, DRDY, DOUT[3:0], and MCLK. MCLK is output by the FPGA chip and provides the main clock for the FPGA chip U8. DCLK is output by the FPGA chip U8 and provides the data clock after frequency division for the FPGA chip. DRDY is output by the FPGA chip U8 and provides the preparation signal for the completion of data conversion for the FPGA chip. DOUT[3:0] is output by the FPGA chip U8, and the FPGA chip U23D obtains the converted data through DOUT[3:0]. The FPGA chip converts the analog signal source into a digital signal through the DCLK, DRDY, and DOUT[3:0] signal lines. After the data reaches the FPGA chip, the FPGA chip shifts the data right by 3 bits. The processed data is then sent to the host computer through the RGMII-driven RTL8211EG-VB-VG physical layer chip.

[0039] The FPGA chip mainly drives the analog-to-digital converter. Data from four channels is received by the FPGA chip simultaneously. The four signals exist independently in the circuit, but they are connected to the same source signal. The instantaneous expressions of the signals are correlated, while the instantaneous expressions of the noise are uncorrelated. Therefore, the FPGA chip only needs to right-shift the actual data by 3 bits to recover the original signal. Because the instantaneous expressions of the noise are uncorrelated, the amplitude is greatly attenuated.

[0040] like Figure 5 The diagram shown illustrates the gigabit network communication principle of this invention. The FPGA chip drives the RTL8211 gigabit network PHY chip to ultimately complete data transmission. A gigabit network connector is used for communication, uploading real-time collected data to a host computer. The host computer displays the noise suppression performance of the signal link's sampling averaging technique at different sampling rates.

[0041] The sampling and averaging technology for signal links in this invention is based on the premise that the noise in precision signal links can no longer be optimized through methods such as selecting components, improving structure, and controlling interference. This is mainly reflected in:

[0042] (1) Circuit noise: The noise generated by the operational amplifier circuit, including resistors, at the circuit output is optimized. The circuit uses the ADI ADA4898-2 operational amplifier to form a precision signal link. The resistor values ​​are selected by using the optimal solution.

[0043] (2) Power supply noise: The noise and ripple generated at the output terminal of the power supply are optimized. For example, the circuit uses the ADI LT3045 low dropout regulator (LDO) to power the precision signal link and the ADI LTC6655LNB-4.096 reference voltage to power the analog-to-digital converter. The extremely low noise power supply system provides low noise power supply for the precision signal link and analog-to-digital conversion circuit.

[0044] (3) Spatial interference: The noise entering the circuit output through spatial coupling from outside the circuit system has been optimized, and the circuit board has shielded each precision signal link, etc.

[0045] (4) Digital system interference: The processor system of the analog-to-digital converter is optimized in terms of layout and wiring.

[0046] Based on the above, this utility model draws on the idea of ​​parallel resistors reducing the resistance value. Previously, each channel of the analog-to-digital converter separately acquired a source signal, resulting in noise in the output. Now, we consider acquiring a single source signal from each channel and then averaging the acquired signals. For the source signal, the signal is additive, and the amplitude remains unchanged after averaging. For the noise signal, the amplitude after averaging is similar to the principle of parallel resistors: 2 in parallel equals 0.707 times, 4 in parallel equals 0.5 times, 8 in parallel equals 0.354 times, 16 in parallel equals 0.25 times, and so on. With n in parallel, the noise becomes √n times the original value.

[0047] For noise, for example, if there are four signal sources sampling and averaging the signal link, then the instantaneous expression at the output is Un5(t) = 0.25(Un1(t) + Un2(t) + Un3(t) + Un4(t)). Because the four instantaneous expressions are uncorrelated, the final Un5 = =0.5Un, meaning the noise output after parallel connection is 0.5 times the noise output of a single amplifier. However, for the signal, the final instantaneous expression at the output terminal is still the average value of the outputs of the four amplifiers. Since the output values ​​of the four amplifiers are exactly the same, the final output is exactly the same as the output of a single amplifier.

[0048] The signal link sampling and averaging technology of this invention has been applied in product testing and is running stably. Comparison results with other existing circuits in actual testing are shown in Table 1 and... Figure 5-6 As shown.

[0049] Table 1. Comparison of noise performance without and with the present invention under different sampling rates.

[0050] Sampling rate Link averaging technology was not used. Using link averaging technology Attenuation factor 102.4Ksps 33.5uVrms 11.5uVrms 0.343 51.2Ksps 23.2uVrms 7.9uVrms 0.341 25.6Ksps 16.3uVrms 5.56uVrms 0.341 12.8Ksps 28.6uVrms 9.8uVrms 0.343 6.4Ksps 19.6uVrms 6.6uVrms 0.337 3.2Ksps 13.4uVrms 4.62uVrms 0.345 1.6Ksps 5.63uVrms 1.95uVrms 0.346

[0051] Figure 5 The noise performance is calculated at a sampling rate of 102.4 kHz without employing sampling averaging techniques in the signal link. Figure 6 Under a sampling rate of 102.4 kHz, the noise performance of the signal link sampling averaging technique was compared. The noise level without the technique was 33.5 μVrms, while the noise level with the technique was 11.5 μVrms. The actual noise attenuation was 0.343 times, and the theoretical noise attenuation was 0.354 times. This demonstrates the feasibility of the signal link sampling averaging technique. Figure 5 and Figure 6 It is clear that the noise index under the sampling rate of 102.4Ksps is lower than that of the technical solution of this utility model.

[0052] Table 1 compares the noise performance of the sampling averaging technique without the signal link with the sampling averaging technique under different sampling rates. Under different sampling rate conditions, the actual attenuation factor is basically consistent with the theoretically calculated attenuation factor.

[0053] The above description is only a preferred embodiment of the present utility model. It should be noted that for those skilled in the art, several improvements and modifications can be made without departing from the principle of the present utility model, and these improvements and modifications should also be considered within the protection scope of the present utility model.

Claims

1. A precision instrument sampling noise suppression circuit based on link averaging, characterized in that: The system includes a signal source, an operational amplifier, an ADC driver, an analog-to-digital converter (ADC), an FPGA chip, and a communication connector, connected in sequence. The FPGA chip is connected to the ADC via multiple signal lines and drives the ADC to operate. The signal source is connected to the operational amplifier, which conditions the signal from the signal source and then inputs it to the ADC driver. The ADC driver is connected to the ADC via multiple independent channels formed by multiple different signal lines, and converts the signal source signal into a voltage range within the reference voltage range of the ADC. The analog-to-digital converter is connected to the FPGA chip via signal lines, and data from multiple channels is simultaneously received by the FPGA chip. After processing the data, the FPGA chip transmits it to the host computer via a communication connector.

2. The precision instrument sampling noise suppression circuit based on link averaging according to claim 1, characterized in that: The multiple signal lines connecting the FPGA chip to the analog-to-digital converter include DCLK, DRDY, and DOUT signal lines.

3. The precision instrument sampling noise suppression circuit based on link averaging according to claim 1, characterized in that: The FPGA chip drives the analog-to-digital converter, which converts the analog signal source into a digital signal through the DCLK, DRDY, and DOUT signal lines. Data from multiple channels is received by the FPGA chip simultaneously. Although the multiple signals exist independently in the circuit, they are connected to the same source signal. The instantaneous expressions of the signals are correlated, while the instantaneous expressions of the noise are uncorrelated. The FPGA chip performs a right shift operation of 3 bits on the actual data to recover the original signal.

4. The precision instrument sampling noise suppression circuit based on link averaging according to claim 1, characterized in that: Each channel of the analog-to-digital converter (ADC) shares a common source signal, which is then connected in parallel with resistors at the output of the ADC driver.

5. The precision instrument sampling noise suppression circuit based on link averaging according to claim 1, characterized in that: Operational amplifiers and ADC drivers constitute a precision signal conditioning link.

6. The precision instrument sampling noise suppression circuit based on link averaging according to claim 5, characterized in that: The operational amplifier used is the ADA4898-2, with a noise level of 0.9nV / Hz.

7. The precision instrument sampling noise suppression circuit based on link averaging according to claim 1, characterized in that: It also includes multiple power supply circuits, which use low-noise LDO regulators with a noise level of 0.8uVrms.

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