Carrier plate and system for heterojunction PVD coating

Abstract

The application provides a carrier plate and system for heterojunction PVD coating, which comprises a detachable carrier plate body and a baffle. The carrier plate body is used for carrying silicon wafers to ensure that the silicon wafers maintain stable positions during the coating process and guarantee the uniformity and quality of the coating. The silicon wafers are used for receiving sputtering coating of target materials, and the baffle is used for impacting the silicon wafers falling between the anode shield plate and the target material to prevent the target material from being conducted with the shield plate due to the accumulation of the silicon wafers, thereby avoiding the occurrence of problems such as abnormal glow discharge and ensuring the normal operation of the equipment and the production efficiency. The carrier plate body and the baffle are arranged in a non-parallel manner, the silicon wafer carrying surface of the carrier plate body and the silicon wafer limiting surface of the baffle form a spatial included angle, and the silicon wafer carrying surface and the silicon wafer limiting surface are located in different plane dimensions. That is, when the included angle formed by the two is an acute angle, a right angle or an obtuse angle, the baffle can impact the silicon wafers, thereby achieving effective management of the silicon wafers and stable operation of the equipment.

Description

Technical Field

[0001] This application relates to the field of solar cell manufacturing equipment technology, and in particular to a carrier plate and system for heterojunction PVD coating. Background Technology

[0002] The existing heterojunction PVD coating process mainly uses physical methods to detach atoms, molecules, and ions from the target material and sputter them from the surface, then they impact and adhere to the substrate. PVD stands for Physical Vapor Deposition.

[0003] However, as production time increases, it is inevitable that wafers will fall out in the chamber. If the silicon wafer falls between the target and the anode guard plate, it will cause the target and the anode guard plate to conduct, which will lead to abnormal ignition discharge. Abnormal ignition discharge will cause equipment shutdown, silicon wafer damage, target and guard plate damage, increase safety hazards, reduce battery performance, and make the product consistency worse.

[0004] It should be noted that the above content is not necessarily prior art, nor is it intended to limit the scope of patent protection of this application. Utility Model Content

[0005] This application provides a carrier plate and system for heterojunction PVD coating to solve the problem that when a silicon wafer falls between the target and the anode guard plate, it causes the target and the anode guard plate to conduct, resulting in abnormal ignition discharge. Abnormal ignition discharge can lead to equipment shutdown, silicon wafer damage, damage to the target and guard plate, increased safety hazards, reduced battery performance, and poor product consistency.

[0006] As one aspect of this application, this application provides a carrier plate for heterojunction PVD coating, comprising:

[0007] Detachable carrier plate body and baffle;

[0008] There is an included angle between the carrier plate body and the baffle, and the plane on the side of the carrier plate body used to support the silicon wafer is not coplanar with the plane on the side of the baffle used to collide with the silicon wafer.

[0009] Optionally, the baffle is configured to be made of a flexible material.

[0010] Optionally, the carrier plate body includes a plurality of first rods arranged along a first direction and a plurality of second rods arranged along a second direction, wherein the projection of any one of the first rods on the side of the carrier plate body used to support the silicon wafer is perpendicular to the projection of any one of the second rods on the side of the carrier plate body used to support the silicon wafer.

[0011] The plurality of first rods and the plurality of second rods form a plurality of hollowed-out receiving slots for carrying silicon wafers.

[0012] Optionally, the carrier plate body and the baffle are connected by a wire harness binding connection.

[0013] Optionally, the connection between the carrier plate body and the baffle is a plug-in connection or a tenon-and-mortise connection.

[0014] Optionally, at least one of the carrier plate body and the baffle is provided with a fixing hole, through which the wire harness is passed for binding and fixing.

[0015] Optionally, the carrier plate body is configured to be made of stainless steel.

[0016] As another aspect of the embodiments of this application, the embodiments of this application also provide a system for heterojunction PVD coating, including a carrier plate as described above, and a process cavity for providing a vacuum environment, wherein the carrier plate is located within the process cavity.

[0017] Optionally, it also includes a base, on which an anode guard plate and a target material are provided. The anode guard plate is fixedly connected to the base, and the target material abuts against the base and rotates relative to the base.

[0018] There is a gap between the anode guard plate and the target material.

[0019] Optionally, the length of the baffle is greater than or equal to the distance from the base to the surface of the target material, so as to ensure that the baffle can effectively impact the silicon wafer.

[0020] The embodiments of this application employing the above technical solution may include the following advantages: By setting a carrier plate including a carrier plate body and a baffle, the carrier plate body and the baffle are not parallel to each other, and the silicon wafer bearing surface of the carrier plate body and the silicon wafer limiting surface of the baffle form a spatial angle. The silicon wafer bearing surface and the silicon wafer limiting surface are located in different planar dimensions. Due to the setting of the baffle, when the carrier plate body passes through the process cavity, the baffle can impact the silicon wafer located between the anode guard plate and the target material. The silicon wafer will fall or break upon impact, terminating the abnormal start-up discharge, solving the problems of equipment shutdown, silicon wafer damage, and target and guard plate damage caused by abnormal start-up discharge, reducing safety hazards, improving battery performance, and improving product consistency. On the other hand, it is also unnecessary to open the process cavity, reducing the manpower required for cavity opening and reducing production capacity loss. Attached Figure Description

[0021] In the accompanying drawings, unless otherwise specified, the same reference numerals throughout the various drawings denote the same or similar parts or elements. These drawings are not necessarily drawn to scale. It should be understood that these drawings depict only some embodiments disclosed in this application and should not be construed as limiting the scope of this application.

[0022] Figure 1 A three-dimensional structural diagram of the carrier plate provided in the embodiments of this application;

[0023] Figure 2 This is a schematic diagram showing the state of the silicon wafer falling between the target and the anode guard plate in this embodiment.

[0024] Explanation of reference numerals in the attached figures:

[0025] 100-Silicon wafer; 1-Carrier plate body; 11-First rod; 12-Second rod; 13-Accommodation groove; 2-Baffle; 21-Fixing hole; 3-Anode guard plate; 4-Target material. Detailed Implementation

[0026] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be noted that, unless otherwise specified, the embodiments and features described in these embodiments can be combined with each other. The application will now be described in detail with reference to the accompanying drawings and embodiments.

[0027] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such terms can be used interchangeably where appropriate so that the embodiments of this application described herein can be implemented, for example, in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0028] In this application, the term "numerical interval" (i.e., numerical range) refers to a range of values. Unless otherwise specified, the distribution of selectable values ​​within this numerical interval is considered continuous, and includes the two endpoints (i.e., the minimum and maximum values) of the interval, as well as every value between these endpoints. Unless otherwise specified, when a numerical interval refers only to integers within that interval, it includes the two endpoints of the range and every integer between them, effectively listing every integer. When multiple numerical ranges are provided to describe features or characteristics, these ranges can be merged. In other words, unless otherwise specified, the numerical ranges disclosed in this application should be understood to include any and all subranges included therein. The "numerical value" in this numerical interval can be any quantitative value, such as a number, percentage, or proportion. The term "numerical interval" can broadly include percentage intervals, proportion intervals, ratio intervals, and other quantitative intervals.

[0029] Exemplary embodiments according to this application will now be described in more detail with reference to the accompanying drawings. It should be understood that these exemplary embodiments may be implemented in many different forms and should not be construed as being limited to the embodiments set forth herein.

[0030] Please see Figure 1 This utility model discloses a carrier plate for heterojunction PVD coating. The carrier plate includes a detachably connected carrier plate body 1 and a baffle 2. The side of the carrier plate body 1 used to support the silicon wafer 100 is defined as the silicon wafer bearing surface, ensuring that the silicon wafer 100 maintains a stable position during the coating process, thereby guaranteeing the uniformity and quality of the coating. The silicon wafer 100 receives the sputtered coating from the target material 4, which is a crucial step in the manufacturing of heterojunction cells and directly affects the cell's performance. The side of the baffle 2 used to impact the silicon wafer 100 falling between the anode guard plate 3 and the target material 4 is defined as the silicon wafer limiting surface, preventing the target material 4 from becoming conductive due to the accumulation of silicon wafers 100, thereby avoiding problems such as abnormal start-up discharge and ensuring the normal operation of the equipment and production efficiency. The carrier plate body 1 and the baffle 2 are not parallel to each other, and the silicon wafer bearing surface of the carrier plate body 1 and the silicon wafer limiting surface of the baffle 2 form a spatial angle. The silicon wafer bearing surface and the silicon wafer limiting surface are located in different planar dimensions, that is, the angle between the silicon wafer bearing surface and the silicon wafer limiting surface is not 0° and 180°. Only when the angle between the two is an acute angle, a right angle or an obtuse angle can the silicon wafer limiting surface of the baffle 2 play the role of impacting the silicon wafer 100. This design cleverly utilizes spatial and mechanical principles to achieve effective management of the silicon wafer 100 and stable operation of the equipment.

[0031] In an optional embodiment, the carrier body 1 includes a plurality of first rods 11 arranged along a first direction and a plurality of second rods 12 arranged along a second direction. The projection of any first rod 11 onto the silicon wafer bearing surface of the carrier body 1 is perpendicular to the projection of any second rod 12 onto the silicon wafer bearing surface. According to the above arrangement, the plurality of first rods 11 and second rods 12 form a plurality of rectangular frames. The rectangular frames are defined as receiving grooves 13. The receiving grooves 13 are used to support the silicon wafer 100, providing a stable and regular support platform for the silicon wafer 100, ensuring that the silicon wafer 100 will not be displaced or tilted during the coating process. Since the carrier plate is used to complete the heterojunction PVD coating, it needs to receive the atoms, molecules, ions and other substances sputtered from the target 4. Therefore, the receiving tank 13 is configured as a hollow type. This hollow design not only reduces the weight of the carrier plate and reduces the material cost, but more importantly, it allows the sputtered particles to reach the surface of the silicon wafer 100 without obstruction, thereby improving the efficiency and quality of the coating. At the same time, it is also conducive to the gas flow and heat dissipation in the chamber, maintaining the stability of the process environment.

[0032] In an optional embodiment, the connection between the carrier plate body 1 and the baffle 2 is configured as a wire harness bundling connection. This connection method is simple, practical, and easy to operate and maintain. At least one of the carrier plate body 1 and the baffle 2 is provided with a fixing hole 21, through which the wire harness is passed for bundling and fixing; in this embodiment, as shown... Figure 1 As shown, the baffle 2 has multiple fixing holes 21 at one end near the carrier plate body 1. The wire harness can pass through the fixing holes 21 and the receiving groove 13 on the carrier plate body 1 near the baffle 2 end for bundling. Alternatively, a through hole can be provided at the corresponding position on the carrier plate body 1, and the wire harness can pass through the fixing hole 21 and the through hole for bundling, thereby connecting the carrier plate body 1 and the baffle 2. When it is necessary to disconnect, the wire harness can be disassembled in a destructive or non-destructive manner, which facilitates quick disassembly and assembly during maintenance or replacement of the baffle 2, reduces downtime, and improves production efficiency.

[0033] In optional embodiments, the connection between the carrier plate body 1 and the baffle 2 is configured as a plug-in connection or a tenon-and-mortise connection. Specifically, one of the carrier plate body 1 and the baffle 2 is provided with an engaging protrusion, and the other is provided with an engaging groove. The engaging protrusion and the engaging groove are connected by plug-in or tenon-and-mortise connection to achieve a detachable connection between the carrier plate body 1 and the baffle 2. This mechanical connection method is not only firmly connected, but also has high reusability and can withstand certain mechanical and thermal stresses, ensuring that it will not loosen or fall off during long-term production. At the same time, it facilitates quick installation and disassembly by operators, improving the maintenance convenience and production flexibility of the equipment.

[0034] Preferably, the baffle 2 is made of a flexible material. In this embodiment, the baffle 2 is a silicone plate. This design prevents scratches or damage to the target 4 and / or the anode guard plate 3 when they come into relative contact, thus maintaining their normal operation. Silicone material not only has good flexibility but also excellent high-temperature resistance and chemical stability. It can operate stably for a long time in the high-temperature and plasma environment of PVD coating without being affected by aging or deterioration. Furthermore, its smooth surface makes it difficult for particulate matter to adhere, which helps maintain the cleanliness of the chamber and further improves the production quality of heterojunction solar cells.

[0035] Preferably, the carrier plate body 1 is made of stainless steel, specifically 316L stainless steel. Based on the inherent properties of 316L stainless steel, the carrier plate body 1 possesses excellent corrosion resistance, resisting the erosion of chemical substances that may occur during the coating process, such as small amounts of active gases in the plasma, ensuring stable performance and a long service life. It also exhibits good high-temperature resistance, able to withstand the high temperatures within the process chamber during PVD coating, preventing deformation or performance degradation at high temperatures, ensuring the stability of the coating process and the consistency of coating quality. Furthermore, it possesses high strength and hardness, able to withstand certain mechanical loads during operations such as handling the silicon wafer 100 without easily deforming, providing a stable support platform for the silicon wafer 100, ensuring accurate positioning of the silicon wafer 100 during the coating process, thereby improving coating precision. Its good thermal conductivity facilitates rapid heat conduction during the coating process, resulting in a more uniform temperature distribution within the chamber, contributing to the uniform deposition of the amorphous silicon thin film and improving battery performance. In addition, the smooth surface of 316L stainless steel is easy to clean, which can effectively reduce the adhesion of particulate contaminants, reduce the impact of impurities on the coating quality, and ensure the high cleanliness requirements of heterojunction battery coating production.

[0036] As another embodiment of this application, this application provides a system for heterojunction PVD coating, including a carrier plate as described above, and a process cavity for providing a vacuum environment, with the carrier plate located within the process cavity; as Figure 2 As shown, the system also includes a base, which has an anode guard plate 3 and a target material 4. The anode guard plate 3 is fixedly connected to the base, and the target material 4 abuts against the base and rotates relative to the base. To avoid short circuits, there is a gap between the anode guard plate 3 and the target material 4. As shown by arrow A in the figure, the aforementioned carrier plate passes through the base along the direction of arrow A. During the passage, the silicon wafer 100 on the carrier plate receives atoms, molecules, ions, and other substances sputtered from the target material 4. These substances are deposited on the surface of the silicon wafer 100 to form a high-quality amorphous silicon thin film, which is a core process step in the manufacturing of heterojunction solar cells and directly affects the photoelectric conversion efficiency and stability of the cell. When the silicon wafer 100 falls and happens to fall between the anode guard plate 3 and the target material 4, i.e. Figure 2As shown, when the baffle 2 passes through this position, it can impact the silicon wafer 100, causing the silicon wafer 100 to fall off, or directly shatter the silicon wafer 100. The shattered silicon wafer 100 can also fall between the anode guard plate 3 and the target material 4. This process not only avoids the target material 4 from becoming conductive due to the accumulation of silicon wafer 100, but also effectively prevents abnormal ignition discharge caused by the residue of silicon wafer 100, thereby ensuring the normal operation of the equipment and production efficiency.

[0037] To ensure that the baffle 2 can effectively impact the silicon wafer 100, in this embodiment, the length of the baffle 2 is greater than or equal to the distance from the base to the surface of the target material 4. The length of the baffle 2 refers to its distance in the direction from the base to the target material 4. That is, when the carrier moves in the direction of arrow A, the baffle 2 must contact the target material 4. This design ensures that the baffle 2 can accurately reach the critical position between the anode guard plate 3 and the target material 4 during the movement of the carrier, promptly handle the fallen silicon wafer 100, avoid potential equipment failures and production interruptions, and also help maintain the cleanliness of the process chamber and reduce the impact of impurities on the coating quality.

[0038] In summary, this utility model discloses a carrier plate and system for heterojunction PVD coating. The carrier plate includes a detachably connected carrier plate body 1 and a baffle 2. The carrier plate body 1 supports the silicon wafer 100 to ensure that the silicon wafer 100 maintains a stable position during the coating process, thereby ensuring the uniformity and quality of the coating. The silicon wafer 100 receives the sputtered coating from the target material 4, which is a key step in the manufacturing of heterojunction cells and directly affects the performance of the cells. The baffle 2 is used to impact the silicon wafer 100 that falls between the anode guard plate 3 and the target material 4, preventing the target material 4 from becoming conductive due to the accumulation of silicon wafer 100, thereby avoiding problems such as abnormal start-up discharge and ensuring the normal operation of the equipment and production efficiency. The carrier plate body 1 and the baffle 2 are not parallel to each other. The silicon wafer bearing surface of the carrier plate body 1 and the silicon wafer limiting surface of the baffle 2 form a spatial angle. The silicon wafer bearing surface and the silicon wafer limiting surface are located in different plane dimensions. That is, the angle between the silicon wafer bearing surface and the silicon wafer limiting surface is not 0° or 180°. Only when the angle between the two is an acute angle, a right angle or an obtuse angle can the baffle 2 play the role of impacting the silicon wafer 100. This design cleverly utilizes the principles of space and mechanics to achieve effective management of the silicon wafer 100 and stable operation of the equipment.

[0039] It should be noted that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the exemplary embodiments according to this application. As used herein, the singular form is intended to include the plural form as well, unless the context clearly indicates otherwise. Furthermore, it should be understood that when the terms "comprising" and / or "including" are used in this specification, they indicate the presence of features, steps, operations, devices, components, and / or combinations thereof.

[0040] For ease of description, directional terms such as "front, back, up, down, left, right," "horizontal, vertical, horizontal," and "top, bottom" generally indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings. These terms are used solely for the purpose of facilitating the description of this application and simplifying the description. Unless otherwise stated, these directional terms do not indicate or imply that the referred mechanism or element must have a specific orientation or be constructed and operated in a specific orientation, and therefore should not be construed as limiting the scope of protection of this application. The directional terms "inner" and "outer" refer to the inner or outer contours relative to the components themselves. For example, if a device in the drawings is inverted, a device described as "above" or "on top of" other devices or structures will subsequently be positioned as "below" or "under" other devices or structures. Thus, the exemplary term "above" can include both "above" and "below." The device may also be positioned in other different ways (rotated 90 degrees or in other orientations), and the spatial relative descriptions used herein are interpreted accordingly.

[0041] Unless otherwise expressly specified and limited, the terms "installation," "connection," "linking," and "fixing," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection, an electrical connection, or a communication connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.

[0042] Unless otherwise expressly specified and limited, "above" or "below" the second feature can include direct contact between the first and second features, or contact between the first and second features through another feature between them. Furthermore, "above," "over," and "on top" of the second feature includes the first feature directly above or diagonally above the second feature, or simply indicates that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature includes the first feature directly above or diagonally above the second feature, or simply indicates that the first feature is at a lower horizontal level than the second feature.

[0043] Unless otherwise specifically stated, the relative arrangement, numerical expressions, and values ​​of the components and steps described in these embodiments do not limit the scope of this application. It should also be understood that, for ease of description, the dimensions of the various parts shown in the drawings are not drawn to actual scale. Techniques, methods, and devices known to those skilled in the art may not be discussed in detail, but where appropriate, such techniques, methods, and devices should be considered part of the specification. In all examples shown and discussed herein, any specific values ​​should be interpreted as merely exemplary and not as limitations. Therefore, other examples of exemplary embodiments may have different values. It should be noted that similar reference numerals and letters in the following drawings denote similar items; therefore, once an item is defined in one drawing, it need not be further discussed in subsequent drawings.

[0044] It should also be noted that the terms "one embodiment," "another embodiment," and "embodiment" used in this specification refer to specific features, structures, or characteristics described in connection with that embodiment, which are included in at least one embodiment described in the general description of this application. The appearance of the same expression in multiple places in the specification does not necessarily refer to the same embodiment. Furthermore, when a specific feature, structure, or characteristic is described in connection with any embodiment, the intention is to suggest that implementing such a feature, structure, or characteristic in conjunction with other embodiments also falls within the scope of this application.

[0045] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0046] It should also be noted that the above are merely preferred embodiments of this application and do not limit the scope of patent protection of this application. Any equivalent structural or procedural changes made using the content of this application’s specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the scope of patent protection of this application.

Claims

1. A carrier plate for heterojunction PVD coating, characterized in that, include: The carrier plate body (1) and the baffle (2) are detachably connected; The carrier plate body (1) and the baffle (2) are arranged in a non-parallel manner. The silicon wafer bearing surface of the carrier plate body (1) and the silicon wafer limiting surface of the baffle (2) form a spatial angle. The silicon wafer bearing surface and the silicon wafer limiting surface are located in different planar dimensions.

2. The carrier plate according to claim 1, characterized in that, The baffle (2) is configured as a flexible material.

3. The carrier plate according to claim 1, characterized in that, The carrier body (1) includes a plurality of first rods (11) arranged along a first direction and a plurality of second rods (12) arranged along a second direction. The projection of any first rod (11) on the silicon wafer bearing surface is perpendicular to the projection of any second rod (12) on the silicon wafer bearing surface. Multiple first rods (11) and multiple second rods (12) form multiple hollow receiving slots (13) for carrying silicon wafers (100).

4. The carrier plate according to any one of claims 1-3, characterized in that, The carrier plate body (1) and the baffle (2) are connected by a wire harness binding connection.

5. The carrier plate according to any one of claims 1-3, characterized in that, The connection between the carrier plate body (1) and the baffle (2) is either a plug-in connection or a tenon-and-mortise connection.

6. The carrier plate according to claim 4, characterized in that, At least one of the carrier plate body (1) and the baffle (2) is provided with a fixing hole (21), and the wire harness passes through the fixing hole (21) for binding and fixing.

7. The carrier plate according to claim 1, characterized in that, The carrier plate body (1) is made of stainless steel.

8. A system for heterojunction PVD coating, characterized in that, The carrier plate as described in any one of claims 1-7 is further comprising a process cavity for providing a vacuum environment, wherein the carrier plate is located within the process cavity.

9. The system according to claim 8, characterized in that, It also includes a base, on which an anode guard plate (3) and a target material (4) are provided. The anode guard plate (3) is fixedly connected to the base, and the target material (4) abuts against the base and rotates relative to the base. There is a gap between the anode guard plate (3) and the target material (4).

10. The system according to claim 9, characterized in that, The length of the baffle (2) is greater than or equal to the distance from the base to the surface of the target (4).

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