MOS chip parallel packaging structure

Abstract

The application provides a MOS chip parallel packaging structure, which comprises a first MOS chip and a second MOS chip. The two MOS chips are packaged back to back, the packaging size of the product is reduced, and the electrical performance of the product is improved.

Description

Technical Field

[0001] This application relates to the field of semiconductor packaging technology, and particularly to a parallel packaging structure for MOS chips. Background Technology

[0002] As the application of MOS power devices in various industries gradually expands, the demand for miniaturized packaging size is increasing while product performance is improving. However, the improvement in product performance is accompanied by an increase in chip area, which cannot meet the product requirements.

[0003] In existing technologies, MOS chip packaging involves spacing each chip and connecting it with pins. This packaging method results in a larger overall product size, making miniaturization impossible. Summary of the Invention

[0004] To address or mitigate the problems in existing technologies, this application provides a parallel packaging structure for MOS chips. This new packaging structure, developed based on wafer-level packaging technology, improves performance while reducing product package size.

[0005] As a preferred embodiment of this application, it includes a first MOS chip and a second MOS chip;

[0006] The first MOS chip and the second chip have a drain on their first and second sides respectively, and the first MOS chip and the second chip have a gate and a source respectively.

[0007] The first side of the first MOS chip and the first side of the second MOS chip are connected through a first conductive layer, and the drains of the first MOS chip and the second MOS chip are led out through the first conductive layer;

[0008] The first MOS chip has a second conductive layer and a third conductive layer on its second surface, and the second MOS chip has a fourth conductive layer and a fifth conductive layer on its second surface.

[0009] The source of the first MOS chip is led out through the second conductive layer, the gate of the second MOS chip is led out through the third conductive layer, the source of the first MOS chip is led out through the fourth conductive layer, and the gate of the second MOS chip is led out through the fifth conductive layer.

[0010] The second conductive layer and the fourth conductive layer are connected by a sixth conductive layer; the third conductive layer and the fifth conductive layer are connected by a seventh conductive layer.

[0011] In a preferred embodiment of this application, the first conductive layer, the second conductive layer, the third conductive layer, the fourth conductive layer, and the fifth conductive layer are metals.

[0012] Both the first electrode lead-out layer and the second electrode lead-out layer are conductive metal spheres.

[0013] Compared with the prior art, the MOS chip packaging structure provided in this application reduces the product packaging size and increases the product electrical performance by packaging two MOS chips back to back. Attached Figure Description

[0014] The accompanying drawings, which are included to provide a further understanding of this application and form part of this application, illustrate exemplary embodiments and are used to explain this application, but do not constitute an undue limitation of this application. Some specific embodiments of this application will be described in detail below with reference to the accompanying drawings in an exemplary and non-limiting manner. The same reference numerals in the drawings designate the same or similar parts or components. Those skilled in the art should understand that these drawings are not necessarily drawn to scale. In the drawings:

[0015] Figure 1 This is a schematic diagram of a parallel packaging structure for a MOS chip provided in this application. Detailed Implementation

[0016] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are merely some, not all, of the embodiments of the present application. All other embodiments obtained by those skilled in the art based on the embodiments of the present application without creative effort should fall within the scope of protection of the present application.

[0017] like Figure 1 As shown, this application provides a parallel packaging structure for MOS chips, including a first MOS chip 1 and a second MOS chip 2;

[0018] The first MOS chip 1 has a drain on its first side and the second chip has a gate and a source on its second side.

[0019] The first surface of the first MOS chip 1 and the first surface of the second MOS chip 2 are connected through the first conductive layer 9, and the drains of the first MOS chip 1 and the second MOS chip 2 are led out through the first conductive layer 9;

[0020] The second surface of the first MOS chip 1 is provided with a second conductive layer 3 and a third conductive layer 4, and the second surface of the second MOS chip 2 is provided with a fourth conductive layer 5 and a fifth conductive layer 6.

[0021] The source of the first MOS chip 1 is led out through the second conductive layer 3, the gate of the second MOS chip 2 is led out through the third conductive layer 4, the source of the first MOS chip 1 is led out through the fourth conductive layer 5, and the gate of the second MOS chip 2 is led out through the fifth conductive layer 6.

[0022] The second conductive layer 3 and the fourth conductive layer 5 are connected by a sixth conductive layer 7; the third conductive layer 4 and the fifth conductive layer 6 are connected by a seventh conductive layer 8.

[0023] In a preferred embodiment of this application, the first conductive layer 9, the second conductive layer 3, the third conductive layer 4, the fourth conductive layer 5, the fifth conductive layer 6, the sixth conductive layer 7, and the seventh conductive layer 8 are metals.

[0024] The parallel packaging structure for a MOS chip provided in this application, due to the adoption of wafer stacking technology, is more compact and robust in its internal structure. While reducing the area occupied by the chip and PCB, it also brings multiple beneficial effects such as cost reduction and performance improvement, and has broad application prospects and market value.

[0025] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A parallel packaging structure for a MOS chip, characterized in that, Including the first MOS chip and the second MOS chip; The first MOS chip and the second chip have a drain on their first and second sides respectively, and the first MOS chip and the second chip have a gate and a source respectively. The first side of the first MOS chip and the first side of the second MOS chip are connected through a first conductive layer, and the drains of the first MOS chip and the second MOS chip are led out through the first conductive layer; The first MOS chip has a second conductive layer and a third conductive layer on its second surface, and the second MOS chip has a fourth conductive layer and a fifth conductive layer on its second surface. The source of the first MOS chip is led out through the second conductive layer, the gate of the second MOS chip is led out through the third conductive layer, the source of the first MOS chip is led out through the fourth conductive layer, and the gate of the second MOS chip is led out through the fifth conductive layer. The second conductive layer and the fourth conductive layer are connected by a sixth conductive layer; the third conductive layer and the fifth conductive layer are connected by a seventh conductive layer.

2. The parallel packaging structure of a MOS chip as described in claim 1, characterized in that, The first conductive layer, the second conductive layer, the third conductive layer, the fourth conductive layer, and the fifth conductive layer are metals.

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