Array substrate and display panel

Abstract

This application discloses an array substrate and a display panel. The array substrate includes an open region and a non-open region located on at least one side of the open region. The array substrate also includes a substrate, a buffer layer, and a polycrystalline silicon thin-film transistor. The buffer layer is disposed on the substrate and includes a first silicon oxide layer and a first silicon nitride layer sequentially stacked on the substrate. The first silicon oxide layer is located in both the non-open region and the open region, and the first silicon nitride layer is located in the non-open region. The polycrystalline silicon thin-film transistor is located in the non-open region and includes a polycrystalline silicon semiconductor layer disposed on the first silicon nitride layer. In the first silicon nitride layer, the number of silicon-hydrogen bonds per cubic centimeter is 1.0 × 10⁻⁶. 21 Up to 1.0×10 23 Within the specified range. This application can improve the transmittance of the array substrate opening region while simultaneously replenishing hydrogen to the polycrystalline silicon semiconductor device in the non-opening region.

Description

Technical Field

[0001] This application relates to the field of display technology, specifically to an array substrate and a display panel. Background Technology

[0002] In related technologies, low-temperature poly-silicon (LTPS) semiconductor devices are commonly used in the fabrication of array substrates. Array substrates include open areas and non-open areas located outside the open areas. The open areas are the main paths for light transmission, affecting the overall screen transmittance. The buffer layer, insulating film layer, and interlayer dielectric layer of the array substrate are typically configured as a stacked structure of silicon oxide / silicon nitride layers.

[0003] However, within the opening region, due to the difference in refractive index between silicon nitride and silicon oxide, some light is reflected at the interface between the silicon oxide and silicon nitride layers, resulting in reduced transmittance in the opening region. If the entire silicon nitride layer in the corresponding film is removed, leaving only the silicon oxide layer, hydrogen replenishment will be impossible in the low-temperature polycrystalline silicon semiconductor device. Conversely, if the entire silicon oxide layer in the corresponding film is removed, leaving only the silicon nitride layer, the transmittance of the array substrate will decrease because the silicon nitride layer has lower transmittance than the silicon oxide layer.

[0004] Therefore, it is necessary to propose a new technical solution to solve the above-mentioned technical problems. Utility Model Content

[0005] The purpose of this application is to provide an array substrate and a display panel that can improve the transmittance of the array substrate in the aperture area while replenishing hydrogen to the polycrystalline silicon semiconductor device in the non-aperture area.

[0006] To solve the above problems, the technical solution of this application is as follows:

[0007] In a first aspect, this application proposes an array substrate, including an opening region and a non-opening region located on at least one side of the opening region, the array substrate comprising:

[0008] Substrate;

[0009] A buffer layer, disposed on the substrate, includes a first silicon oxide layer and a first silicon nitride layer sequentially stacked on the substrate, wherein the first silicon oxide layer is located in the non-opening region and the opening region, and the first silicon nitride layer is located in the non-opening region; and

[0010] A polycrystalline silicon thin-film transistor, located in the non-opening region, includes a polycrystalline silicon semiconductor layer, the polycrystalline silicon semiconductor layer being disposed on the first silicon nitride layer;

[0011] In the first silicon nitride layer, the number of silicon-hydrogen bonds per cubic centimeter is 1.0 × 10⁻⁶. 21 Up to 1.0×10 23 Within the range.

[0012] In one embodiment of this application, the thickness of the first silicon nitride layer is less than or equal to the thickness of the first silicon oxide layer.

[0013] In one embodiment of this application, the thickness of the first silicon nitride layer is in the range of 500 angstroms to 1000 angstroms.

[0014] In one embodiment of this application, the array substrate further includes:

[0015] A gate insulating layer includes a second silicon oxide layer and a second silicon nitride layer. The second silicon oxide layer is located in the non-opening region and the opening region. The second silicon oxide layer is disposed on the buffer layer and covers the polysilicon semiconductor layer. The second silicon nitride layer is located in the non-opening region and is disposed on the side of the second silicon nitride layer away from the polysilicon semiconductor layer.

[0016] The first metal layer includes a gate, which is located in the non-opening region and disposed on the second silicon nitride layer, corresponding to the polysilicon semiconductor layer.

[0017] In the second silicon nitride layer, the number of silicon-hydrogen bonds per cubic centimeter is 1.0 × 10⁻⁶. 21 Up to 1.0×10 23 Within the range.

[0018] In one embodiment of this application, the thickness of the second silicon nitride layer is less than or equal to the thickness of the second silicon oxide layer.

[0019] In one embodiment of this application, the thickness of the second silicon nitride layer is in the range of 250 angstroms to 500 angstroms.

[0020] In one embodiment of this application, the thickness of the second silicon nitride layer is less than or equal to the thickness of the first silicon nitride layer.

[0021] In one embodiment of this application, the array substrate further includes a third silicon oxide layer, which is an interlayer dielectric layer disposed on the second silicon oxide layer and covers the gate and the second silicon nitride layer.

[0022] In one embodiment of this application, the array substrate further includes:

[0023] The second metal layer includes a first electrode, a second electrode, and a third electrode located in the non-opening region and spaced apart on the interlayer dielectric layer, wherein the first electrode and the second electrode are electrically connected to the polycrystalline silicon semiconductor layer, respectively.

[0024] A planarization layer, located in the non-opening region and the opening region, is disposed on the interlayer dielectric layer and covers the second metal layer;

[0025] A first transparent conductive layer is disposed on the planarization layer, a portion of the first transparent conductive layer is located in the opening region, another portion of the first transparent conductive layer is located in the non-opening region, and is electrically connected to the third electrode.

[0026] A passivation layer is located in the non-opening region and the opening region, the passivation layer is disposed on the planarization layer, and covers the first transparent conductive layer; and

[0027] A second transparent conductive layer is located in the opening area. The second transparent conductive layer is disposed on the passivation layer and is electrically connected to the second electrode.

[0028] The polycrystalline silicon semiconductor layer, the gate, the first electrode, and the second electrode form the polycrystalline silicon thin-film transistor.

[0029] Secondly, this application proposes a display panel including an array substrate. The array substrate includes an opening region and a non-opening region located on at least one side of the opening region. The array substrate includes a substrate, a buffer layer, and polycrystalline silicon thin-film transistors. The buffer layer is disposed on the substrate and includes a first silicon oxide layer and a first silicon nitride layer sequentially stacked on the substrate. The first silicon oxide layer is located in the non-opening region and the opening region, and the first silicon nitride layer is located in the non-opening region. The polycrystalline silicon thin-film transistor is located in the non-opening region and includes a polycrystalline silicon semiconductor layer disposed on the first silicon nitride layer. In the first silicon nitride layer, the number of silicon-hydrogen bonds per cubic centimeter is 1.0 × 10⁻⁶. 21 Up to 1.0×10 23 Within the range.

[0030] In this application, the buffer layer comprises a first silicon oxide layer and a first silicon nitride layer stacked together. The first silicon nitride layer is located only in the non-opening region, and the number of silicon-hydrogen bonds per cubic centimeter in the first silicon nitride layer is 1.0 × 10⁻⁶. 21 Up to 1.0×10 23Within this range, the first silicon nitride layer can effectively replenish hydrogen to the polycrystalline silicon semiconductor layer in the non-opening region. The buffer layer located in the opening region only has the first silicon oxide layer, which can avoid some light being reflected at the interface between the two films with different refractive indices due to the stacked films in the opening region, thus improving the transmittance of the opening region. Attached Figure Description

[0031] Figure 1 This is a schematic diagram of one embodiment of an array substrate in related technologies;

[0032] Figure 2 This is a schematic diagram of another embodiment of an array substrate in related technologies;

[0033] Figure 3 This is a plan view of one embodiment of the array substrate of this application;

[0034] Figure 4 This is a schematic diagram of one embodiment of the array substrate of this application;

[0035] Figure 5 This is a schematic diagram of step S1 of the method for fabricating the array substrate of this application;

[0036] Figure 6 This is a schematic diagram of step S2 of the method for fabricating the array substrate of this application;

[0037] Figure 7 This is a schematic diagram of step S3 of the method for fabricating the array substrate of this application;

[0038] Figure 8 This is a schematic diagram of step S4 of the method for fabricating the array substrate of this application;

[0039] Figure 9 This is a schematic diagram of step S5 of the method for fabricating the array substrate of this application;

[0040] Figure 10 This is a schematic diagram of step S6 of the method for fabricating the array substrate of this application;

[0041] Figure 11 This is a schematic diagram of step S7 of the method for fabricating the array substrate of this application;

[0042] Figure 12 This is a schematic diagram of step S8 of the method for fabricating the array substrate of this application;

[0043] Figure 13 This is a schematic diagram of step S9 of the method for fabricating the array substrate of this application;

[0044] Figure 14 This is a schematic diagram of step S10 of the method for fabricating the array substrate of this application. Detailed Implementation

[0045] The terms used in this specification and claims have the meanings that are commonly understood by one of ordinary skill in the art to which this application pertains. The terms used in this specification and claims are for the purpose of facilitating the description and understanding of this application only, and are not intended to limit this application to the narrow interpretation of the specific terms used in the specification and claims.

[0046] Please see Figure 1 In one related technology, in order to achieve hydrogen replenishment of the polycrystalline silicon semiconductor layer 31' in the polycrystalline silicon thin film transistor 30', the buffer layer 20', the insulating film layer 40' and the interlayer dielectric layer 60' are set as a double-layer stacked structure of silicon oxide layer SiOx / silicon nitride layer SiNx.

[0047] However, due to the difference in refractive index between the silicon nitride layer SiNx and the silicon oxide layer SiOx, when light reaches the interface between the silicon oxide layer SiOx and the silicon nitride layer SiNx, some of the light will be reflected at the interface, which weakens the light passing through the array substrate and reduces the transmittance of the opening region.

[0048] Please see Figure 1 A beam of light L1 is incident from the substrate side of the array substrate. When it reaches the buffer layer 20', part of the light S1 is reflected at the interface between silicon oxide and silicon nitride in the buffer layer 20'. The remaining light passes through this interface and reaches the insulating film layer 40', where part of the light S2 is reflected at the interface between silicon oxide and silicon nitride in the insulating film layer 40'. The remaining light passes through this interface and reaches the interlayer dielectric layer 60', where part of the light S3 is reflected at the interface between silicon oxide and silicon nitride in the interlayer dielectric layer 60'. This results in a decrease in the transmittance of the opening region.

[0049] Please see Figure 2 In another related technology, to improve transmittance, the silicon nitride (SiNx) layer in the buffer layer, insulating film layer, and interlayer dielectric layer is removed, leaving only the silicon oxide (SiOx) layer. Because the SiNx layer is removed, it affects hydrogen replenishment in polycrystalline silicon thin-film transistors, thus impacting device performance.

[0050] This application discloses a display panel, which includes an array substrate 100, a liquid crystal layer, and an opposing substrate. The opposing substrate may be a color filter substrate. The display panel can be applied to tablet computers, e-readers, electronic display screens, laptops, mobile phones, augmented reality (AR) / virtual reality (VR) devices, media players, wearable devices, digital cameras, car navigation systems, etc.

[0051] Please see Figure 3 This application proposes an array substrate 100, which includes an opening region AA1 and a non-opening region AA2 located on at least one side of the opening region AA1.

[0052] Optionally, the array substrate 100 includes a pixel region AA and a non-pixel region NA located on at least one side of the pixel region AA. The pixel region AA includes a plurality of arrayed opening regions AA1. The non-opening regions AA2 are located between adjacent opening regions AA1.

[0053] Please see Figure 4 Optionally, the array substrate 100 may also include a substrate 10, a buffer layer 20, and a polysilicon thin-film transistor 30.

[0054] A buffer layer 20 is disposed on the substrate 10. The buffer layer 20 includes a first silicon oxide layer 21 and a first silicon nitride layer 22 sequentially stacked on the substrate 10. The first silicon oxide layer 21 is located in the non-opening region AA2 and the opening region AA1. The first silicon nitride layer 22 is located in the non-opening region AA2.

[0055] The polysilicon thin-film transistor 30 is located in the non-opening region AA2. The polysilicon thin-film transistor 30 includes a polysilicon semiconductor layer 31. The polysilicon semiconductor layer 31 is disposed on the first silicon nitride layer 22.

[0056] In the first silicon nitride layer 22, the number of silicon-hydrogen bonds per cubic centimeter is 1.0 × 10⁻⁶. 21 Up to 1.0×10 23 Within the range.

[0057] In this embodiment, the buffer layer 20 includes a first silicon oxide layer 21 and a first silicon nitride layer 22 stacked together. The first silicon nitride layer 22 is located only in the non-opening region AA2, and the number of silicon-hydrogen bonds per cubic centimeter in the first silicon nitride layer 22 is 1.0 × 10⁻⁶. 21 Up to 1.0×10 23 Within this range, the first silicon nitride layer 22 can effectively replenish hydrogen to the polycrystalline silicon semiconductor layer 31 in the non-opening region AA2. The portion of the buffer layer 20 located in the opening region AA1 is only provided with the first silicon oxide layer 21, which can prevent some light from being reflected at the interface between the two films with different refractive indices due to the stacked two films in the opening region AA1, thereby improving the transmittance of the opening region AA1.

[0058] Optionally, the substrate 10 is a glass substrate 10.

[0059] Optionally, the polycrystalline silicon thin-film transistor 30 is a low-temperature polycrystalline silicon thin-film transistor. The polycrystalline silicon semiconductor layer 31 is a low-temperature polycrystalline silicon semiconductor layer.

[0060] Optionally, in the first silicon nitride layer 22, the number of silicon-hydrogen bonds per cubic centimeter is on the order of 10. 21 and 10 22 Between. In the first silicon nitride layer 22, the number of silicon-hydrogen bonds per cubic centimeter can be 1.0 × 10⁻⁶. 21 1.1×10 21 1.2×10 21 1.3×10 21 1.4×10 21 1.5×10 21 1.6×10 21 1.7×10 21 1.8×10 21 1.9×10 21 2.0×10 21 2.1×10 21 2.2×10 21 2.3×10 21 2.4×10 21 2.5×10 21 2.6×10 21 2.7×10 21 2.8×10 21 2.9×10 21 3.0×10 21 3.1×10 21 3.2×10 21 3.3×10 21 3.4×10 21 3.5×10 21 3.6×10 21 3.7×10 21 3.8×10 21 3.9×10 21 4.0×10 21 4.1×10 21 4.2×10 21 4.3×10 21 4.4×10 21 4.5×10 21 4.6×10 21 4.7×10 21 4.8×10 21 4.9×10 21 5.0×10 21 5.1×10 21 5.2×10 21 5.3×10 21 5.4×10 21 5.5×1021 、5.6×10 21 、5.7×10 21 、5.8×10 21 、5.9×10 21 、6.0×10 21 、6.1×10 21 、6.2×10 21 、6.3×10 21 、6.4×10 21 、6.5×10 21 、6.6×10 21 、6.7×10 21 、6.8×10 21 、6.9×10 21 、7.0×10 21 、7.1×10 21 、7.2×10 21 、7.3×10 21 、7.4×10 21 、7.5×10 21 、7.6×10 21 、7.7×10 21 、7.8×10 21 、7.9×10 21 、8.0×10 21 、8.1×10 21 、8.2×10 21 、8.3×10 21 、8.4×10 21 、8.5×10 21 、8.6×10 21 、8.7×10 21 、8.8×10 21 、8.9×10 21 、9.0×10 21 、9.1×10 21 、9.2×10 21 、9.3×10 21 、9.4×10 21 、9.5×10 21 、9.6×10 21 、9.7×10 21 、9.8×10 21 、9.9×10 21 、1.0×10 22 、1.1×10 22 、1.2×10 22 、1.3×10 22 、1.4×10 22 、1.5×1022 、1.6×10 22 、1.7×10 22 、1.8×10 22 、1.9×10 22 、2.0×10 22 、2.3×10 22 、2.4×10 22 、2.5×10 22 、2.6×10 22 、2.7×10 22 、2.8×10 22 、2.9×10 22 、3.0×10 22 、3.1×10 22 、3.2×10 22 、3.3×10 22 、3.4×10 22 、3.5×10 22 、3.6×10 22 、3.7×10 22 、3.8×10 22 、3.9×10 22 、4.0×10 22 、4.1×10 22 、4.2×10 22 、4.3×10 22 、4.4×10 22 、4.5×10 22 、4.6×10 22 、4.7×10 22 、4.8×10 22 、4.9×10 22 、5.0×10 22 、5.1×10 22 、5.2×10 22 、5.3×10 22 、5.4×10 22 、5.5×10 22 、5.6×10 22 、5.7×10 22 、5.8×10 22 、5.9×10 22 、6.0×10 22 、6.1×10 22 、6.2×10 22 、6.3×10 22 、6.4×10 22 、6.5×10 22 、6.6×10 22 、6.7×1022 6.8×10 22 6.9×10 22 7.0×10 22 7.1×10 22 7.2×10 22 7.3×10 22 7.4×10 22 7.5×10 22 7.6×10 22 7.7×10 22 7.8×10 22 7.9×10 22 8.0×10 22 8.1×10 22 8.2×10 22 8.3×10 22 8.4×10 22 8.5×10 22 8.6×10 22 8.7×10 22 8.8×10 22 8.9×10 22 9.0×10 22 9.1×10 22 9.2×10 22 9.3×10 22 9.4×10 22 9.5×10 22 9.6×10 22 9.7×10 22 9.8×10 22 9.9×10 22 1.0×10 23 As the number of silicon-hydrogen bonds per cubic centimeter in the first silicon nitride layer 22 increases, the effect of the first silicon nitride layer 22 on replenishing hydrogen in the polycrystalline silicon semiconductor layer 31 of the non-opening region AA2 becomes better.

[0061] Optionally, the thickness h1 of the first silicon nitride layer 22 is less than or equal to the thickness h2 of the first silicon oxide layer 21.

[0062] In this embodiment, the thickness h1 of the first silicon nitride layer 22 is relatively small. Because the light transmittance of the silicon nitride layer is lower than that of the silicon oxide layer, a larger thickness of the silicon nitride layer would affect the transmittance of the pixel area AA, since some non-vertically upward-emitting light rays from the non-aperture area AA2 can exit from the aperture area AA1. Therefore, in this embodiment, the thickness h1 of the first silicon nitride layer 22 is set to be smaller than the thickness h2 of the first silicon oxide layer 21, thereby improving the overall transmittance of the pixel area AA.

[0063] Optionally, the thickness h1 of the first silicon nitride layer 22 is in the range of 500 angstroms to 1000 angstroms.

[0064] In this embodiment, when the number of silicon-hydrogen bonds per cubic centimeter is constant, the thicker h1 of the first silicon nitride layer 22, the better the hydrogen replenishment effect on the polycrystalline silicon semiconductor layer 31. The first silicon nitride layer 22 can also prevent impurity ions such as sodium and potassium ions in the glass substrate 10 from diffusing upwards to the polycrystalline silicon semiconductor layer 31. Therefore, the thicker the first silicon nitride layer 22, the better the blocking effect on impurity ions in the glass substrate 10.

[0065] Optionally, the array substrate 100 further includes a light-shielding layer LS. The light-shielding layer LS is disposed on the substrate 10 and covered by a first silicon oxide layer 21. The light-shielding layer LS is used to block light from the backlight side incident on the polysilicon semiconductor layer 31. The material of the light-shielding layer LS can be a metal.

[0066] The thickness h1 of the first silicon nitride layer 22 can be 500 Å, 550 Å, 600 Å, 650 Å, 700 Å, 750 Å, 800 Å, 850 Å, 900 Å, 950 Å, 1000 Å, etc. As the thickness h1 of the first silicon nitride layer 22 increases, the hydrogen replenishment effect on the polycrystalline silicon semiconductor layer 31 is better, and the blocking effect on impurity ions in the glass substrate 10 is also better. As the thickness h1 of the first silicon nitride layer 22 decreases, the thickness of the array substrate 100 can also be relatively reduced, thereby achieving a thinner and lighter display panel design and reducing material and production costs.

[0067] Optionally, the array substrate 100 may further include a gate insulating layer 40 and a first metal layer.

[0068] The gate insulating layer 40 includes a second silicon oxide layer 41 and a second silicon nitride layer 42. The second silicon oxide layer 41 is located in the non-aperture region AA2 and the aperture region AA1. The second silicon oxide layer 41 is disposed on the buffer layer 20 and covers the polysilicon semiconductor layer 31. The second silicon nitride layer 42 is located in the non-aperture region AA2 and is disposed on the side of the second silicon nitride layer 42 away from the polysilicon semiconductor layer 31.

[0069] The first metal layer includes a gate GE. The gate GE is located in the non-opening region AA2 and is disposed on the second silicon nitride layer 42, corresponding to the polysilicon semiconductor layer 31.

[0070] In the second silicon nitride layer 42, the number of silicon-hydrogen bonds per cubic centimeter is 1.0 × 10⁻⁶. 21 Up to 1.0×10 23 Within the range.

[0071] In this embodiment, the gate insulating layer 40 includes a second silicon oxide layer 41 and a second silicon nitride layer 42 stacked together, wherein the second silicon nitride layer 42 is located only in the non-opening region AA2, and the number of silicon-hydrogen bonds per cubic centimeter in the second silicon nitride layer 42 is 1.0 × 10⁻⁶. 21 Up to 1.0×10 23 Within this range, the second silicon nitride layer 42 can effectively replenish hydrogen to the polycrystalline silicon semiconductor layer 31 in the non-opening region AA2, further improving the hydrogen replenishment effect on the polycrystalline silicon semiconductor layer 31. The portion of the gate insulating layer 40 located in the opening region AA1 is only provided with the second silicon oxide layer 41, which can avoid some light being reflected at the interface between the two films with different refractive indices due to the stacked two films in the opening region AA1, further improving the transmittance of the opening region AA1.

[0072] Optionally, in the second silicon nitride layer 42, the order of magnitude of silicon-hydrogen bonds per cubic centimeter is in the range of 10. 21 and 10 22 Between. In the second silicon nitride layer 42, the number of silicon-hydrogen bonds per cubic centimeter can be 1.0 × 10⁻⁶. 21 1.1×10 21 1.2×10 21 1.3×10 21 1.4×10 21 1.5×10 21 1.6×10 21 1.7×10 21 1.8×10 21 1.9×10 21 2.0×10 21 2.1×10 21 2.2×10 21 2.3×10 21 2.4×10 21 2.5×10 21 2.6×10 21 2.7×10 21 2.8×10 21 2.9×10 21 3.0×10 21 3.1×10 21 3.2×10 21 3.3×10 21 3.4×10 21 3.5×10 21 3.6×10 21 3.7×10 21 3.8×10 21 3.9×10 21、4.0×10 21 、4.1×10 21 、4.2×10 21 、4.3×10 21 、4.4×10 21 、4.5×10 21 、4.6×10 21 、4.7×10 21 、4.8×10 21 、4.9×10 21 、5.0×10 21 、5.1×10 21 、5.2×10 21 、5.3×10 21 、5.4×10 21 、5.5×10 21 、5.6×10 21 、5.7×10 21 、5.8×10 21 、5.9×10 21 、6.0×10 21 、6.1×10 21 、6.2×10 21 、6.3×10 21 、6.4×10 21 、6.5×10 21 、6.6×10 21 、6.7×10 21 、6.8×10 21 、6.9×10 21 、7.0×10 21 、7.1×10 21 、7.2×10 21 、7.3×10 21 、7.4×10 21 、7.5×10 21 、7.6×10 21 、7.7×10 21 、7.8×10 21 、7.9×10 21 、8.0×10 21 、8.1×10 21 、8.2×10 21 、8.3×10 21 、8.4×10 21 、8.5×10 21 、8.6×10 21 、8.7×10 21 、8.8×10 21 、8.9×10 21、9.0×10 21 、9.1×10 21 、9.2×10 21 、9.3×10 21 、9.4×10 21 、9.5×10 21 、9.6×10 21 、9.7×10 21 、9.8×10 21 、9.9×10 21 、1.0×10 22 、1.1×10 22 、1.2×10 22 、1.3×10 22 、1.4×10 22 、1.5×10 22 、1.6×10 22 、1.7×10 22 、1.8×10 22 、1.9×10 22 、2.0×10 22 、2.3×10 22 、2.4×10 22 、2.5×10 22 、2.6×10 22 、2.7×10 22 、2.8×10 22 、2.9×10 22 、3.0×10 22 、3.1×10 22 、3.2×10 22 、3.3×10 22 、3.4×10 22 、3.5×10 22 、3.6×10 22 、3.7×10 22 、3.8×10 22 、3.9×10 22 、4.0×10 22 、4.1×10 22 、4.2×10 22 、4.3×10 22 、4.4×10 22 、4.5×10 22 、4.6×10 22 、4.7×10 22 、4.8×10 22 、4.9×10 22 、5.0×10 22 、5.1×10 22、5.2×10 22 、5.3×10 22 、5.4×10 22 、5.5×10 22 、5.6×10 22 、5.7×10 22 、5.8×10 22 、5.9×10 22 、6.0×10 22 、6.1×10 22 、6.2×10 22 、6.3×10 22 、6.4×10 22 、6.5×10 22 、6.6×10 22 、6.7×10 22 、6.8×10 22 、6.9×10 22 、7.0×10 22 、7.1×10 22 、7.2×10 22 、7.3×10 22 、7.4×10 22 、7.5×10 22 、7.6×10 22 、7.7×10 22 、7.8×10 22 、7.9×10 22 、8.0×10 22 、8.1×10 22 、8.2×10 22 、8.3×10 22 、8.4×10 22 、8.5×10 22 、8.6×10 22 、8.7×10 22 、8.8×10 22 、8.9×10 22 、9.0×10 22 、9.1×10 22 、9.2×10 22 、9.3×10 22 、9.4×10 22 、9.5×10 22 、9.6×10 22 、9.7×10 22 、9.8×10 22 、9.9×10 22 、1.0×10 23As the number of silicon-hydrogen bonds per cubic centimeter in the second silicon nitride layer 42 increases, the effect of the second silicon nitride layer 42 on replenishing hydrogen in the polycrystalline silicon semiconductor layer 31 of the non-opening region AA2 becomes better.

[0073] Optionally, the thickness h3 of the second silicon nitride layer 42 is less than or equal to the thickness h4 of the second silicon oxide layer 41.

[0074] In this embodiment, the thickness h3 of the second silicon nitride layer 42 is relatively small. Because the light transmittance of the silicon nitride layer is lower than that of the silicon oxide layer, a larger thickness of the silicon nitride layer would affect the transmittance of the pixel area AA, since some non-vertically upward-emitting light from the non-aperture area AA2 can exit from the aperture area AA1. Therefore, in this embodiment, the thickness h3 of the second silicon nitride layer 42 is set to be smaller than the thickness h4 of the second silicon oxide layer 41, thereby improving the overall transmittance of the pixel area AA.

[0075] Optionally, the thickness h3 of the second silicon nitride layer 42 is in the range of 250 angstroms to 500 angstroms.

[0076] In this embodiment, when the number of silicon-hydrogen bonds per cubic centimeter is constant, the thicker the second silicon nitride layer 42 is, the better the hydrogen replenishment effect on the polycrystalline silicon semiconductor layer 31.

[0077] The thickness h3 of the second silicon nitride layer 42 can be 250 angstroms, 300 angstroms, 350 angstroms, 400 angstroms, 450 angstroms, 500 angstroms, etc. As the thickness h3 of the second silicon nitride layer 42 increases, the hydrogen replenishment effect on the polycrystalline silicon semiconductor layer 31 is better, and the blocking effect on impurity ions in the glass substrate 10 is also better. As the thickness h3 of the second silicon nitride layer 42 decreases, the thickness of the array substrate 100 can also be relatively reduced, thereby achieving a thinner and lighter display panel design and reducing material and production costs.

[0078] Optionally, the thickness h3 of the second silicon nitride layer 42 is less than or equal to the thickness h1 of the first silicon nitride layer 22.

[0079] In this embodiment, the first silicon nitride layer 22 can also prevent impurity ions such as sodium and potassium ions in the glass substrate 10 from diffusing upwards to the polycrystalline silicon semiconductor layer 31. Therefore, the thicker the first silicon nitride layer 22 is, the better the blocking effect on impurity ions in the glass substrate 10.

[0080] Optionally, the array substrate 100 further includes a third silicon oxide layer 60. The third silicon oxide layer 60 is an interlayer dielectric layer, which is disposed on the second silicon oxide layer 41 and covers the gate GE and the second silicon nitride layer 42.

[0081] In this embodiment, the interlayer dielectric layer is formed only by the third silicon oxide layer 60. Compared with the interlayer dielectric layer formed by silicon oxide and silicon nitride layers in related technologies, when light from the opening region AA1 reaches the interface between the interlayer dielectric layer and the second silicon oxide layer 41, very little light is reflected at this interface because the material of the interlayer dielectric layer is also silicon oxide. This embodiment can avoid the reflection of some light at the interface of the two films with different refractive indices due to the stacked two films in the opening region AA1, further improving the transmittance of the opening region AA1.

[0082] Calculations show that when the interlayer dielectric layer is formed using only the third silicon oxide layer 60, the transmittance of the array substrate 100 can be increased by 2.8%.

[0083] Optionally, the array substrate 100 may further include a second metal layer 70, a planarization layer 81, a first transparent conductive layer 91, a passivation layer 82, and a second transparent conductive layer 92.

[0084] The second metal layer 70 includes a first electrode S, a second electrode D, and a third electrode Com located in the non-opening region AA2 and spaced apart on the interlayer dielectric layer. The first electrode S and the second electrode D are electrically connected to the polysilicon semiconductor layer 31, respectively.

[0085] The planarization layer 81 is located in the non-opening region AA2 and the opening region AA1, is disposed on the interlayer dielectric layer, and covers the second metal layer 70.

[0086] A first transparent conductive layer 91 is disposed on the planarization layer 81. A portion of the first transparent conductive layer 91 is located in the opening region AA1. Another portion of the first transparent conductive layer 91 is located in the non-opening region AA2 and is electrically connected to the third electrode Com.

[0087] The passivation layer 82 is located in the non-opening region AA2 and the opening region AA1. The passivation layer 82 is disposed on the planarization layer 81 and covers the first transparent conductive layer 91.

[0088] The second transparent conductive layer 92 is located in the opening region AA1. The second transparent conductive layer 92 is disposed on the passivation layer 82 and is electrically connected to the second electrode D.

[0089] The polycrystalline silicon semiconductor layer 31, the gate GE, the first electrode S, and the second electrode D form a polycrystalline silicon thin film transistor 30.

[0090] This application also proposes a method for fabricating an array substrate 100, comprising the following steps:

[0091] Please see Figure 5 Step S1: A light-shielding metal layer is formed on the substrate 10. The light-shielding metal is patterned by processes such as photoresist deposition, exposure, development, and etching to form the light-shielding layer LS.

[0092] Please see Figure 6 Step S2: Deposit a first silicon oxide layer 21, a first silicon nitride layer 22, and a polysilicon semiconductor layer 31. The first silicon oxide layer 21 and the first silicon nitride layer 22 form a buffer layer 20. The polysilicon semiconductor layer 31 is crystallized, and the channel pattern of the polysilicon semiconductor layer 31 is obtained by photoresist deposition, exposure, development, and etching, and the channel size is defined. While obtaining the channel pattern of the polysilicon semiconductor layer 31, the portion of the first silicon nitride layer 22 of the buffer layer 20 located in the opening region AA1 is removed by over-etching.

[0093] Please see Figure 7 Step S3: Deposit a second silicon oxide layer 41 and a second silicon nitride layer 42, the second silicon oxide layer 41 and the second silicon nitride layer 42 forming a gate insulating layer 40.

[0094] Please see Figure 8 Step S4: Deposit a first metal layer and pattern it to form the gate GE. During the patterning process, the area of ​​the second silicon nitride layer 42 of the gate insulating layer 40 not covered by the gate GE is removed by over-etching, leaving only the second silicon nitride layer 42 below the gate GE. The gate GE is located in the non-aperture region AA2; therefore, the second silicon nitride layer 42 is also located only in the non-aperture region AA2.

[0095] Please see Figure 9 Step S5: Deposit an interlayer insulating layer, which consists of only a single layer of third silicon oxide 60.

[0096] Please see Figure 10 Step S6: A first via and a second via are formed in the interlayer insulating layer, exposing a portion of the polysilicon semiconductor layer 31, respectively. A second metal layer 70 is deposited, and the second metal layer 70 is patterned to form a first electrode S and a second electrode D. A portion of the first electrode S is located within the first via and is electrically connected to the polysilicon semiconductor layer 31. A portion of the second electrode D is located within the second via and is electrically connected to the polysilicon semiconductor layer 31. The second metal layer 70 located in the opening region AA1 is removed.

[0097] Please see Figure 11 Step S7: Deposit planarization layer 81, and form a third via in planarization layer 81. The third via exposes the second electrode D.

[0098] Please see Figure 12 Step S8: Deposit the first transparent conductive layer 91 and pattern the first transparent conductive layer 91.

[0099] Please see Figure 13Step S9: Deposit passivation layer 82, and form a fourth via in passivation layer 82, exposing the second electrode D.

[0100] Please see Figure 14 Step S10: Deposit a second transparent conductive layer 92 and pattern the second transparent conductive layer 92. The second transparent conductive layer 92 passes through the fourth via and is electrically connected to the second electrode D.

[0101] In the fabrication method of the array substrate 100 of this application, by performing an over-etching process on the silicon nitride layer, the number of photomasks can be reduced, thereby lowering production costs.

[0102] The specific embodiments of this application have been described in detail above. The embodiments disclosed above are merely preferred embodiments of this application. Those skilled in the art can make many modifications and improvements without departing from the concept of this application. All such modifications and improvements fall within the scope of protection defined by the claims of this application.

Claims

1. An array substrate, comprising an opening region and a non-opening region located on at least one side of the opening region, characterized in that, The array substrate includes: Substrate; A buffer layer, disposed on the substrate, includes a first silicon oxide layer and a first silicon nitride layer sequentially stacked on the substrate, wherein the first silicon oxide layer is located in the non-opening region and the opening region, and the first silicon nitride layer is located in the non-opening region; and A polycrystalline silicon thin-film transistor, located in the non-opening region, includes a polycrystalline silicon semiconductor layer, the polycrystalline silicon semiconductor layer being disposed on the first silicon nitride layer; In the first silicon nitride layer, the number of silicon-hydrogen bonds per cubic centimeter is 1.0 × 10⁻⁶. 21 Up to 1.0×10 23 Within the range.

2. The array substrate as described in claim 1, characterized in that, The thickness of the first silicon nitride layer is less than or equal to the thickness of the first silicon oxide layer.

3. The array substrate as described in claim 1, characterized in that, The thickness of the first silicon nitride layer is in the range of 500 angstroms to 1000 angstroms.

4. The array substrate as described in any one of claims 1-3, characterized in that, The array substrate further includes: A gate insulating layer includes a second silicon oxide layer and a second silicon nitride layer. The second silicon oxide layer is located in the non-opening region and the opening region. The second silicon oxide layer is disposed on the buffer layer and covers the polysilicon semiconductor layer. The second silicon nitride layer is located in the non-opening region and is disposed on the side of the second silicon nitride layer away from the polysilicon semiconductor layer. The first metal layer includes a gate, which is located in the non-opening region and disposed on the second silicon nitride layer, corresponding to the polysilicon semiconductor layer. In the second silicon nitride layer, the number of silicon-hydrogen bonds per cubic centimeter is 1.0 × 10⁻⁶. 21 Up to 1.0×10 23 Within the range.

5. The array substrate as described in claim 4, characterized in that, The thickness of the second silicon nitride layer is less than or equal to the thickness of the second silicon oxide layer.

6. The array substrate as described in claim 4, characterized in that, The thickness of the second silicon nitride layer is in the range of 250 angstroms to 500 angstroms.

7. The array substrate as described in claim 4, characterized in that, The thickness of the second silicon nitride layer is less than or equal to the thickness of the first silicon nitride layer.

8. The array substrate as described in claim 4, characterized in that, The array substrate further includes a third silicon oxide layer, which is an interlayer dielectric layer disposed on the second silicon oxide layer and covers the gate and the second silicon nitride layer.

9. The array substrate as described in claim 8, characterized in that, The array substrate further includes: The second metal layer includes a first electrode, a second electrode, and a third electrode located in the non-opening region and spaced apart on the interlayer dielectric layer, wherein the first electrode and the second electrode are electrically connected to the polycrystalline silicon semiconductor layer, respectively. A planarization layer, located in the non-opening region and the opening region, is disposed on the interlayer dielectric layer and covers the second metal layer; A first transparent conductive layer is disposed on the planarization layer, a portion of the first transparent conductive layer is located in the opening region, another portion of the first transparent conductive layer is located in the non-opening region, and is electrically connected to the third electrode. A passivation layer is located in the non-opening region and the opening region, the passivation layer is disposed on the planarization layer, and covers the first transparent conductive layer; and A second transparent conductive layer is located in the opening area. The second transparent conductive layer is disposed on the passivation layer and is electrically connected to the second electrode. The polycrystalline silicon semiconductor layer, the gate, the first electrode, and the second electrode form the polycrystalline silicon thin-film transistor.

10. A display panel, characterized in that, Includes the array substrate as described in any one of claims 1-9.

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