A high-integration differential absolute value encoder signal acquisition module
By using a highly integrated differential absolute encoder signal acquisition module, and employing technologies such as terminating resistors, clamping protection circuits, and filtering circuits, the number of isolation chips is reduced, achieving both signal stability and miniaturization.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- NANJING SHIDIAN ELECTRONIC TECH CO LTD
- Filing Date
- 2025-06-12
- Publication Date
- 2026-06-12
AI Technical Summary
Existing encoder signal acquisition modules require multiple isolation chips, resulting in a large board space requirement and hindering module miniaturization.
A highly integrated differential absolute encoder signal acquisition module is adopted. Signal stability is enhanced by setting terminating resistors, clamping protection circuits, filtering circuits and level stabilization circuits. An isolated transceiver circuit is used as a signal transmission medium to reduce the number of isolation chips.
It achieves efficient signal acquisition, reduces board space, solves the problem of large space occupation of encoder signal acquisition module, and promotes module miniaturization.
Smart Images
Figure CN224353842U_ABST
Abstract
Description
Technical Field
[0001] This utility model relates to the field of signal processing technology, and in particular to a highly integrated differential absolute encoder signal acquisition module. Background Technology
[0002] In the field of motion control, various types of motors are used, and various encoders are required to locate the motor's operating status and position to obtain real-time position. The encoder data is usually transmitted to the controller through a differential signal acquisition module.
[0003] To prevent encoder overvoltage or other unexpected operations from burning out the controller and causing the entire control system to fail, isolation circuits are typically incorporated into the differential signal acquisition module. However, existing isolation circuits require multiple isolation chips, occupying a significant amount of board space and hindering module miniaturization. Figure 1 The acquisition module shown acquires the encoder's data signal and clock signal through two differential lines. The two differential lines are connected to two first-level isolation chips, which then transmit the signals to a second-level isolation chip. The second-level isolation chip then transmits the signals to the controller. For the data acquisition of one encoder, three isolation chips are required. Utility Model Content
[0004] The purpose of this application is to provide a highly integrated differential absolute encoder signal acquisition module to solve the technical problem that in the prior art, encoder signal acquisition modules require multiple isolation chips to acquire data from one encoder, resulting in a large board space occupation and hindering module miniaturization.
[0005] To achieve the above objectives, the embodiments of this application adopt the following technical solutions:
[0006] A highly integrated differential absolute encoder signal acquisition module includes an isolated transceiver circuit, an FPGA controller, a first differential signal transmission circuit, and a second differential signal transmission circuit. The first differential signal transmission circuit is used to transmit data signals, and the second differential signal transmission circuit is used to transmit clock signals.
[0007] Both the first differential signal transmission circuit and the second differential signal transmission circuit include differential lines, terminating resistors, clamping protection circuits, filtering circuits, and level stabilization circuits.
[0008] One end of the differential line is connected to an external encoder, and the other end is connected to the isolation transceiver circuit. The terminating resistor, clamping protection circuit, filtering circuit and level stabilizing circuit are all connected to the differential line and are arranged sequentially from the external encoder to the isolation transceiver circuit.
[0009] The isolated transceiver circuit is connected to the FPGA controller.
[0010] In a highly integrated differential absolute encoder signal acquisition module described in this application embodiment, the differential line includes a differential positive line and a differential negative line. The two ends of the terminating resistor are respectively connected to the differential positive line and the differential negative line. The clamping protection circuit, the filtering circuit, and the level stabilizing circuit are all connected to the differential positive line and the differential negative line.
[0011] In a highly integrated differential absolute encoder signal acquisition module described in this application embodiment, the clamping protection circuit includes a first transient voltage suppression diode and a second transient voltage suppression diode;
[0012] The first terminal of the first transient voltage suppressor diode is connected to the differential positive line, the first terminal of the second transient voltage suppressor diode is connected to the differential negative line, and the second terminals of both the first and second transient voltage suppressor diodes are grounded.
[0013] In a highly integrated differential absolute encoder signal acquisition module described in this application embodiment, the filtering circuit includes a first magnetic bead and a second magnetic bead, wherein the first magnetic bead is connected in series on the differential positive phase line and the second magnetic bead is connected in series on the differential inverting phase line.
[0014] In the highly integrated differential absolute encoder signal acquisition module described in this application embodiment, the filtering circuit further includes a first filtering capacitor and a second filtering capacitor;
[0015] The first terminal of the first filter capacitor is connected to the differential positive line, the first terminal of the second filter capacitor is connected to the differential negative line, and the second terminals of both the first and second filter capacitors are grounded.
[0016] In a highly integrated differential absolute encoder signal acquisition module described in this application embodiment, the level stabilization circuit includes a pull-up resistor and a pull-down resistor;
[0017] One end of the pull-up resistor is connected to the differential positive line, and the other end is connected to the +5V operating voltage. One end of the pull-down resistor is connected to the differential negative line, and the other end is grounded.
[0018] In a highly integrated differential absolute encoder signal acquisition module described in this application embodiment, the isolation transceiver circuit includes an isolation transceiver and a clamping filter capacitor;
[0019] The A pin of the isolated transceiver is connected to the differential positive line of the first differential signal transmission circuit, the B pin is connected to the differential inverting line of the first differential signal transmission circuit, the Z pin is connected to the differential inverting line of the second differential signal transmission circuit, the Y pin is connected to the differential positive line of the second differential signal transmission circuit, the DI pin is connected to one end of the clamping filter capacitor, the other end of the clamping filter capacitor is grounded, the VDDA pin is connected to a +3.3V operating voltage, the VDDB pin is connected to a +5V operating voltage, and the RO pin, RE# pin, DE pin, and DI pin are all connected to the FPGA controller.
[0020] In a highly integrated differential absolute encoder signal acquisition module described in this application embodiment, both the VDDA pin and VDDB pin of the isolated transceiver are connected to an input filter capacitor, and the other end of the input filter capacitor is grounded.
[0021] In the highly integrated differential absolute encoder signal acquisition module described in this application embodiment, the isolation transceiver is model CA-IS3086WX.
[0022] Compared with the prior art, the embodiments of this application have the following beneficial effects:
[0023] As can be seen from the above technical solutions, the highly integrated differential absolute encoder signal acquisition module provided in this application reduces the impedance between differential lines by setting a terminating resistor to enhance signal stability, provides overvoltage protection for the subsequent circuit by setting a clamping protection circuit, improves signal quality and stability by setting a filtering circuit, further improves signal stability and prevents signal jitter by setting a level stabilization circuit, and provides electrical isolation by setting an isolation transceiver circuit between the front-end circuit and the back-end controller as a signal transmission intermediary. Under the premise of efficient signal acquisition, only one isolation chip is used, which greatly reduces the board space occupied by the acquisition module. This solves the technical problem in the prior art that the encoder signal acquisition module needs to use multiple isolation chips to acquire the data of one encoder, resulting in a large board space occupied by the encoder signal acquisition module, which is not conducive to the miniaturization of the module. Attached Figure Description
[0024] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. The drawings are not intended to be drawn to scale, and for clarity, not every component will be labeled in each drawing. The drawings described below are merely some embodiments of this application. Those skilled in the art can obtain other drawings based on these drawings without creative effort. Wherein:
[0025] Figure 1 This is a schematic diagram of the structure of an encoder signal acquisition module in the prior art.
[0026] Figure 2 This is a structural schematic diagram of an embodiment of this application. Detailed Implementation
[0027] Because existing encoder signal acquisition modules require multiple isolation chips to acquire data from a single encoder, they occupy a large amount of board space and are not conducive to module miniaturization.
[0028] In view of this, this application provides a highly integrated differential absolute encoder signal acquisition module. The concept is to enhance signal stability by setting a terminating resistor to reduce the impedance between differential lines, provide overvoltage protection for subsequent circuits by setting a clamping protection circuit, improve signal quality and stability by setting a filtering circuit, further improve signal stability and prevent signal jitter by setting a level stabilization circuit, and use an isolated transceiver circuit between the front-end circuit and the back-end controller as a signal transmission intermediary to provide electrical isolation. This achieves efficient signal acquisition while using only one isolation chip, greatly reducing the board space occupied by the acquisition module. It solves the technical problem in the prior art where encoder signal acquisition modules require multiple isolation chips to acquire data from a single encoder, resulting in a large board space occupied by the encoder signal acquisition module and hindering module miniaturization.
[0029] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.
[0030] In the description of this application, it should be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," and "counterclockwise," etc., indicating orientation or positional relationships based on the orientation or positional relationships shown in the accompanying drawings, are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, features defined with "first" and "second" may explicitly or implicitly include one or more of the stated features. In the description of this application, "a plurality of" means two or more, unless otherwise explicitly specified.
[0031] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection, an electrical connection, or a connection that allows communication between them; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication between two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.
[0032] In this application, unless otherwise expressly specified and limited, "above" or "below" the second feature can include direct contact between the first and second features, or contact between the first and second features through another feature between them. Furthermore, "above," "over," and "on top" of the second feature includes the first feature being directly above or diagonally above the second feature, or simply indicates that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature includes the first feature being directly below or diagonally below the second feature, or simply indicates that the first feature is at a lower horizontal level than the second feature.
[0033] The following disclosure provides many different embodiments or examples for implementing different structures of this application. To simplify the disclosure, specific examples of components and arrangements are described below. Of course, these are merely examples and are not intended to limit the scope of this application. Furthermore, reference numerals and / or letters may be repeated in different examples; such repetition is for simplification and clarity and does not in itself indicate a relationship between the various embodiments and / or arrangements discussed. In addition, various specific examples of processes and materials are provided in this application, but those skilled in the art will recognize the application of other processes and / or the use of other materials.
[0034] This application provides a highly integrated absolute encoder signal acquisition module, such as... Figure 2 As shown, a highly integrated absolute encoder signal acquisition module includes an isolated transceiver circuit, a first differential signal transmission circuit 1, and a second differential signal transmission circuit 2. The first differential signal transmission circuit 1 is used to transmit data signals, and the second differential signal transmission circuit 2 is used to transmit clock signals.
[0035] Both the first differential signal transmission circuit 1 and the second differential signal transmission circuit 2 include a differential line, a terminating resistor, a clamping protection circuit, a filtering circuit, and a level stabilization circuit. One end of the differential line is connected to an external encoder, and the other end is connected to the isolation transceiver circuit.
[0036] Specifically, the differential lines include differential positive phase lines and differential negative phase lines.
[0037] The terminating resistor R1, clamping protection circuit, filtering circuit, and level stabilizing circuit are all connected to the differential line and are arranged sequentially from the external encoder to the isolated transceiver circuit. The isolated transceiver circuit is connected to the FPGA controller.
[0038] Specifically, the two ends of the terminating resistor R1 are connected to the differential positive line and the differential negative line respectively, and the clamping protection circuit, the filtering circuit and the level stabilizing circuit are all connected to the differential positive line and the differential negative line.
[0039] Preferably, the terminating resistor R1 has a resistance of 120Ω, and it is connected to both the external encoder and the clamping protection circuit.
[0040] In some embodiments, the clamping protection circuit includes a first transient voltage suppression diode TV1 and a second transient voltage suppression diode TV2. The first terminal of the first transient voltage suppression diode TV1 is connected to the differential positive line, and the first terminal of the second transient voltage suppression diode TV2 is connected to the differential anti-phase line. The second terminals of both the first transient voltage suppression diode TV1 and the second transient voltage suppression diode TV2 are grounded.
[0041] The first transient voltage suppression diode TV1 and the second transient voltage suppression diode TV2 are both model SM712.TCT.
[0042] In some embodiments, the filter circuit includes a first magnetic bead L1 and a second magnetic bead L2, wherein the first magnetic bead L1 is connected in series on the differential positive line and the second magnetic bead L2 is connected in series on the differential inverting line.
[0043] The impedance of the first magnetic bead L1 and the second magnetic bead L2 is 220Ω±25%.
[0044] In some embodiments, the filtering circuit further includes a first filtering capacitor C1 and a second filtering capacitor C2. The first terminal of the first filtering capacitor C1 is connected to the differential positive line, and the first terminal of the second filtering capacitor C2 is connected to the differential anti-phase line. The second terminals of the first filtering capacitor C1 and the second filtering capacitor C2 are both grounded.
[0045] The values of the first filter capacitor C1 and the second filter capacitor C2 are both 100pF and 50V.
[0046] In some embodiments, the level stabilization circuit includes a pull-up resistor R2 and a pull-down resistor R3. One end of the pull-up resistor R2 is connected to the differential positive line, and the other end is connected to a +5V operating voltage. One end of the pull-down resistor R3 is connected to the differential anti-phase line, and the other end is grounded.
[0047] The values of the pull-up resistor R2 and the pull-down resistor R3 are both 4.7kΩ and 1%, respectively. 4.7kΩ and 1% indicate that the resistance is 4.7kΩ, the accuracy is 1%, and there is a deviation of 1%.
[0048] In some embodiments, the isolated transceiver circuit includes an isolated transceiver U1 and a clamping filter capacitor C3. The A pin of the isolated transceiver U1 is connected to the differential positive line of the first differential signal transmission circuit 1, the B pin of the isolated transceiver U1 is connected to the differential inverting line of the first differential signal transmission circuit 1, the Z pin of the isolated transceiver U1 is connected to the differential inverting line of the second differential signal transmission circuit 2, the Y pin of the isolated transceiver U1 is connected to the differential positive line of the second differential signal transmission circuit 2, the DI pin of the isolated transceiver U1 is connected to one end of the clamping filter capacitor C3, and the other end of the clamping filter capacitor C3 is grounded. The VDDA pin of the isolated transceiver U1 is connected to a +3.3V operating voltage, the VDDB pin of the isolated transceiver U1 is connected to a +5V operating voltage, and the RO pin, RE# pin, DE pin, and the DI pin are all connected to the FPGA controller.
[0049] The clamping filter capacitor C3 clamps the signal of the DI pin of the isolated transceiver U1 to a low level (0V), with a value of 100pF and 50V. Preferably, both the VDDA and VDDB pins of the isolated transceiver U1 are connected to an input filter capacitor C4, the other end of which is grounded to optimize the input voltage. The input filter capacitor C4 is a surface-mount capacitor with a value of 100nF and 50V. The isolated transceiver U1 is model CA-IS3086WX. It should be noted that both the GNDA and GNDB pins of the isolated transceiver U1 are grounded. Briefly describe the working process of this application, the FPGA control... When the controller receives an instruction to send a fixed frequency and number of pulse signals to the external encoder, the FPGA controller pulls the DE pin of the isolated transceiver U1 high (high level 1). At this time, the Y and Z pins of the isolated transceiver U1 output pulse signals to the external encoder. The data signal of the external encoder, in Gray code or binary code form, returns to the A and B pins of the isolated transceiver U1 through the first differential signal transmission circuit 1. The FPGA controller pulls the RE# level of the isolated transceiver U1 low (low level 0). After decoding, the isolated transceiver U1 reports to the FPGA controller through the RO pin.
[0050] In summary, the highly integrated differential absolute encoder signal acquisition module provided in this application reduces the impedance between differential lines by setting a terminating resistor to enhance signal stability, provides overvoltage protection for subsequent circuits by setting a clamping protection circuit, improves signal quality and stability by setting a filtering circuit, further enhances signal stability and prevents signal jitter by setting a level stabilization circuit, and provides electrical isolation by setting an isolation transceiver circuit between the front-end circuit and the back-end controller as a signal transmission intermediary. This achieves efficient signal acquisition while using only one isolation chip, greatly reducing the board space occupied by the acquisition module. It solves the technical problem in the prior art where encoder signal acquisition modules require multiple isolation chips to acquire data from a single encoder, resulting in a large board space occupied by the encoder signal acquisition module and hindering module miniaturization.
[0051] The above provides a detailed description of a highly integrated differential absolute encoder signal acquisition module and its fabrication method provided in the embodiments of this application. Specific examples have been used to illustrate the principles and implementation methods of this application. The descriptions of the above embodiments are only for the purpose of helping to understand the technical solutions and core ideas of this application. Those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. These modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.
Claims
1. A highly integrated differential absolute encoder signal acquisition module, characterized in that, It includes an isolated transceiver circuit, a first differential signal transmission circuit, and a second differential signal transmission circuit. The first differential signal transmission circuit is used to transmit data signals, and the second differential signal transmission circuit is used to transmit clock signals. Both the first differential signal transmission circuit and the second differential signal transmission circuit include differential lines, terminating resistors, clamping protection circuits, filtering circuits, and level stabilization circuits. One end of the differential line is connected to an external encoder, and the other end is connected to the isolation transceiver circuit. The terminating resistor, clamping protection circuit, filtering circuit and level stabilizing circuit are all connected to the differential line and are arranged sequentially from the external encoder to the isolation transceiver circuit. The isolated transceiver circuit is connected to the FPGA controller.
2. The highly integrated differential absolute encoder signal acquisition module as described in claim 1, characterized in that, The differential line includes a differential positive line and a differential negative line. The two ends of the terminating resistor are respectively connected to the differential positive line and the differential negative line. The clamping protection circuit, the filtering circuit, and the level stabilizing circuit are all connected to the differential positive line and the differential negative line.
3. The highly integrated differential absolute encoder signal acquisition module as described in claim 2, characterized in that, The clamping protection circuit includes a first transient voltage suppression diode and a second transient voltage suppression diode; The first terminal of the first transient voltage suppressor diode is connected to the differential positive line, the first terminal of the second transient voltage suppressor diode is connected to the differential negative line, and the second terminals of both the first and second transient voltage suppressor diodes are grounded.
4. The highly integrated differential absolute encoder signal acquisition module as described in claim 2, characterized in that, The filter circuit includes a first ferrite bead and a second ferrite bead, wherein the first ferrite bead is connected in series on the differential positive line and the second ferrite bead is connected in series on the differential inverting line.
5. The highly integrated differential absolute encoder signal acquisition module as described in claim 4, characterized in that, The filtering circuit also includes a first filtering capacitor and a second filtering capacitor. The first terminal of the first filter capacitor is connected to the differential positive line, the first terminal of the second filter capacitor is connected to the differential negative line, and the second terminals of both the first and second filter capacitors are grounded.
6. The highly integrated differential absolute encoder signal acquisition module as described in claim 2, characterized in that, The level stabilization circuit includes pull-up resistors and pull-down resistors; One end of the pull-up resistor is connected to the differential positive line, and the other end is connected to the +5V operating voltage. One end of the pull-down resistor is connected to the differential negative line, and the other end is grounded.
7. The highly integrated differential absolute encoder signal acquisition module as described in claim 2, characterized in that, The isolated transceiver circuit includes an isolated transceiver and a clamping filter capacitor; The A pin of the isolated transceiver is connected to the differential positive line of the first differential signal transmission circuit, the B pin is connected to the differential inverting line of the first differential signal transmission circuit, the Z pin is connected to the differential inverting line of the second differential signal transmission circuit, the Y pin is connected to the differential positive line of the second differential signal transmission circuit, the DI pin is connected to one end of the clamping filter capacitor, the other end of the clamping filter capacitor is grounded, the VDDA pin is connected to a +3.3V operating voltage, the VDDB pin is connected to a +5V operating voltage, and the RO pin, RE# pin, DE pin, and DI pin are all connected to the FPGA controller.
8. The highly integrated differential absolute encoder signal acquisition module as described in claim 7, characterized in that, The VDDA and VDDB pins of the isolated transceiver are both connected to an input filter capacitor, and the other end of the input filter capacitor is grounded.
9. The highly integrated differential absolute encoder signal acquisition module as described in claim 7, characterized in that, The isolation transceiver is model CA-IS3086WX.