An output driver integrated circuit and driving chip

Abstract

The utility model discloses an output drive integrated circuit and drive chip, include: interface circuit, the shift register of multiple groups is connected in series and is composed of shift circuit, the latch circuit that multiple groups of latch are connected in parallel are composed of, the decoding circuit that multiple groups of decoding unit are composed of, and every decoding unit will every two latch's output convert into a group level control signal, and, level conversion output circuit is correspondingly arranged with multiple groups of decoding unit respectively, receives the level control signal of every decoding unit output, to produce every output state of main controller signal correspondence, and every output is one of first voltage Vh, second voltage Vm, zero voltage or high resistance state. The utility model does not need to increase other circuit components additionally, has simplified the circuit structure, reduced production and maintenance cost, improved product reliability.

Description

Technical Field

[0001] This utility model relates to the field of integrated circuit technology, and in particular to an output driver integrated circuit and driver chip. Background Technology

[0002] The statements in this section are merely background information related to this utility model and do not necessarily constitute prior art.

[0003] A voltage driver chip can be used to drive the required voltage output. In the field of liquid crystal writing, a voltage driver chip can be used to drive the partial erasure voltage output. For example, a VFD driver chip or an STN liquid crystal driver chip can be used to provide the required voltage to different conductive areas of the liquid crystal writing device to achieve partial erasure.

[0004] In the existing liquid crystal writing device partial erasure control method, there is a situation where it is necessary to control the driving output corresponding to the conductive area to be in a high-impedance state. The so-called high-impedance state (Hiz) refers to controlling these conductive areas and their corresponding driving circuits to be in an 'open circuit' state, that is, physically connected but without current input or current output.

[0005] However, the aforementioned voltage driving chips can often only directly output two or three set voltages. For example, VFD driving chips can only directly output zero voltage or another non-zero voltage, requiring the cooperation of components such as optocouplers and isolation transformers to output the voltage required for partial erasure, and cannot directly output a high-impedance state. STN liquid crystal driving chips can also only directly output two or three different voltages and cannot directly output a high-impedance state. In addition, even if there are multi-voltage input analog switches with high-impedance output, they cannot be used in liquid crystal writing devices with high erasure voltages because they do not support input voltages higher than 20 volts.

[0006] Therefore, the existing voltage-driven chips commonly used for partial erasure cannot directly output a high-impedance state. They need to use control switches to block the current output in order to achieve a high-impedance output, which leads to complex circuit structure, increased production costs, and a corresponding increase in product failure rate. Utility Model Content

[0007] To address the aforementioned issues, this invention proposes an output driver integrated circuit and driver chip capable of driving the output to a set high voltage (first voltage Vh), intermediate voltage (second voltage Vm), high impedance state, and zero voltage, which can be directly used for partial erasure control of liquid crystal writing devices.

[0008] In some implementations, the following technical solutions are adopted:

[0009] An output driver integrated circuit, comprising:

[0010] Interface circuitry for inputting signals from an external main controller, logic power signals, and drive power signals;

[0011] A shift circuit consisting of multiple sets of shift registers connected in series converts the serial signal input to the main controller of the interface circuit into a parallel output.

[0012] A latching circuit consisting of multiple sets of latches connected in parallel, wherein the number of latches corresponds to the number of shift registers, so as to latch each output of the shift circuit;

[0013] A decoding circuit composed of multiple sets of decoding units, each set of decoding units converts the output of every two latches into a set of level control signals;

[0014] Additionally, a level conversion output circuit is provided corresponding to multiple groups of decoding units, which receives the level control signal output by each group of decoding units to generate each output state corresponding to the main controller signal. Each output is one of the following: a first voltage Vh, a second voltage Vm, zero voltage, or a high impedance state.

[0015] Wherein, the first voltage Vh and the second voltage Vm satisfy:

[0016] The first voltage Vh is greater than the second voltage Vm; and the voltage range of the first voltage Vh and the second voltage Vm is between [5, 120V].

[0017] As a further embodiment, the interface circuit includes: a latch input pin LAT for inputting latch signals, a shift register clock input pin CLK for inputting clock signals, a shift register serial data input pin A for inputting serial data, an output pin B, a first drive power input pin VH and a second drive power input pin VM for inputting drive power, a logic power input pin VDD for inputting logic power, and an analog ground pin PGND and a logic ground pin LGND.

[0018] As a further embodiment, in the shift circuit, the data output terminal of the preceding shift register is connected to the data input terminal of the following shift register; at the same time, the data output terminal of each shift register is also connected to the data input terminal of the corresponding latch; the data input terminal of the first shift register is connected to the serial data input pin A of the shift register.

[0019] As a further embodiment, in the latch circuit, the data input terminal of each latch is connected to the data output terminal of the corresponding shift register, and the latch signal input terminal of each latch is connected to the latch input pin LAT; the data output terminals of two adjacent latches are connected to a corresponding decoding unit.

[0020] As a further embodiment, each decoding unit includes: in two adjacent latches, the data output terminal of the first latch is connected to a first NOT gate, and the data output terminal of the second latch is connected to a second NOT gate; the output terminals of the first NOT gate and the second NOT gate are respectively connected to the two input terminals of a first AND gate; the data output terminals of the first latch and the second latch are respectively connected to the two input terminals of a third AND gate; the output terminals of the first NOT gate and the second latch are respectively connected to the two input terminals of a second AND gate; and the output terminals of the first AND gate, the second AND gate, and the third AND gate are respectively connected to a level conversion output circuit.

[0021] As a further embodiment, each level conversion output circuit includes: a first NMOS transistor, a second NMOS transistor, and a third NMOS transistor respectively connected to the first AND gate, the second AND gate, and the third AND gate;

[0022] In this configuration, the gate of the first NMOS transistor is connected to the output terminal of the first AND gate, the source is grounded, and the drain is connected to the output pin.

[0023] The gate of the second NMOS transistor is connected to the output of the second AND gate, the source is grounded, and the drain is connected to the gate of the fourth PMOS transistor; a first resistor is connected between the gate and the source of the fourth PMOS transistor, and the source of the fourth PMOS transistor is connected to the second drive power input pin; the drain of the fourth PMOS transistor is connected to the output pin.

[0024] The gate of the third NMOS transistor is connected to the output of the third AND gate, the source is grounded, and the drain is connected to the gate of the fifth PMOS transistor through the second resistor; the gate and source of the fifth PMOS transistor are connected, and the source of the fifth PMOS transistor is connected to the first drive power input pin; the drain of the fifth PMOS transistor is connected to the output pin.

[0025] The first drive power input pin is connected to the first drive power supply Vh, and the second drive power input pin is connected to the second drive power supply Vm.

[0026] In other embodiments, the following technical solutions are adopted:

[0027] A driver chip, comprising the above-described output driver integrated circuit.

[0028] As a further option, the driver chip serves as the voltage driver chip for the liquid crystal writing device.

[0029] Compared with the prior art, the beneficial effects of this utility model are:

[0030] (1) Each output of the output driver integrated circuit of this utility model can be selected as high impedance state, first voltage Vh, second voltage Vm and zero voltage as needed. These voltage output states can fully meet the voltage required for partial erasure of the liquid crystal writing device. No additional circuit components are needed, which simplifies the circuit structure, greatly reduces production and maintenance costs, and improves product reliability.

[0031] Other features and advantages of this invention will be set forth in part in the description which follows, and in part will be obvious from the description or may be learned by practice of this aspect. Attached Figure Description

[0032] Figure 1 This is a schematic diagram of the output driver integrated circuit architecture in an embodiment of the present invention;

[0033] Figure 2 This is a schematic diagram of the output driver integrated circuit structure in an embodiment of the present invention;

[0034] Figure 3 This is a schematic diagram of the driver chip packaging structure in an embodiment of the present invention. Detailed Implementation

[0035] It should be noted that the following detailed description is illustrative and intended to provide further explanation of the present invention. Unless otherwise specified, all technical and scientific terms used in this invention have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains.

[0036] It should be noted that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the exemplary embodiments according to the present invention. As used herein, the singular form is intended to include the plural form as well, unless the context clearly indicates otherwise. Furthermore, it should be understood that when the terms "comprising" and / or "including" are used in this specification, they indicate the presence of features, steps, operations, devices, components, and / or combinations thereof.

[0037] Example 1

[0038] In one or more embodiments, an output driver integrated circuit is disclosed, combined with Figure 1 ,include:

[0039] Interface circuitry for inputting signals from an external main controller, logic power signals, and drive power signals;

[0040] A shift circuit consisting of multiple sets of shift registers connected in series converts the serial signal input to the main controller of the interface circuit into a parallel output.

[0041] A latching circuit consisting of multiple latches connected in parallel, the number of latches corresponding to the number of shift registers, is used to latch each output of the shift circuit. The purpose of adding a latching circuit is to prevent voltage spikes from occurring at the output of the driver chip during data shifting.

[0042] A decoding circuit composed of multiple sets of decoding units, each set of decoding units converts the output of every two latches into a set of level control signals;

[0043] In addition, there are level conversion output circuits corresponding to multiple groups of decoding units. There are multiple groups of level conversion output circuits, and each group of level conversion output circuits corresponds to a group of decoding units. Each group of level conversion output circuits receives the level control signal output by the corresponding group of decoding units to generate each output state corresponding to the main controller signal. Each output is one of the following: first voltage Vh, second voltage Vm, zero voltage, and high impedance state. At the same time, the output ground can be changed from logic ground LGND to analog ground PGND through level conversion, so that the circuit can work normally even if there is a certain voltage difference between the two grounds.

[0044] As a specific implementation method, combined with Figure 2 The output driver integrated circuit is as follows:

[0045] (1) The interface circuit includes:

[0046] The interface circuit is used to input signals from the external main controller, logic power signals, and drive power signals; it mainly includes:

[0047] The latch input pin LAT is used to input the latch signal. When LAT is high, the data in the shift register is latched and held on the falling edge to ensure that the data is transmitted after it stabilizes.

[0048] The shift register clock input pin CLK is used to input the clock signal. On the rising edge of the clock signal, the shift register reads the data from the serial input (pin A) to synchronize the data shift operation and control the data transmission rhythm.

[0049] The shift register has serial data input pin A and output pin B, which are used to input and output serial data respectively. The data is transmitted serially through the shift register and shifted synchronously by CLK. The output of the last shift register is connected to the output pin B to realize chip cascading. Finally, the data is latched and output to the output pins Q1~Q64 by LAT control.

[0050] The first drive power input pin VH is used to input the first drive power voltage Vh.

[0051] The second drive power input pin VM is used to input the second drive power voltage Vm.

[0052] The logic power input pin VDD is used to input logic power.

[0053] The analog ground pin PGND is used to provide analog ground.

[0054] The logic ground pin LGND is used to provide logic ground.

[0055] (2) The shift circuit includes:

[0056] The shift circuit consists of 128 shift registers (not all of which are shown in the figure). Each shift register includes a serial data input terminal, a clock signal input terminal, and a data output terminal.

[0057] The data input of the first shift register is connected to the serial data input pin A of the shift register, the data output of the previous shift register is connected to the data input of the next shift register, and the output of the last shift register is connected to the output pin B to achieve chip cascading. At the same time, the data output of each shift register is also connected to the data input of the corresponding latch. The clock signal input of each shift register is connected to the clock input pin CLK. The 128-bit shift register will read the serially input data sequentially on the rising edge of the clock signal.

[0058] (3) The latching circuit includes:

[0059] The latch circuit consists of 128 latches (not all of which are shown in the figure). Each latch includes a data input terminal, a latch signal input terminal, and a data output terminal.

[0060] Each latch's data input is connected to a corresponding shift register's data output, and each latch's latch signal input is connected to the latch input pin LAT. When pin LAT is high, the latch's output changes with the input; when pin LAT is low, the latch's output remains in its last state, thus achieving stable latching of the input data.

[0061] The data output terminals of two adjacent latches are connected to a corresponding decoding unit.

[0062] (4) The decoding circuit includes:

[0063] The decoding circuit consists of 64 decoding units (not all of which are shown in the figure). Each decoding unit corresponds to the output of two latches. In this embodiment, each pair of adjacent latches is grouped together and referred to as the first latch and the second latch, respectively.

[0064] Each decoding unit consists of two NOT gates and three AND gates, specifically:

[0065] The data output terminal of the first latch is connected to the first NOT gate, and the data output terminal of the second latch is connected to the second NOT gate. The first and second NOT gates are used to invert the input data. For example, if the input data is 1, the output after passing through the NOT gate is 0.

[0066] The outputs of the first NOT gate and the second NOT gate are respectively connected to the two inputs of the first AND gate; the data outputs of the first latch and the second latch are respectively connected to the two inputs of the third AND gate; the outputs of the first NOT gate and the second latch are respectively connected to the two inputs of the second AND gate; the first AND gate, the second AND gate, and the third AND gate are used to perform logical operations on the input data. The output is 1 only when both inputs are logic 1 (true), otherwise the output is 0.

[0067] The outputs of the first, second, and third AND gates are connected to the level conversion output circuit. Each decoding unit converts the input binary data into a level conversion control signal to select the output channel of the level conversion output circuit, i.e., select ground level output, high impedance output, first voltage Vh output, or second voltage Vm output. In this embodiment, the first voltage Vh > the second voltage Vm, and the voltage range of the first voltage Vh and the second voltage Vm is between [5, 120V]. That is, the values ​​of the first driving power supply Vh and the second driving power supply Vm can be greater than 40V, so the power input terminal can withstand voltages greater than 40V but less than 120V, which is suitable for liquid crystal writing devices with high erasing voltages, such as liquid crystal blackboards. Of course, the values ​​of the first voltage Vh and the second voltage Vm can also be less than 40V.

[0068] (5) The level conversion output circuit includes:

[0069] In this embodiment, the level conversion output circuit has 64 bits, which are respectively set to correspond one-to-one with the 64-bit decoding unit; each level conversion output circuit includes: a first NMOS transistor, a second NMOS transistor, and a third NMOS transistor respectively connected to the first AND gate, the second AND gate, and the third AND gate;

[0070] In this configuration, the gate of the first NMOS transistor is connected to the output terminal of the first AND gate, the source is grounded, and the drain is connected to the output pin.

[0071] The gate of the second NMOS transistor is connected to the output of the second AND gate, the source is grounded, and the drain is connected to the gate of the fourth PMOS transistor. A first resistor is connected between the gate and the source of the fourth PMOS transistor, and the source of the fourth PMOS transistor is connected to the second drive power supply pin. The first drive power supply input pin is connected to the second drive power supply Vm to provide the second voltage Vm. The drain of the fourth PMOS transistor is connected to the output pin.

[0072] The gate of the third NMOS transistor is connected to the output of the third AND gate, the source is grounded, and the drain is connected to the gate of the fifth PMOS transistor through the second resistor. The gate and source of the fifth PMOS transistor are connected, and the source of the fifth PMOS transistor is connected to the first drive power input pin. The second drive power input pin is connected to the first drive power supply Vh to provide the first voltage Vh. The drain of the fifth PMOS transistor is connected to the output pin.

[0073] It should be noted that the drains of the first NMOS transistor, the fourth PMOS transistor, and the fifth PMOS transistor are connected to the same output pin. The level conversion control signal generated by the decoding circuit controls one of the first, second, and third NMOS transistors to turn on. When the level conversion control signal generated by the decoding circuit controls the first NMOS transistor to turn on, the output pin outputs a high-impedance state. When the level conversion control signal generated by the decoding circuit controls the second NMOS transistor to turn on, the output pin outputs a second voltage Vm. When the level conversion control signal generated by the decoding circuit controls the third NMOS transistor to turn on, the output pin outputs a first voltage Vh.

[0074] Each level conversion output circuit is connected to a corresponding driver output pin, for a total of 64 driver output pins Q1~Q64.

[0075] In this embodiment, the external main controller controls the input to each shift register in the shift circuit according to the required voltage output state, and controls the latch circuit to latch the required input to each shift register through the latch signal; the latched data is converted into a level conversion control signal by the decoding circuit, which controls the level conversion output circuit to output the corresponding voltage state. Table 1 shows the correspondence between the data of the two latch circuits and the final drive output.

[0076] Table 1. Correspondence between latch circuit data and drive output

[0077]

[0078] Each output of the output driver integrated circuit of this utility model can be selected as a high-impedance state, a first voltage Vh, a second voltage Vm, or a zero voltage as needed. These voltage output states can fully meet the voltage requirements for partial erasure of the liquid crystal writing device without the need for additional circuit components, simplifying the circuit structure, greatly reducing production and maintenance costs, and improving product reliability.

[0079] Example 2

[0080] In one or more embodiments, a driver chip is disclosed, including the output driver integrated circuit described in Embodiment 1; Figure 3A schematic diagram of the driver chip's package structure is provided, including: first driver power input pin VH, second driver power input pin VM, logic power input pin VDD, analog ground pin PGND, logic ground pin LGND, latch input pin LAT, clock input pin CLK, serial data input pin A, output pin B, and driver output pins Q1~Q64.

[0081] This driver chip can be used as a voltage driver chip for liquid crystal writing devices.

[0082] As a specific example, the liquid crystal writing device includes a first conductive layer, a liquid crystal layer, and a second conductive layer arranged sequentially; the first conductive layer and the second conductive layer are respectively divided into several conductive regions that are parallel to each other and insulated from each other, and the conductive regions on the first conductive layer and the conductive regions on the second conductive layer are perpendicular to each other in space; the local erasure of the target area is achieved by the voltage difference between the spatially overlapping positions of each conductive region on the first conductive layer and each conductive region on the second conductive layer.

[0083] In this embodiment, at least one voltage driving chip is configured for each conductive region on the first conductive layer. The driving outputs Q1 to Q64 of the voltage driving chip are connected to each conductive region on the first conductive layer according to the quantity requirements, and are used to provide the required driving voltage for each conductive region on the first conductive layer. The driving voltage can be a high-resistivity state, a first voltage Vh, a second voltage Vm, or zero voltage.

[0084] Similarly, at least one voltage driving chip is configured for each conductive region on the second conductive layer; the driving outputs Q1~Q64 of the voltage driving chip are connected to each conductive region on the second conductive layer according to the quantity requirements, and are used to provide the required driving voltage for each conductive region on the first conductive layer. The driving voltage can be a high-resistivity state, a first voltage Vh, a second voltage Vm, or zero voltage.

[0085] Based on the specific local erase location and erase voltage control strategy, the main controller can control each drive output pin of the voltage drive chip to output the required voltage to achieve local erase.

[0086] Of course, many specific erase voltage control strategies have been disclosed in the prior art, and this embodiment does not impose any specific limitations.

[0087] In this embodiment, each drive output pin of the voltage drive chip can be directly selected to output a high-impedance state, a first voltage Vh, a second voltage Vm, or zero voltage according to actual needs. This can adapt to different erase voltage control strategies and is particularly suitable for erase voltage control strategies with high-impedance output. No additional circuit components are required, and the circuit structure is simple and reliable.

[0088] Although the specific embodiments of the present utility model have been described above in conjunction with the accompanying drawings, this is not intended to limit the scope of protection of the present utility model. Those skilled in the art should understand that various modifications or variations that can be made by those skilled in the art without creative effort based on the technical solution of the present utility model are still within the scope of protection of the present utility model.

Claims

1. An output driver integrated circuit, comprising: Interface circuitry for inputting signals from an external main controller, logic power signals, and drive power signals; A shift circuit consisting of multiple sets of shift registers connected in series converts the serial signal input to the main controller of the interface circuit into a parallel output. A latching circuit consisting of multiple sets of latches connected in parallel, wherein the number of latches corresponds to the number of shift registers, so as to latch each output of the shift circuit; A decoding circuit composed of multiple sets of decoding units, each set of decoding units converts the output of every two latches into a set of level control signals; Additionally, a level conversion output circuit is provided corresponding to multiple groups of decoding units, which receives the level control signal output by each group of decoding units to generate each output state corresponding to the main controller signal. Each output is one of the following: a first voltage Vh, a second voltage Vm, zero voltage, or a high impedance state.

2. The output driver integrated circuit as described in claim 1, characterized in that, The first voltage Vh and the second voltage Vm satisfy: The first voltage Vh is greater than the second voltage Vm; and the voltage range of the first voltage Vh and the second voltage Vm is between [5, 120V].

3. The output driver integrated circuit as described in claim 1, characterized in that, The interface circuit includes: a latch input pin LAT for inputting latch signals, a shift register clock input pin CLK for inputting clock signals, a shift register serial data input pin A for inputting serial data, an output pin B for cascading, a first drive power input pin VH and a second drive power input pin VM for inputting drive power, a logic power input pin VDD for inputting logic power, and an analog ground pin PGND and a logic ground pin LGND.

4. An output driver integrated circuit as described in claim 1, characterized in that, In the shift circuit, the data output of the previous shift register is connected to the data input of the next shift register; at the same time, the data output of each shift register is also connected to the data input of the corresponding latch; the data input of the first shift register is connected to the serial data input pin A of the shift register, and the output of the last shift register is connected to the output pin B.

5. An output driver integrated circuit as described in claim 1, characterized in that, In the latch circuit, the data input terminal of each latch is connected to the data output terminal of the corresponding shift register, and the latch signal input terminal of each latch is connected to the latch input pin LAT; the data output terminals of two adjacent latches are connected to a corresponding decoding unit.

6. An output driver integrated circuit as described in claim 1, characterized in that, Each decoding unit includes: in two adjacent latches, the data output terminal of the first latch is connected to a first NOT gate, and the data output terminal of the second latch is connected to a second NOT gate; the output terminals of the first NOT gate and the second NOT gate are respectively connected to the two input terminals of a first AND gate; the data output terminals of the first latch and the second latch are respectively connected to the two input terminals of a third AND gate; the output terminals of the first NOT gate and the second latch are respectively connected to the two input terminals of a second AND gate; and the output terminals of the first AND gate, the second AND gate, and the third AND gate are respectively connected to a level conversion output circuit.

7. An output driver integrated circuit as described in claim 1, characterized in that, Each level conversion output circuit includes: a first NMOS transistor, a second NMOS transistor, and a third NMOS transistor, which are respectively connected to the first AND gate, the second AND gate, and the third AND gate; In this configuration, the gate of the first NMOS transistor is connected to the output terminal of the first AND gate, the source is grounded, and the drain is connected to the output pin. The gate of the second NMOS transistor is connected to the output of the second AND gate, the source is grounded, and the drain is connected to the gate of the fourth PMOS transistor; a first resistor is connected between the gate and the source of the fourth PMOS transistor, and the source of the fourth PMOS transistor is connected to the second drive power input pin; the drain of the fourth PMOS transistor is connected to the output pin. The gate of the third NMOS transistor is connected to the output of the third AND gate, the source is grounded, and the drain is connected to the gate of the fifth PMOS transistor through the second resistor; the gate and source of the fifth PMOS transistor are connected, and the source of the fifth PMOS transistor is connected to the first drive power input pin; the drain of the fifth PMOS transistor is connected to the output pin.

8. An output driver integrated circuit as described in claim 7, characterized in that, The first drive power input pin is connected to the first drive power supply Vh, and the second drive power input pin is connected to the second drive power supply Vm.

9. A driver chip, characterized in that, Includes the output driver integrated circuit as described in any one of claims 1-8.

10. A driver chip as described in claim 9, characterized in that, The driving chip serves as the voltage driving chip for the liquid crystal writing device.

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