Thermal management assembly and solid state circuit breaker

Abstract

The utility model provides a kind of thermal management assembly and solid-state circuit breaker, the thermal management assembly is used for semiconductor switching device, comprising: semiconductor refrigerator, including the first refrigerator surface and the second refrigerator surface of relatively arranged along first direction, first refrigerator surface is suitable for heat conduction connection in semiconductor switching device to adjust the temperature of semiconductor switching device;And substrate, including the first substrate surface and the second substrate surface of relatively arranged along first direction, and the substrate outer side surface connected between first substrate surface and second substrate surface, first substrate surface is connected to the second refrigerator surface;Wherein, the thermal management assembly further includes first conductive layer, first conductive layer is located substrate outer side surface and is electrically connected to semiconductor refrigerator.This application by setting first conductive layer on the outer side surface of substrate, so that the space of substrate surface occupied by substrate control circuit can be reduced, and then the integrated density of thermal management assembly can be improved.

Description

Technical Field

[0001] This utility model relates to the field of semiconductor switching device technology, specifically to a thermal management component and a solid-state circuit breaker. Background Technology

[0002] During the switching process, semiconductor switching devices (such as IGBTs and MOSFETs) in solid-state circuit breakers generate Joule heat due to their internal resistance. Under overload or high-frequency operation, this can easily lead to excessively high junction temperatures, resulting in degraded device performance or even failure.

[0003] Semiconductor switching modules and their cooling equipment are mostly independent components, and their structure is not deeply integrated, resulting in a large device size that is difficult to adapt to the installation requirements of compact low-voltage power distribution equipment. Utility Model Content

[0004] The embodiments of this utility model provide a thermal management component and a solid-state circuit breaker, which can improve the technical problem of large size of cooling equipment for semiconductor switching devices.

[0005] In a first aspect, embodiments of the present invention provide a thermal management component for a semiconductor switching device, comprising:

[0006] A semiconductor cooler includes a first cooler surface and a second cooler surface disposed opposite each other along a first direction, the first cooler surface being thermally connected to the semiconductor switching device to adjust the temperature of the semiconductor switching device; and

[0007] The substrate includes a first substrate surface and a second substrate surface disposed opposite to each other along the first direction, and an outer surface of the substrate connected between the first substrate surface and the second substrate surface, wherein the first substrate surface is connected to the second cooler surface;

[0008] The thermal management component further includes a first conductive layer, which is disposed on the outer side of the substrate and electrically connected to the semiconductor cooler.

[0009] In one embodiment, the first conductive layer is a silver-plated layer; and / or

[0010] The width of the first conductive layer ranges from 0.2 mm to 0.5 mm.

[0011] In one embodiment, a first bonding layer is further included, the first bonding layer being adapted to bond between the first cooler surface of the thermoelectric cooler and the semiconductor switching device.

[0012] In one embodiment, the thickness of the first bonding layer ranges from 5 μm to 10 μm; and / or

[0013] The first bonding layer is a silver paste bonding layer, wherein the silver powder particle size in the silver paste bonding layer does not exceed 5 μm, and the thermal conductivity of the silver paste bonding layer is greater than 100 W / m·K; or, the first bonding layer is an inert solder bonding layer, wherein the thermal resistance of the inert solder bonding layer does not exceed 0.05 °C·cm. 2 / W; and / or

[0014] The first bonding layer is adapted to bond to an effective heat dissipation region of the semiconductor switching device to form a bonding surface, wherein the ratio of the area of ​​the bonding surface to the area of ​​the semiconductor switching device is (98-100):100; and / or

[0015] A waterproof layer is provided at the junction of the first bonding layer with the surface of the first cooler and the semiconductor switching device.

[0016] In one embodiment, the thermoelectric cooler is a thermoelectric cooler chip with an insulating encapsulation layer on its surface. The insulating encapsulation layer is a ceramic insulating encapsulation layer. The thickness of the thermoelectric cooler chip ranges from 2 mm to 3 mm, and the thickness of the insulating encapsulation layer ranges from 0.1 mm to 0.3 mm; and / or

[0017] A fan is provided on the surface of the first cooler.

[0018] In one embodiment, the substrate is a thermally conductive substrate, and the first substrate surface of the substrate is bonded to the second cooler surface of the semiconductor cooler;

[0019] Wherein, within the bonding region between the thermally conductive substrate and the semiconductor cooler, the surface roughness Ra of the first substrate surface and / or the second cooler surface does not exceed 0.1 μm; and / or

[0020] The substrate contains at least 96% AlN by mass; and / or

[0021] The thermal conductivity of the substrate is not less than 180 W / m·K.

[0022] In one embodiment, a second bonding layer is further included, the second bonding layer being adapted to be bonded between the surface of the second cooler and the surface of the first substrate.

[0023] In one embodiment, the second bonding layer is adapted to bond to the thermoelectric cooler to form a bonding surface, wherein the area of ​​the bonding surface is in a 1:1 ratio to the area of ​​the thermoelectric cooler; and / or

[0024] The thickness of the second bonding layer is 5 μm-10 μm; and / or

[0025] The second bonding layer is a silver paste bonding layer, wherein the silver powder particle size in the silver paste bonding layer is less than or equal to 5 μm, and the thermal conductivity of the silver paste bonding layer is greater than 100 W / m·K.

[0026] In one embodiment, it further includes a micro heat pipe array, and the substrate is a thermally conductive substrate;

[0027] The micro heat pipe array is connected to the second substrate surface of the substrate to connect the semiconductor cooler through the substrate for thermal conduction.

[0028] In one embodiment, the surface of the second substrate is provided with a plurality of trenches.

[0029] In one embodiment, the depth of the trench ranges from 30 μm to 80 μm; and / or

[0030] The thickness of the substrate is 0.2mm-0.5mm.

[0031] In one embodiment, the micro heat pipe array is welded to the substrate;

[0032] A barrier layer is provided between the substrate and the micro heat pipe array, and the barrier layer surrounds the welding joint between the substrate and the micro heat pipe array.

[0033] In one embodiment, the micro heat pipe array is soldered to the substrate using Sn-Ag-Cu solder; and / or

[0034] The barrier layer is a nickel layer.

[0035] In one embodiment, the device further includes a housing, in which the semiconductor switching device, the semiconductor cooler, the substrate, and the micro heat pipe array are disposed along the first direction.

[0036] In one embodiment, the encapsulation housing is a Kovar alloy housing; and / or

[0037] The thickness of the encapsulation shell is 0.4mm-0.6mm; and / or

[0038] The encapsulation shell is filled with an inert gas, the humidity of which does not exceed 5 ppm.

[0039] In one embodiment, the encapsulation housing is provided with a plurality of heat dissipation fins, which are thermally connected to the micro heat pipe array.

[0040] In one embodiment, the height of the heat dissipation fins ranges from 4mm to 6mm; and / or

[0041] The distance between two adjacent fins ranges from 0.8 mm to 1.2 mm; and / or

[0042] A heat-conducting layer is provided between the heat dissipation fins and the micro heat pipe array.

[0043] In one embodiment, a buffer layer is provided between the package housing and the semiconductor cooler, the substrate, and the micro heat pipe array.

[0044] In one embodiment, the thickness of the buffer layer is 0.4 mm to 0.6 mm.

[0045] In one embodiment, the package housing is provided with pads, and the electrodes of the semiconductor switching device are electrically connected to the pads; and / or

[0046] The package housing is provided with pads, a second conductive layer electrically connected to the first conductive layer is provided at the edge of the surface of the first substrate, a third conductive layer is provided at the edge of the surface of the second cooler, the second conductive layer is electrically connected to the third conductive layer, and the first conductive layer is electrically connected to the pads.

[0047] In one embodiment, the widths of the second conductive layer and the third conductive layer range from 0.4 mm to 0.6 mm; and / or

[0048] The second conductive layer and the third conductive layer are silver-plated layers.

[0049] In one embodiment, the semiconductor switching device has a size of 10mm × 10mm and a heat flux density of 100W / cm². 2 -200W / cm 2 .

[0050] Secondly, embodiments of the present invention provide a solid-state circuit breaker, comprising: a semiconductor switching device and the aforementioned thermal management component.

[0051] In the embodiments of this utility model, by providing a first conductive layer on the outer side of the substrate and realizing low-pressure control of the semiconductor cooler through the first conductive layer, the space occupied by the substrate control circuit on the substrate surface can be reduced, thereby reducing the volume of the thermal management component and increasing the integration density of the thermal management component. Attached Figure Description

[0052] To more clearly illustrate the technical solutions in the embodiments of this utility model, the drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this utility model. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0053] Figure 1This is a cross-sectional view of the thermal management component provided in an embodiment of this utility model.

[0054] Explanation of reference numerals in the attached figures: Semiconductor switching device-1; Semiconductor cooler-2; Substrate-3; Trench-31; Fan-4; Micro heat pipe array-5; Encapsulation shell-6; Heat dissipation fins-61; Pad-62; First bonding layer-7; Second bonding layer-8; Barrier layer-9; Thermally conductive layer-10; Buffer layer-11; First conductive layer-12; Second conductive layer-13; Third conductive layer-14. Detailed Implementation

[0055] The technical solutions of the present utility model will be clearly and completely described below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are only some embodiments of the present utility model, and not all embodiments. Based on the embodiments of the present utility model, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present utility model. In addition, it should be understood that the specific embodiments described herein are only for illustration and explanation of the present utility model and are not intended to limit the present utility model. In the present utility model, unless otherwise stated, directional terms such as "upper" and "lower" generally refer to the upper and lower positions of the device in actual use or operation, specifically the drawing directions in the accompanying drawings; while "inner" and "outer" refer to the outline of the device.

[0056] Firstly, please refer to Figure 1 An embodiment of this utility model provides a thermal management component for a semiconductor switching device 1, comprising:

[0057] The semiconductor cooler 2 includes a first cooler surface and a second cooler surface disposed opposite each other along a first direction A. The first cooler surface is thermally connected to the semiconductor switching device 1 to adjust the temperature of the semiconductor switching device 1.

[0058] The substrate 3 includes a first substrate surface and a second substrate surface disposed opposite to each other along the first direction A, and an outer side surface of the substrate connected between the first substrate surface and the second substrate surface, wherein the first substrate surface is connected to the second cooler surface;

[0059] The thermal management component further includes a first conductive layer 12, which is disposed on the outer side of the substrate 3 and electrically connected to the semiconductor cooler 2.

[0060] It is understood that by setting a first conductive layer 12 on the outer surface of the substrate 3 and using the first conductive layer 12 to achieve low-voltage control of the semiconductor cooler 2, the space occupied by the control circuit on the surface of the substrate 3 can be reduced, thereby reducing the volume of the thermal management component and increasing the integration density of the thermal management component. Simultaneously, by placing the control circuit of the substrate 3 within the first conductive layer 12 on the outer surface of the substrate 3, the low-voltage control circuit of the substrate 3 can be isolated from and kept away from the high-voltage semiconductor switching device 1, thereby ensuring the electrical safety of both the low-voltage control circuit of the substrate 3 and the high-voltage power circuit of the semiconductor switching device 1.

[0061] It is understood that the thermoelectric cooler 2 can heat and cool the semiconductor switching device 1, thereby controlling and adjusting the temperature of the semiconductor switching device 1. The PN junction array inside the thermoelectric cooler 2 can form natural electrical isolation between the surface of the first cooler and the surface of the second cooler, thereby cutting off the potential conduction path between the semiconductor switching device 1 and the TEC, thus improving the accuracy of temperature control of the semiconductor switching device 1, reducing thermal interference, protecting the semiconductor switching device 1, and reducing electromagnetic interference (EMI).

[0062] It can be understood that the first conductive layer 12 is a conductive network with a three-dimensional conductive path. Through graphical design, a conductive path with separate positive and negative electrodes can be realized, which can meet the requirements of electrical isolation and signal integrity. Through its integrated design, space can also be saved.

[0063] In one embodiment, the first conductive layer 12 is a silver-plated layer.

[0064] It is understandable that using a silver plating layer as the first conductive layer 12 can improve the conductivity of the conductive layer, enhance its anti-oxidation and corrosion resistance, improve the uniformity and continuity of the conductive path, adapt to complex geometries and structures, and improve its mechanical properties and flexibility.

[0065] In one embodiment, the width of the first conductive layer 12 is in the range of 0.2mm-0.5mm, for example, it can be 0.2mm, 0.3mm, 0.4mm, 0.5mm, etc.

[0066] In one embodiment, a first bonding layer 7 is further included, the first bonding layer 7 being adapted to bond between the first cooler surface of the semiconductor cooler 2 and the semiconductor switching device 1.

[0067] It is understandable that by setting a first bonding layer 7 between the first cooler surface of the thermoelectric cooler 2 and the semiconductor switching device 1, the thermoelectric cooler 2 and the semiconductor switching device 1 can be fixed together. Simultaneously, there is no air gap between the thermoelectric cooler 2 and the semiconductor switching device 1, thereby reducing the thermal resistance between them, improving heat transfer efficiency, and thus better achieving temperature control of the semiconductor switching device 1. Compared to contact mounting of the thermoelectric cooler 2 and the semiconductor switching device 1 (such as parallel bonding or vertical embedding), relying on thermal grease or adjustable fixing devices to ensure contact force, bonding the thermoelectric cooler 2 and the semiconductor switching device 1 through the first bonding layer 7 can effectively reduce the thermal resistance between them.

[0068] In one embodiment, the thickness of the first bonding layer 7 is in the range of 5μm-10μm, for example, it can be 5μm, 6μm, 7μm, 8μm, 9μm, 10μm, etc.

[0069] It is understandable that by controlling the thickness of the first bonding layer 7, the semiconductor cooler 2 and the semiconductor switching device 1 can be effectively bonded, while the heat transfer time of the first bonding layer 7 can be controlled. If the thickness of the first bonding layer 7 is less than 5 μm, local voids are easily caused due to uneven thickness of the first bonding layer 7, resulting in high thermal resistance of the first bonding layer 7. If the thickness of the first bonding layer 7 is greater than 10 μm, the thermal resistance of the first bonding layer 7 increases significantly (approximately 0.02 °C / W for every 1 μm increase), and the structural stability of the first bonding layer 7 decreases, making it prone to cracking.

[0070] In one embodiment, the first bonding layer 7 is a silver paste bonding layer, wherein the silver powder particle size in the silver paste bonding layer does not exceed 5 μm, and the thermal conductivity of the silver paste bonding layer is greater than 100 W / m·K; or, the first bonding layer 7 is an inert solder bonding layer, wherein the thermal resistance of the inert solder bonding layer does not exceed 0.05 °C·cm. 2 / W.

[0071] It is understood that the material of the silver paste bonding layer is silver paste, a conductive material composed of silver powder and polymer materials (such as epoxy resin), mainly used for heat dissipation and fixation between the chip and the substrate. The smaller the particle size of the silver powder, the better the filling performance of the silver paste at the bonding interface, the lower the thermal resistance, and the stronger the mechanical strength. By controlling the silver powder particle size of the sintered silver paste to ≤5μm, the porosity of the silver paste after curing can be reduced, the contact area between particles can be increased, and the thermal conductivity of the sintered silver paste bonding layer can be >100W / m·K (the thermal conductivity of traditional silver paste is about 50-80W / m·K), while the shear strength is ≥30MPa. Solder is a metallic material used for brazing in welding applications requiring high strength and corrosion resistance.

[0072] In one embodiment, the first bonding layer 7 is adapted to be bonded to the effective heat dissipation area of ​​the semiconductor switching device 1 to form a bonding surface, wherein the ratio of the area of ​​the bonding surface to the area of ​​the semiconductor switching device 1 is (98-100):100, for example, it can be 98:100, 99:100, or 100:100.

[0073] It is understood that the effective heat dissipation area of ​​the semiconductor switching device 1 is its central area (accounting for more than 98% of the area of ​​the semiconductor switching device 1), and its edge area is used for electrode lead-out. By making the first bonding layer 7 completely cover the effective heat dissipation area of ​​the semiconductor switching device 1, edge thermal islands can be eliminated, the heat conduction path can be expanded, and the heat conduction effect can be improved, thereby better controlling the temperature of the semiconductor switching device 1.

[0074] In one embodiment, a waterproof layer is provided at the junction of the first bonding layer 7 with the surface of the first cooler and the semiconductor switching device 1.

[0075] It is understandable that by providing a waterproof layer at the edge of the first bonding layer 7, moisture can be prevented from corroding the interface between the semiconductor switching device 1 and the semiconductor cooler 2.

[0076] As an example, the waterproof layer can be a silicone rubber waterproof layer.

[0077] In one embodiment, the semiconductor cooler 2 is a semiconductor cooler chip with an insulating encapsulation layer on its surface. The insulating encapsulation layer is a ceramic insulating encapsulation layer. The thickness of the semiconductor cooler chip ranges from 2mm to 3mm, for example, it can be 2mm, 2.2mm, 2.5mm, 2.7mm, 3mm, etc. The thickness of the insulating encapsulation layer ranges from 0.1mm to 0.3mm, for example, it can be 0.1mm, 0.2mm, 0.3mm, etc.

[0078] It is understandable that insulating the thermoelectric cooler protects it from environmental damage, provides electrical isolation and mechanical protection, ensures stable operation under complex conditions, and better cuts off the potential conduction path between the semiconductor switching device 1 and the thermoelectric cooler. By using ceramic insulating encapsulation and controlling the thickness of the ceramic insulating encapsulation layer, the dielectric strength of the ceramic insulating encapsulation layer can be controlled, allowing it to withstand a withstand voltage more than twice the operating voltage of the thermoelectric cooler, thus meeting industrial-grade insulation requirements. The insulating encapsulation layer further isolates the low-voltage control circuit of the substrate 3 from the high-voltage semiconductor switching device 1, improving the electrical safety of both the low-voltage control circuit of the substrate 3 and the high-voltage power circuit of the semiconductor switching device 1.

[0079] In one embodiment, a fan 4 is provided on the surface of the first cooler.

[0080] It is understandable that the heat dissipation effect of the thermal management components can be further improved by placing the fan 4 on the surface of the first cooler. By placing the fan 4 on the surface of the first cooler, heat interference from both sides of the semiconductor cooler 2 can be avoided, thereby improving the temperature control effect, which is suitable for high power density scenarios (such as server CPU liquid cooling systems).

[0081] As an example, the surface of the first cooler is covered with a first bonding layer 7, and therefore, the fan 4 is disposed on the surface of the first cooler outside the first bonding layer 7.

[0082] In one embodiment, the substrate 3 is a thermally conductive substrate, and the first substrate surface of the substrate 3 is bonded to the second cooler surface of the semiconductor cooler 2;

[0083] Wherein, in the bonding area between the thermally conductive substrate and the semiconductor cooler 2, the surface roughness Ra of the first substrate surface and / or the second cooler surface does not exceed 0.1 μm.

[0084] It is understood that by controlling the surface roughness Ra of the first substrate surface and / or the second cooler surface in the bonding area between the thermally conductive substrate and the semiconductor cooler 2, the first substrate surface and the second cooler surface can achieve molecular-level bonding, thereby reducing the interfacial thermal resistance between them.

[0085] As an example, the surface roughness Ra of the first substrate surface and / or the second cooler surface can be made not more than 0.1 μm by chemical mechanical polishing (CMP).

[0086] In one embodiment, the AlN mass content in the substrate 3 is not less than 96%.

[0087] It is understandable that the higher the AlN content in substrate 3, the better the thermal conductivity of substrate 3, but the higher the AlN content, the higher the cost of substrate 3. By ensuring that the AlN content in substrate 3 is not less than 96%, the thermal conductivity of substrate 3 can reach 180 W / m·K, thus balancing the thermal conductivity and cost of substrate 3.

[0088] In one embodiment, the thermal conductivity of the substrate 3 is not less than 180 W / m·K.

[0089] In one embodiment, a second bonding layer 8 is further included, the second bonding layer 8 being adapted to be bonded between the surface of the second cooler and the surface of the first substrate.

[0090] It is understood that by setting a second bonding layer 8 between the surface of the second cooler and the surface of the first substrate, the semiconductor cooler 2 and the substrate 3 can be fixed together. At the same time, there is no air gap between the semiconductor cooler 2 and the substrate 3, thereby reducing the thermal resistance between them, improving the heat transfer efficiency, and thus better realizing the temperature control of the semiconductor switching device 1.

[0091] In one embodiment, the second bonding layer 8 is adapted to be bonded to the semiconductor cooler 2 to form a bonding surface, wherein the area of ​​the bonding surface is in a 1:1 ratio to the area of ​​the semiconductor cooler 2.

[0092] It is understandable that by making the second bonding layer 8 completely cover the surface of the second cooler of the semiconductor cooling chip, the heat conduction path can be expanded and the heat conduction effect can be improved, thereby better controlling the temperature of the semiconductor switching device 1.

[0093] In one embodiment, the thickness of the second bonding layer 8 is 5μm-10μm, for example, it can be 5μm, 6μm, 7μm, 8μm, 9μm, 10μm, etc.

[0094] It is understandable that by controlling the thickness of the second bonding layer 8, the semiconductor cooler 2 and the substrate 3 can be effectively bonded, while the heat transfer time of the second bonding layer 8 can be controlled. If the thickness of the second bonding layer 8 is less than 5 μm, local voids are easily caused by uneven thickness of the second bonding layer 8, resulting in high thermal resistance of the second bonding layer 8. If the thickness of the second bonding layer 8 is greater than 10 μm, the thermal resistance of the second bonding layer 8 increases significantly (approximately 0.02 °C / W for every 1 μm increase), and the structural stability of the second bonding layer 8 decreases, making it prone to cracking.

[0095] In one embodiment, the second bonding layer 8 is a silver paste bonding layer, wherein the silver powder particle size in the silver paste bonding layer is less than or equal to 5 μm, and the thermal conductivity of the silver paste bonding layer is greater than 100 W / m·K.

[0096] It is understandable that the material of the silver paste bonding layer is silver paste, a conductive material composed of silver powder and polymer materials (such as epoxy resin), mainly used for heat dissipation and fixation between the chip and the substrate. The smaller the particle size of the silver powder, the better the filling performance of the silver paste at the bonding interface, the lower the thermal resistance, and the stronger the mechanical strength. By controlling the silver powder particle size of the sintered silver paste to ≤5μm, the porosity of the silver paste after curing can be reduced, the contact area between particles can be increased, and the thermal conductivity of the sintered silver paste bonding layer can be >100W / m·K (the thermal conductivity of traditional silver paste is about 50-80W / m·K), while the shear strength is ≥30MPa.

[0097] In one embodiment, it further includes a micro heat pipe array 5, and the substrate 3 is a thermally conductive substrate;

[0098] The micro heat pipe array 5 is connected to the second substrate surface of the substrate 3 to conduct heat to the semiconductor cooler 2 through the substrate 3.

[0099] It is understandable that the micro heat pipe array 5 is a highly efficient heat transfer element, whose core advantage lies in achieving rapid heat transfer and uniform temperature distribution through the phase change heat transfer principle. By connecting the micro heat pipe array 5 to the surface of the second substrate of the heat-conducting substrate, the heat of the heat-conducting substrate can be rapidly transferred through the micro heat pipe array 5, thereby improving the heat transfer efficiency.

[0100] In one embodiment, the surface of the second substrate is provided with a plurality of trenches 31.

[0101] It is understandable that by setting multiple grooves 31 on the surface of the second substrate, the capillary force of the micro heat pipe array 5 can be improved, thereby enhancing the heat transfer capability of the micro heat pipe array 5.

[0102] In one embodiment, the depth of the trench 31 is in the range of 30μm-80μm, for example, it can be 30μm, 40μm, 50μm, 60μm, 70μm, 80μm, etc.

[0103] It is understandable that if the depth of the trench 31 is less than 30μm, the capillary force of the micro heat pipe array 5 is weak, the working fluid recirculation speed of the micro heat pipe array 5 is slow, and the heat transfer capacity is reduced. If the depth of the trench 31 is greater than 80μm, the mechanical strength of the substrate 3 is reduced, and solder is easily left at the bottom of the trench 31, which affects the welding quality between the substrate 3 and the micro heat pipe array 5.

[0104] In one embodiment, the thickness of the substrate 3 is 0.2mm-0.5mm, for example, it can be 0.2mm, 0.3mm, 0.4mm, 0.5mm, etc.

[0105] In one embodiment, the micro heat pipe array 5 is welded to the substrate 3;

[0106] A barrier layer 9 is provided between the substrate 3 and the micro heat pipe array 5, and the barrier layer 9 surrounds the welding joint of the substrate 3 and the micro heat pipe array 5.

[0107] As an example, micro heat pipe array 5 is a copper heat pipe array.

[0108] It is understandable that the barrier layer 9 can prevent elemental interdiffusion between the substrate 3 and the micro heat pipe array 5 (Al in the substrate 3 and Cu in the micro heat pipe array 5 are prone to forming a brittle phase Al2Cu at high temperatures), and can prevent embrittlement of the welding interface and thermal fatigue failure, thereby improving the connection reliability between the substrate 3 and the micro heat pipe array 5.

[0109] In one embodiment, the micro heat pipe array 5 is soldered to the substrate 3 using Sn-Ag-Cu solder.

[0110] In one embodiment, the barrier layer 9 is a nickel layer.

[0111] It is understandable that nickel-layered solders have good compatibility (the wetting angle between Sn-Ag-Cu solder and nickel is <20°).

[0112] In one embodiment, the thickness of the micro heat pipe array 5 is in the range of 1mm-2mm, for example, it can be 1mm, 2mm, etc.

[0113] It is understandable that the micro heat pipe array 5 is too thick, making it unsuitable for compact packaging, and it also increases thermal response delay.

[0114] In one embodiment, the working fluid of the micro heat pipe array 5 includes water, and the liquid filling amount of the micro heat pipe array 5 is 50%-70%, for example, it can be 50%, 52%, 55%, 57%, 60%, 62%, 65%, 67%, 70%, etc.

[0115] It is understandable that if the liquid filling volume of the micro heat pipe array 5 is less than 50%, its working fluid content is insufficient, and the evaporation section is prone to drying out; if the liquid filling volume of the micro heat pipe array 5 is greater than 70%, the working fluid in the condensation section is prone to stagnation, inhibiting steam flow and reducing heat transfer efficiency. By making the liquid filling volume of the micro heat pipe array 5 50%-70%, the heat transfer power of the micro heat pipe array 5 is ≥50W, and ΔT reaches 20℃.

[0116] In one embodiment, the device further includes a housing 6, in which the semiconductor switching device 1, the semiconductor cooler 2, the substrate 3, and the micro heat pipe array 5 are disposed along the first direction A within the housing 6.

[0117] It is understood that the package housing 6 is used to seal the semiconductor switching device 1, the semiconductor cooler 2, the substrate 3 and the micro heat pipe array 5 within the package housing 6, thereby enabling deep integration of multiple independent components such as the semiconductor cooler 2, the substrate 3 and the micro heat pipe array 5, reducing the volume of the thermal management components to adapt to compact devices and improve power density.

[0118] As an example, the package housing 6 includes a cover plate and a shell. During installation, the semiconductor cooler 2, the substrate 3, and the micro heat pipe array 5 are first placed inside the shell, and then the cover plate and the shell are laser welded (leakage rate ≤ 1×10⁻⁶). -9 The bonding layer is welded together (mbar·L / s) to seal the package housing 6, thereby preventing moisture from entering the package housing 6 and causing chip corrosion or electrical short circuit, while also inhibiting the oxidation of the bonding layer (silver paste is prone to oxidation when exposed to air for a long time).

[0119] In one embodiment, the encapsulation housing 6 is a Kovar alloy housing.

[0120] It is understandable that Kovar alloy is an iron-nickel-cobalt alloy with special thermal expansion properties, which can allow for thermal expansion displacement of ±50μm, thereby reducing the interfacial stress (≤10MPa) under high and low temperature cycling (-40℃~125℃).

[0121] In one embodiment, the thickness of the encapsulation shell 6 is 0.4mm-0.6mm.

[0122] It is understandable that if the thickness of the encapsulation shell 6 is less than 0.4mm, the mechanical strength of the encapsulation shell 6 is insufficient (compressive strength < 200MPa), and the airtightness is difficult to guarantee; if the thickness of the encapsulation shell 6 is greater than 0.6mm, the thermal resistance of the encapsulation shell 6 increases, and the weight increases, which is not suitable for miniaturization requirements.

[0123] In one embodiment, the encapsulation housing 6 is filled with an inert gas, the humidity of which does not exceed 5 ppm.

[0124] It is understandable that by filling the inside of the package housing 6 with dry inert gas (humidity ≤ 5ppm), the humidity inside the package housing 6 can be controlled, thereby preventing moisture from causing chip corrosion or electrical short circuits, and inhibiting the oxidation of the bonding layer (silver paste is prone to oxidation when exposed to air for a long time).

[0125] As an example, the encapsulation housing 6 is filled with dry nitrogen gas.

[0126] In one embodiment, the encapsulation shell 6 is provided with a plurality of heat dissipation fins 61, and the plurality of heat dissipation fins 61 are thermally connected to the micro heat pipe array 5.

[0127] It is understandable that by setting multiple heat dissipation fins 61 inside the package housing 6, the heat dissipation area of ​​the package housing 6 can be increased.

[0128] In one embodiment, the height of the heat dissipation fins 61 ranges from 4mm to 6mm, for example, it can be 4mm, 5mm, 6mm, etc.; and / or

[0129] The distance between two adjacent fins ranges from 0.8mm to 1.2mm, for example, it can be 0.8mm, 0.9mm, 1.0mm, 1.1mm, 1.2mm, etc.

[0130] It is understandable that by controlling the height of the heat dissipation fins 61 and the spacing between adjacent fins, the heat dissipation effect of the heat dissipation fins 61 can be improved, while taking into account both the heat dissipation efficiency and mechanical reliability of the heat dissipation fins 61.

[0131] In one embodiment, a heat-conducting layer 10 is provided between the heat dissipation fins 61 and the micro heat pipe array 5.

[0132] It is understandable that by setting a heat-conducting layer 10 between the heat dissipation fins 61 and the micro heat pipe array 5, the tiny gaps between the contact surfaces can be effectively filled, thereby reducing thermal resistance and improving heat dissipation efficiency.

[0133] As an example, the thermally conductive layer 10 is a thermally conductive silicone grease layer, which has excellent thermal conductivity and electrical insulation.

[0134] In one embodiment, a buffer layer 11 is provided between the package housing 6 and the semiconductor cooler 2, the substrate 3 and the micro heat pipe array 5.

[0135] It is understood that by providing a buffer layer 11 between the package housing 6 and the semiconductor cooler 2, the substrate 3 and the micro heat pipe array 5, the mechanical stress between the package housing 6 and the semiconductor cooler 2, the substrate 3 and the micro heat pipe array 5 can be relieved, while preventing moisture and contaminants from causing corrosion or contamination to the semiconductor cooler 2, the substrate 3 and the micro heat pipe array 5.

[0136] As an example, the buffer layer 11 is a silicone rubber buffer layer 11. The silicone rubber buffer layer 11 and the silicone rubber waterproof layer can be integrally molded.

[0137] In one embodiment, the thickness of the buffer layer 11 is 0.4mm-0.6mm, for example, it can be 0.4mm, 0.5mm, 0.6mm, etc.

[0138] In one embodiment, the package housing 6 is provided with pads 62, and the electrodes of the semiconductor switching device 1 are electrically connected to the pads 62.

[0139] It can be understood that by electrically connecting the electrodes of the semiconductor switching device 1 to the pads 62 of the package housing 6, the semiconductor switching device 1 can be electrically connected to the external driving circuit outside the package housing 6 through the pads 62, thereby realizing the control of the semiconductor switching device 1.

[0140] As an example, the electrodes of the semiconductor switching device 1 are electrically connected to the pads 62 via gold wires. The pads 62 are embedded in the housing of the package housing 6.

[0141] In one embodiment, the package housing 6 is provided with pads 62, the edge of the first substrate surface is provided with a second conductive layer 13 electrically connected to the first conductive layer 12, the edge of the second cooler surface is provided with a third conductive layer 14, the second conductive layer 13 is electrically connected to the third conductive layer 14, and the first conductive layer 12 is electrically connected to the pads 62.

[0142] It can be understood that the control signal outside the package 6 is transmitted to the first conductive layer 12 through the pad 62, then to the second conductive layer 13 which is electrically connected to the first conductive layer 12, then to the third conductive layer 14 which is electrically connected to the second conductive layer 13, and finally to the semiconductor cooler 2, thereby realizing the control of the semiconductor cooler 2.

[0143] As an example, the control signal can be issued by the control unit (an ARM Cortex-M7-based microcontroller) of the temperature control module, which can control the thermoelectric cooler 2 to perform cooling or heating, and can control the direction and magnitude of the current in the thermoelectric cooler 2. The third conductive layer 14 can be formed on the ceramic package surface of the thermoelectric cooler 2 using photolithography. The second conductive layer 13 and the third conductive layer 14 can be electrically connected through the second bonding layer 8 between them. The first conductive layer 12 and the second conductive layer 13 can be integrally formed.

[0144] In one embodiment, the width of the second conductive layer 13 and the third conductive layer 14 is in the range of 0.4mm-0.6mm, for example, 0.4mm, 0.5mm, 0.6mm, etc.

[0145] In one embodiment, the second conductive layer 13 and the third conductive layer 14 are silver-plated layers.

[0146] In one embodiment, the semiconductor switching device 1 has a size of 10mm × 10mm and a heat flux density of 100W / cm². 2 -200W / cm 2 For example, it can be 100W / cm 2 110W / cm 2 120W / cm 2 130W / cm 2 140W / cm 2 150W / cm 2 160W / cm 2 170W / cm 2 180W / cm 2 190W / cm 2 200W / cm 2 wait.

[0147] Secondly, embodiments of the present invention provide a solid-state circuit breaker, comprising: a semiconductor switching device and the aforementioned thermal management component.

[0148] The embodiments of this utility model have been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of this utility model. The description of the above embodiments is only for the purpose of helping to understand the method and core ideas of this utility model. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of this utility model. Therefore, the content of this specification should not be construed as a limitation of this utility model.

Claims

1. A thermal management component for a semiconductor switching device, characterized in that, include: A semiconductor cooler includes a first cooler surface and a second cooler surface disposed opposite each other along a first direction, wherein the first cooler surface is thermally connected to the semiconductor switching device to adjust the temperature of the semiconductor switching device. as well as The substrate includes a first substrate surface and a second substrate surface disposed opposite to each other along the first direction, and an outer surface of the substrate connected between the first substrate surface and the second substrate surface, wherein the first substrate surface is connected to the second cooler surface; The thermal management component further includes a first conductive layer, which is disposed on the outer side of the substrate and electrically connected to the semiconductor cooler.

2. The thermal management component according to claim 1, characterized in that, The first conductive layer is a silver-plated layer; and / or The width of the first conductive layer ranges from 0.2 mm to 0.5 mm.

3. The thermal management component according to claim 1, characterized in that, It also includes a first bonding layer adapted to bond between the first cooler surface of the semiconductor cooler and the semiconductor switching device.

4. The thermal management component according to claim 3, characterized in that, The thickness of the first bonding layer ranges from 5 μm to 10 μm; and / or The first bonding layer is a silver glue bonding layer, a particle size of silver powder in the silver glue bonding layer is not more than 5 μm, a thermal conductivity of the silver glue bonding layer is greater than 100 W / m·K, or the first bonding layer is a solder bonding layer, a thermal resistance of the solder bonding layer is not more than 0.05 ℃·cm 2 W; and / or The first bonding layer is adapted to bond to an effective heat dissipation region of the semiconductor switching device to form a bonding surface, wherein the ratio of the area of ​​the bonding surface to the area of ​​the semiconductor switching device is (98-100):100; and / or A waterproof layer is provided at the junction of the first bonding layer with the surface of the first cooler and the semiconductor switching device.

5. The thermal management component according to claim 1, characterized in that, The semiconductor cooler is a semiconductor cooler chip with an insulating encapsulation layer on its surface. The insulating encapsulation layer is a ceramic insulating encapsulation layer. The thickness of the semiconductor cooler chip ranges from 2mm to 3mm, and the thickness of the insulating encapsulation layer ranges from 0.1mm to 0.3mm; and / or A fan is provided on the surface of the first cooler.

6. The thermal management component according to claim 1, characterized in that, The substrate is a thermally conductive substrate, and the first substrate surface of the substrate is bonded to the second cooler surface of the semiconductor cooler; Wherein, within the bonding region between the thermally conductive substrate and the semiconductor cooler, the surface roughness Ra of the first substrate surface and / or the second cooler surface does not exceed 0.1 μm; and / or The substrate contains at least 96% AlN by mass; and / or The thermal conductivity of the substrate is not less than 180 W / m·K.

7. The thermal management component according to claim 1, characterized in that, It also includes a second bonding layer adapted to be bonded between the surface of the second cooler and the surface of the first substrate.

8. The thermal management component according to claim 7, characterized in that, The second bonding layer is adapted to bond with the thermoelectric cooler to form a bonding surface, wherein the area of ​​the bonding surface is in a 1:1 ratio to the area of ​​the thermoelectric cooler; and / or The thickness of the second bonding layer is 5 μm-10 μm; and / or The second bonding layer is a silver paste bonding layer, wherein the silver powder particle size in the silver paste bonding layer is less than or equal to 5 μm, and the thermal conductivity of the silver paste bonding layer is greater than 100 W / m·K.

9. The thermal management component according to claim 1, characterized in that, It also includes a micro heat pipe array, and the substrate is a thermally conductive substrate; The micro heat pipe array is connected to the second substrate surface of the substrate to connect the semiconductor cooler through the substrate for thermal conduction.

10. The thermal management component according to claim 9, characterized in that, The second substrate has multiple grooves on its surface.

11. The thermal management component according to claim 10, characterized in that, The depth of the trench ranges from 30 μm to 80 μm; and / or The thickness of the substrate is 0.2mm-0.5mm.

12. The thermal management component according to claim 9, characterized in that, The micro heat pipe array is welded to the substrate; A barrier layer is provided between the substrate and the micro heat pipe array, and the barrier layer surrounds the welding joint between the substrate and the micro heat pipe array.

13. The thermal management component according to claim 12, characterized in that, The micro heat pipe array is soldered to the substrate using Sn-Ag-Cu solder; and / or The barrier layer is a nickel layer.

14. The thermal management component according to claim 9, characterized in that, It also includes a packaging shell, in which the semiconductor switching device, the semiconductor cooler, the substrate and the micro heat pipe array are disposed along the first direction within the packaging shell.

15. The thermal management component according to claim 14, characterized in that, The encapsulation housing is a Kovar alloy housing; and / or The thickness of the encapsulation shell is 0.4mm-0.6mm; and / or The encapsulation shell is filled with an inert gas, the humidity of which does not exceed 5 ppm.

16. The thermal management component according to claim 14, characterized in that, The encapsulation shell contains multiple heat dissipation fins, which are thermally connected to the micro heat pipe array.

17. The thermal management component according to claim 16, characterized in that, The height of the heat dissipation fins ranges from 4mm to 6mm; and / or The distance between two adjacent fins ranges from 0.8 mm to 1.2 mm; and / or A heat-conducting layer is provided between the heat dissipation fins and the micro heat pipe array.

18. The thermal management component according to claim 14, characterized in that, A buffer layer is provided between the package housing and the semiconductor cooler, the substrate and the micro heat pipe array.

19. The thermal management component according to claim 18, characterized in that, The thickness of the buffer layer is 0.4mm-0.6mm.

20. The thermal management component according to claim 14, characterized in that, The package housing is provided with pads, and the electrodes of the semiconductor switching device are electrically connected to the pads; and / or The package housing is provided with pads, a second conductive layer electrically connected to the first conductive layer is provided at the edge of the surface of the first substrate, a third conductive layer is provided at the edge of the surface of the second cooler, the second conductive layer is electrically connected to the third conductive layer, and the first conductive layer is electrically connected to the pads.

21. The thermal management component according to claim 20, characterized in that, The widths of the second conductive layer and the third conductive layer range from 0.4 mm to 0.6 mm; and / or The second conductive layer and the third conductive layer are silver-plated layers.

22. The thermal management component according to claim 1, characterized in that, The semiconductor switching device has dimensions of 10mm × 10mm and a heat flux density of 100W / cm². 2 -200W / cm 2 .

23. A solid-state circuit breaker, characterized in that, include: Semiconductor switching devices and thermal management components as described in any one of claims 1-22.

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