A power over ethernet (POE) supporting gigabit ethernet port protection circuit

Abstract

The utility model relates to communication technical field, concretely is a kind of gigabit ethernet port protection circuit of supporting POE.The protection circuit includes: chip end signal preprocessing module, between chip end differential signal node and intermediate signal node, for realizing initial impedance matching of signal input;Dual resistance-capacitance isolation transmission module, between the intermediate signal node and network interface end differential signal node, including two levels resistance-capacitance coupling unit, for realizing direct current isolation, high-frequency signal transmission and noise filtering.The utility model constructs multilevel signal processing architecture between chip end and network interface end, with the collaborative design of signal preprocessing module, dual resistance-capacitance isolation transmission module, surge protection module and POE power coupling module to replace traditional network transformer, fundamentally solve the technical contradiction of high-density integration and low-cost implementation.

Description

Technical Field

[0001] This utility model relates to the field of communication technology, specifically to a Gigabit Ethernet port protection circuit that supports PoE. Background Technology

[0002] Traditional PoE (Power over Ethernet) implementations for Gigabit Ethernet ports rely on network transformers to construct signal isolation and power coupling structures. These transformers achieve electrical isolation between the chip and the network port through electromagnetic coupling, while simultaneously using a center tap to superimpose the PoE power signal. However, the core structure and winding design of network transformers result in large size and high cost, and they also suffer from magnetic losses and phase shifts during high-frequency signal transmission, making it difficult to meet the industry demands for high-density integration and low cost. Furthermore, traditional surge protection systems rely on the inherent isolation characteristics of transformers, but with increasingly stringent industrial electromagnetic compatibility requirements, single isolation devices are insufficient to handle complex transient overvoltage protection needs. There is an urgent need to develop integrated solutions that combine signal integrity assurance, surge protection capabilities, and efficient power coupling.

[0003] Based on the above background, the technical problem of this utility model is: how to achieve impedance matching, DC isolation, noise suppression and surge protection of gigabit Ethernet signals through circuit architecture innovation without abandoning the traditional network transformer, while meeting the requirements of collinear transmission and polarity-independent input of POE power supply, so as to break through the limitations of existing solutions in terms of cost, size and integration. Utility Model Content

[0004] This disclosure proposes a Gigabit Ethernet port protection circuit supporting PoE, with the aim of overcoming at least one of the deficiencies in the prior art.

[0005] To achieve the above objectives, the technical solution disclosed in this utility model is as follows:

[0006] According to one aspect of this disclosure, a Gigabit Ethernet port protection circuit supporting PoE is provided, the protection circuit comprising:

[0007] The chip-side signal preprocessing module is configured between the differential signal node and the intermediate signal node on the chip side to achieve initial impedance matching of the signal input.

[0008] A dual RC isolation transmission module is configured between the intermediate signal node and the differential signal node at the network port. It includes two stages of RC coupling units to achieve DC isolation, high-frequency signal transmission and noise filtering.

[0009] The surge protection module includes a first surge suppression unit connected in parallel between the intermediate signal nodes and a second surge suppression unit connected in parallel between the intermediate transmission nodes, used to clamp and protect the transient overvoltage at the chip end and the network port end.

[0010] The POE power coupling module is configured between the differential signal node at the network port and the POE power input node. It includes a common-mode inductor and a grounding filter unit to suppress common-mode noise and realize the coupling transmission of data signals and POE power signals.

[0011] Furthermore, the chip-side signal preprocessing module includes:

[0012] The positive signal node GPHY_MDIAP_P0 at the chip end is connected to the intermediate signal node GE_AP_TSP0 through the first matching resistor GPR3.

[0013] The negative signal node GPHY_MDIAN_P0 at the chip end is connected to the intermediate signal node GE_AN_TSP0 through the second matching resistor GPR7;

[0014] The first matching resistor GPR3 ​​and the second matching resistor GPR7 respectively constitute the positive and negative input impedance matching structures of the differential signal pair, which are used to suppress signal reflection and adjust the input impedance.

[0015] Furthermore, the first-stage coupling unit of the dual RC isolation transmission module includes:

[0016] Intermediate signal node GE_AP_TSP0 is connected to intermediate transmission node GE_AP_TMP0 through the first coupling capacitor GPC3, and intermediate signal node GE_AN_TSP0 is connected to intermediate transmission node GE_AN_TMP0 through the second coupling capacitor GPC19.

[0017] The first-stage coupling unit is used to block the DC component and allow Gigabit Ethernet high-frequency signals to pass through;

[0018] The second-stage filtering unit includes:

[0019] Intermediate transmission node GE_AP_TMP0 is connected to the positive signal node RJ45_AP_P0 at the network port through the third matching resistor GPR4 and the third coupling capacitor GPC10, and intermediate transmission node GE_AN_TMP0 is connected to the negative signal node RJ45_AN_P0 at the network port through the fourth matching resistor GPR8 and the fourth coupling capacitor GPC14.

[0020] The third matching resistor GPR4, the fourth matching resistor GPR8, the third coupling capacitor GPC10, and the fourth coupling capacitor GPC14 form a π-type filter network to suppress high-frequency noise during transmission.

[0021] Furthermore, the first surge suppression unit of the surge protection module is a bidirectional transient voltage suppression device GPTVS1, whose two ends are respectively connected to the intermediate signal nodes GE_AP_TSP0 and GE_AN_TMP0;

[0022] The second surge suppression unit is a bidirectional transient voltage suppression device GPTVS2, with its two ends connected to the intermediate transmission nodes GE_AP_TMP0 and GE_AN_TMP0, respectively.

[0023] The bidirectional transient voltage suppression devices GPTVS1 and GPTVS2 clamp transient overvoltages at the chip end and network port end, respectively, limiting the voltage amplitude to a safe range.

[0024] Furthermore, the PoE power coupling module includes:

[0025] The positive signal node RJ45_AP_P0 and the negative signal node RJ45_AN_P0 of the network port are respectively connected to the two winding input terminals of the common mode inductor PT1. The center tap of the common mode inductor PT1 is connected to the POE power input node CMCT1. The two winding output terminals are respectively connected to the system ground SGND through grounding capacitors GPC1 and GPC21.

[0026] The common-mode inductor PT1 is used to suppress common-mode noise, and the center tap CMCT1 is used to couple the POE power signal to achieve collinear transmission of data and power.

[0027] The ground terminal of the chip-side signal preprocessing module is connected in parallel with a first bypass capacitor GPC2 and a second bypass capacitor GPC18. The ground terminals of the intermediate transmission nodes GE_AP_TMP0 and GE_AN_TMP0 are connected in parallel with a third bypass capacitor GPC4, a fourth bypass capacitor GPC13, and a fifth bypass capacitor GPC17. The first matching resistor GPR3, the second matching resistor GPR7, the third matching resistor GPR4, the fourth matching resistor GPR8, the first bypass capacitor GPC2, the second bypass capacitor GPC18, the third bypass capacitor GPC4, the fourth bypass capacitor GPC13, and the fifth bypass capacitor GPC17 together form an impedance matching and common-mode noise filtering network, matching the characteristic impedance of the differential signal pair to a 100Ω standard Ethernet impedance.

[0028] Furthermore, the gigabit Ethernet port includes four differential signal pairs, namely PAIR A, PAIR B, PAIR C, and PAIR D;

[0029] Each differential signal pair protection circuit unit includes the chip-side signal preprocessing module, dual RC isolation transmission module, surge protection module, and POE power coupling module.

[0030] The network port signal nodes of each differential signal pair correspond to the T568B standard pin layout of the RJ45 interface. The center taps (CMCT1, CMCT2, CMCT3, CMCT4) of each common mode inductor are connected to the back-end Schottky diode rectifier bridge circuit. The rectifier bridge circuit consists of four Schottky diodes forming a bridge structure to realize the polarity conversion and current rectification of the PoE power supply to adapt to the power supply requirements of the Ethernet port.

[0031] The beneficial effects of this utility model are:

[0032] This invention fundamentally solves the technical contradiction between high-density integration and low-cost implementation by constructing a multi-level signal processing architecture between the chip end and the network port end, replacing the traditional network transformer with the collaborative design of a signal preprocessing module, a dual RC isolation transmission module, a surge protection module, and a POE power coupling module.

[0033] Specifically, the signal preprocessing module constructs a differential impedance matching structure and a common-mode noise filtering network at the chip level through a combination of matching resistors and bypass capacitors, ensuring phase consistency and noise suppression of gigabit signal input; the dual RC isolation transmission module utilizes two-stage RC coupling units to achieve DC component blocking and selective transmission of high-frequency signals, and its π-type filter network effectively attenuates out-of-band noise, avoiding signal distortion caused by traditional transformer magnetic losses; the two-stage surge protection structure forms graded clamping protection against electrostatic discharge, electrical fast transient pulse groups, and surge currents through the distributed deployment of bidirectional transient voltage suppression devices, significantly improving electromagnetic compatibility performance; the POE power coupling module utilizes the magnetic coupling characteristics of common-mode inductors to achieve collinear superposition of data signals and power signals, combined with the polarity conversion function of the back-end rectifier bridge circuit, ensuring the compatibility and stability of power input.

[0034] The synergistic effect of the technical solution of this utility model not only removes the bulky network transformer at the physical level, achieving a significant reduction in circuit cost and a significant improvement in integration, but also achieves or surpasses the level of traditional solutions in key performance indicators such as high-frequency signal integrity, transient overvoltage protection and power coupling efficiency through parameter matching and module cascading design, providing a new technical path for the miniaturization and low-cost design of high-density network equipment. Attached Figure Description

[0035] Figure 1 This is a schematic diagram of the differential signal interface on the 10 Gigabit Ethernet port chip side of this utility model;

[0036] Figure 2 This is a schematic diagram showing the pin definitions of the RJ45 interface differential signal and the T568B standard connection in this utility model;

[0037] Figure 3 This is a schematic diagram of the dual RC isolation and protection circuit for PAIRA differential signals in this utility model;

[0038] Figure 4 This is a schematic diagram of the dual RC isolation and protection circuit for PAIR B differential signals in this utility model;

[0039] Figure 5 This is a schematic diagram of the dual RC isolation and protection circuit for PAIR C differential signals in this utility model;

[0040] Figure 6 This is a schematic diagram of the dual RC isolation and protection circuit for PAIR D differential signals in this utility model;

[0041] Figure 7 The principle of the POE power rectifier bridge circuit in this utility model Figure 1 ;

[0042] Figure 8 The principle of the POE power rectifier bridge circuit in this utility model Figure 2 . Detailed Implementation

[0043] The technical solutions of the present utility model will be clearly and completely described below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are only some embodiments of the present utility model, not all embodiments. Based on the embodiments of the present utility model, all other embodiments obtained by those skilled in the art without creative effort are within the protection scope of the present utility model.

[0044] The term "comprising," and any variations thereof, used in the specification and claims of this application, is intended to cover a non-exclusive inclusion. For example, a process, method, system, product, or apparatus that includes a series of steps or units is not necessarily limited to those explicitly listed, but may include other steps or units not explicitly listed or inherent to such process, method, product, or apparatus. Furthermore, the use of "and / or" in the specification and claims indicates at least one of the connected objects, such as A and / or B, indicating the inclusion of A alone, B alone, or both A and B.

[0045] In this embodiment of the invention, the terms "exemplary" or "for example" are used to indicate that something is an example, illustration, or description. Any embodiment or design described as "exemplary" or "for example" in this embodiment of the invention should not be construed as being more preferred or advantageous than other embodiments or designs. Specifically, the use of the terms "exemplary" or "for example" is intended to present the relevant concepts in a specific manner.

[0046] like Figures 1 to 8 As shown, the present invention provides the following preferred embodiments:

[0047] Example 1

[0048] To address the issues of insufficient impedance matching accuracy, low surge protection layer coordination efficiency, and inadequate power coupling noise suppression in existing PoE-enabled Gigabit Ethernet port protection circuits during signal transmission, this embodiment provides a PoE-enabled Gigabit Ethernet port protection circuit. Through precise matching of component parameters and logical coordination design between modules, a full-link protection system covering signal transmission, isolation filtering, overvoltage protection, and power coupling is constructed.

[0049] Specifically, the chip-side signal preprocessing module is located between the differential signal nodes and intermediate signal nodes on the chip side. Its core function is to achieve initial impedance matching of the signal input. Specifically, the positive and negative signal nodes on the chip side are connected to their corresponding intermediate signal nodes via symmetrically arranged resistors. The resistance values ​​of the two resistors are configured according to the impedance requirements of Gigabit Ethernet differential signals, forming a differential matching network conforming to the IEEE 802.3 standard together with the chip's internal equivalent impedance. It is important to understand that the resistors use a symmetrical package design, combined with equal-length differential traces on the PCB. The trace width and spacing are set based on characteristic impedance simulation results to ensure phase consistency of the differential pair within the 1GHz frequency band, effectively suppressing signal reflection and transmission loss caused by impedance mismatch.

[0050] Furthermore, a dual RC isolation transmission module is configured between the intermediate signal node and the differential signal node at the network port, comprising two stages of RC coupling units to achieve functional layering. The first-stage coupling unit uses capacitors connected in series in the signal path, with capacitance parameters selected based on DC isolation requirements and high-frequency signal transmission characteristics. This effectively blocks the DC bias voltage between the chip and the network port, while maintaining low insertion loss for Gigabit Ethernet signals in the 10MHz to 2.5GHz frequency band, ensuring distortion-free signal transmission. The second-stage coupling unit consists of a filter network composed of resistors and capacitors. Resistors are connected in parallel between the signal node and the ground terminal, while capacitors are connected in series or parallel to form a filter characteristic with a specific cutoff frequency. This attenuates out-of-band noise higher than the signal bandwidth, improving the signal-to-noise ratio of the signal node. The two stages form a dual mechanism of DC isolation and noise filtering through cascading. The first stage focuses on DC blocking and signal coupling, while the second stage focuses on high-frequency noise suppression. Together, they reduce interference during signal transmission.

[0051] Furthermore, the surge protection module includes a first surge suppression unit connected in parallel between intermediate signal nodes and a second surge suppression unit connected in parallel between intermediate transmission nodes, forming a graded protection system for transient overvoltages of different energy levels. The first surge suppression unit mainly targets electrostatic discharge (ESD) and electrical fast transient / burst (EFT) interference that may occur at the chip end. Its clamping voltage parameter is set according to the chip's safe operating voltage range, enabling it to respond quickly and limit the overvoltage amplitude, preventing the chip from being impacted by transient energy. The second surge suppression unit is deployed at the network port signal path to absorb energy from externally introduced surge currents (such as 8 / 20μs waveform surge pulses). Its withstand power and clamping voltage are higher than the first-level unit to meet the higher energy level overvoltage protection requirements at the network port. The grounding loops of the two suppression units are connected to the main ground plane through independent paths, and high-frequency impedance elements are set between the two levels to form a gradient suppression path for energy dissipation, avoiding the reflection and superposition of overvoltages between protection levels and improving the overall surge protection effectiveness.

[0052] Furthermore, the PoE power coupling module is integrated between the differential signal node and the PoE power input node at the network port. Its core component, the common-mode inductor, adopts a magnetic core winding structure. The two ends of the winding are connected to the differential signal node at the network port and the subsequent transmission node, respectively, with the center tap connected to the PoE power input node. Through magnetic coupling, the 48V DC power signal is superimposed onto the differential data signal. The winding design of the common-mode inductor meets the requirements of dual-wire or multi-wire parallel winding processes to balance the common-mode noise suppression capability during differential signal transmission. Its inductance value and DC resistance parameters are optimized according to the power transmission requirements of the PoE power supply and the bandwidth characteristics of the data signal, ensuring a high common-mode noise rejection ratio in the frequency band below 100MHz, while reducing transmission loss for gigabit data signals. The grounding filter unit is connected in parallel between the network port grounding node and the system ground plane, containing resistors and capacitors. It is used to suppress ground loop noise and high-frequency oscillations generated during power coupling, forming a common-mode noise discharge path and ensuring efficient co-linear transmission of data signals and PoE power signals.

[0053] Furthermore, in the PCB layout design, the chip-side signal preprocessing module and the first surge suppression unit are positioned close to the chip pins to shorten the signal path and reduce parasitic inductance; the capacitors and resistors of the dual RC isolation transmission module are symmetrically arranged, and the differential traces are length-compensated to ensure consistent latency; the common-mode inductor and grounding filter unit of the PoE power coupling module are deployed close to the network port interface to reduce electromagnetic interference from power signals to the core transmission path. The ground plane of each module is covered with a complete copper foil, and multi-point grounding is achieved through via arrays to reduce the impact of grounding impedance on high-frequency signals.

[0054] The advantages of this embodiment are as follows: The symmetrical impedance matching design of the chip-side signal preprocessing module improves the transmission stability of differential signals at high frequencies; the hierarchical filtering mechanism of the dual RC isolation transmission module effectively combines DC isolation and noise suppression; the two-stage differentiated configuration of the surge protection module forms an energy gradient absorption system, enhancing protection against different types of transient interference; and the common-mode inductor and grounding filter unit of the PoE power coupling module work together to achieve low-loss superposition transmission of power and data signals. Through parameter optimization and physical layout coordination of each module, this protection circuit improves the electromagnetic compatibility performance and surge protection level of the system while ensuring the integrity of Gigabit Ethernet signals, providing an efficient hardware implementation solution for the reliable operation of industrial network equipment in complex electromagnetic environments.

[0055] Example 2

[0056] To address the signal reflection issue caused by impedance mismatch when gigabit Ethernet differential signals are input to the chip, this embodiment clarifies and optimizes the specific circuit structure of the chip-side signal preprocessing module. An initial impedance adjustment mechanism for differential signal input is constructed through symmetrically set matching resistors to ensure the integrity of signal transmission.

[0057] Furthermore, the positive signal node GPHY_MDIAP_P0 and the negative signal node GPHY_MDIAN_P0 on the chip side are connected to the corresponding intermediate signal nodes GE_AP_TSP0 and GE_AN_TSP0 respectively through the first matching resistor GPR3 ​​and the second matching resistor GPR7, forming independent transmission paths for the differential signal pair. The resistance values ​​of the first matching resistor GPR3 ​​and the second matching resistor GPR7 are set according to the matching requirements of the chip's output impedance and the characteristic impedance of the transmission line, typically ranging from 22Ω to 50Ω, to ensure that the overall input impedance of the differential pair meets the 100Ω ± 15% tolerance requirement specified in the IEEE 802.3 standard. It is important to understand that both resistors are surface-mount resistors of the same precision class, and their package size and parasitic parameters have been optimized for high-frequency characteristics to reduce the impact of their equivalent inductance and capacitance on gigabit signal transmission. In the PCB layout, GPR3 ​​and GPR7 are symmetrically distributed on both sides of the differential trace, and the trace length error is controlled within 5mil to avoid phase shift caused by path differences. At the same time, the two ends of the resistor are directly connected to the signal node through short wires to reduce the interference of solder joint parasitic inductance on impedance matching.

[0058] Furthermore, the grounding terminal of the chip-side signal preprocessing module is connected in parallel with a first bypass capacitor GPC2 and a second bypass capacitor GPC18. These two capacitors correspond to the grounding loops of the positive and negative signal nodes, respectively. The capacitance values ​​are selected from high-frequency ceramic capacitors in the range of 100nF to 1μF, used to filter out common-mode noise introduced by the chip's power supply, preventing noise from coupling to the transmission path through the signal nodes. At this time, the first matching resistor GPR3, the second matching resistor GPR7, and the bypass capacitors together form a high-frequency impedance compensation network, achieving dynamic impedance equalization in the 125MHz to 1GHz frequency band and suppressing reflection phenomena caused by changes in the chip's output impedance with frequency.

[0059] Furthermore, during signal transmission, the positive and negative signals of the differential pair undergo amplitude adjustment and impedance transformation via GPR3 ​​and GPR7, ensuring that the equivalent impedance looking from the intermediate signal nodes GE_AP_TSP0 and GE_AN_TSP0 towards the chip is consistent with the characteristic impedance of the subsequent transmission lines. This effectively controls the signal reflection coefficient below -20dB. It should be noted that the power rating of the matching resistors is selected based on the maximum drive voltage of the signal to ensure no thermal failure occurs during prolonged operation. Simultaneously, the temperature coefficient of the resistors is controlled within ±50ppm / ℃ to prevent impedance drift caused by ambient temperature changes from affecting matching accuracy.

[0060] The advantage of this embodiment lies in that, by clearly defining the specific connection relationship and parameter design principles of the first matching resistor GPR3 ​​and the second matching resistor GPR7, a precise impedance matching structure for differential signal input is constructed, effectively suppressing the impact of high-frequency signal reflection on transmission quality. The symmetrical layout and parameter consistency design ensure phase balance of the differential pair. Combined with the noise filtering effect of the grounding bypass capacitor, a complete preprocessing system for chip-side signal input is formed, providing stable input conditions for subsequent isolated signal transmission and noise suppression.

[0061] Example 3

[0062] To address the issues of DC bias interference and high-frequency noise coupling during gigabit Ethernet signal transmission, this embodiment refines the two-stage unit structure of the dual RC isolation transmission module. Through the cascaded design of capacitive coupling and π-type filter network, the functional layering of DC component blocking and specific frequency band noise suppression is achieved.

[0063] Furthermore, in the first-stage coupling unit of the dual RC isolation transmission module, the intermediate signal node GE_AP_TSP0 is connected to the intermediate transmission node GE_AP_TMP0 through the first coupling capacitor GPC3, and GE_AN_TSP0 is connected to GE_AN_TMP0 through the second coupling capacitor GPC19. GPC3 and GPC19 use film or ceramic capacitors with excellent high-frequency characteristics, typically with capacitance values ​​ranging from 1nF to 10nF. This capacitance range provides an equivalent impedance of less than 1Ω at 100MHz, ensuring low-loss transmission of gigabit signals (maximum transmission frequency approximately 125MHz), while simultaneously creating a circuit to the DC component, blocking the DC potential difference between the chip and the network port, and preventing bias interference from potential differences between different ground planes. It is important to understand that the withstand voltage of the two capacitors is selected based on the highest DC voltage the system may withstand, typically not less than 60V to adapt to the voltage requirements of PoE power supply scenarios.

[0064] Furthermore, the second-stage filtering unit consists of a π-type network formed by the third matching resistor GPR4, the fourth matching resistor GPR8, the third coupling capacitor GPC10, and the fourth coupling capacitor GPC14. GPR4 is connected in series between GE_AP_TMP0 and the positive signal node RJ45_AP_P0 at the network port. GPC10 is connected in parallel between RJ45_AP_P0 and the ground terminal. GPR8 and GPC14 are symmetrically connected to the negative signal path. The cutoff frequency of this π-type structure is designed through a combination of resistor and capacitor values. For example, when GPR4 = 33Ω and GPC10 = 47pF, the cutoff frequency is approximately 100MHz, capable of attenuating noise above 200MHz with a bandwidth exceeding gigabit signals, achieving an attenuation slope of -20dB / decade. GPR4 and GPR8 also perform impedance fine-tuning of the signal path, working in conjunction with the preceding and following stage capacitors and the characteristic impedance of the transmission line to ensure impedance continuity throughout the entire transmission link.

[0065] Furthermore, in the signal transmission path, the first-stage coupling unit first isolates the DC component to prevent high-voltage DC at the network port from damaging the chip through the signal path, while providing a coupling channel for high-frequency signals. The second-stage π-type filter unit filters out common-mode noise and high-frequency harmonics coupled after long-distance transmission, especially suppressing the third and higher harmonic components in the Ethernet signal caused by electromagnetic coupling. It should be noted that the GPC10 and GPC14 are installed close to the signal node at the network port, connecting to the ground plane with the shortest path to reduce the impact of ground loop inductance on the filtering effect. The GPR4 and GPR8 use low ESR (equivalent series resistance) chip resistors to avoid excessive attenuation of signal amplitude due to their own losses.

[0066] Furthermore, the component layout of the two-level units follows the principle of differential symmetry. GPC3 and GPC19, GPR4 and GPR8, and GPC10 and GPC14 are all placed mirror images of each other with the differential center line as the axis of symmetry. Differential traces maintain equal length and spacing when passing through capacitors and resistors to avoid signal distortion caused by differences in parasitic parameters. This hierarchical processing mechanism allows DC isolation and noise filtering functions to be implemented by different units, avoiding performance trade-offs caused by a single unit undertaking multiple functions, and improving the purity of signal transmission.

[0067] The advantage of this embodiment lies in the fact that a functionally defined two-stage signal processing system is formed by combining the DC blocking characteristics of the first-stage coupling capacitor with the high-frequency noise suppression characteristics of the second-stage π-type filter network. The parameter combination and layout design of the capacitors and resistors ensure low-loss transmission of gigabit signals while effectively suppressing interference from DC bias and out-of-band noise.

[0068] Example 4

[0069] To address the issue of Gigabit Ethernet ports being susceptible to transient overvoltage surges in complex electromagnetic environments, this embodiment defines the structure of the two-stage suppression unit of the surge protection module. By deploying bidirectional transient voltage suppressor devices (TVS) in a differentiated manner, a gradient overvoltage protection system is constructed for both the chip and the network port.

[0070] Furthermore, the first surge suppression unit of the surge protection module is a bidirectional TVS device, GPTVS1, whose two ends are connected to the intermediate signal nodes GE_AP_TSP0 and GE_AN_TMP0 respectively, i.e., bridging the differential signal pairs output by the chip-side preprocessing module. The clamping voltage parameter of GPTVS1 is set according to the chip's safe operating voltage, typically 1.2 times the withstand voltage of the chip's I / O port. For example, when the chip port withstand voltage is 5V, a device with a clamping voltage ≤6V is selected to ensure that the overvoltage amplitude is limited within the chip's tolerance range during electrostatic discharge (ESD) or electrical fast transient (EFT) interference. The device has a response time of less than 1ns, enabling it to quickly conduct and absorb nanosecond-level transient energy. Its parasitic capacitance is controlled below 5pF to avoid affecting the phase characteristics of gigabit signals.

[0071] Furthermore, the second surge suppression unit is a bidirectional TVS device, GPTVS2, connected between the intermediate transmission nodes GE_AP_TMP0 and GE_AN_TMP0, i.e., located between the two levels of the dual RC isolation transmission module. Compared to GPTVS1, GPTVS2 has a higher clamping voltage and peak pulse power. For example, a device with a clamping voltage ≤30V and a peak power ≥400W is selected to cope with lightning surges that may be introduced at the network port (such as surge pulses with an 8 / 20μs waveform and a peak voltage of 2kV). This hierarchical design allows GPTVS1 to mainly handle low-energy transient interference generated locally at the chip end, while GPTVS2 undertakes the initial clamping of external high-energy surges. The clamping voltages of the two levels of devices form a gradient protection range of 5V to 30V, preventing overvoltage energy from directly acting on the chip port.

[0072] Furthermore, during the overvoltage response, GPTVS1 and GPTVS2, through their bidirectional conductivity, can quickly clamp transient voltages of both positive and negative polarities. Their grounding pins are connected to the main grounding plane through independent grounding vias, and the difference in grounding path length between the two devices is controlled within 2mm to ensure the synchronization of the discharge current. It is important to understand that the signal path impedance between the two TVS devices (i.e., the line impedance between intermediate transmission nodes) is designed to be greater than 50Ω, so that overvoltage energy is preferentially discharged through the TVS rather than coupled to the downstream circuit, while avoiding mutual interference between the two devices when they are turned on.

[0073] Furthermore, considering the sensitivity of high-frequency signal transmission to parasitic parameters of the line, both GPTVS1 and GPTVS2 adopt surface-mount SMD packages with pin lengths trimmed to less than 2mm to reduce the impact of equivalent inductance on clamping speed. In the PCB layout, the two devices are placed adjacent to their corresponding signal nodes, forming a protective link of "chip-side preprocessing module—first TVS—RC isolation unit—second TVS—network port," ensuring that transient energy is attenuated step by step before entering the core transmission path.

[0074] The advantage of this embodiment lies in achieving layered protection against transient overvoltages of different energy levels through the targeted configuration of two-stage bidirectional TVS devices. The differentiated clamping voltage and power capacity design effectively isolates overvoltage threats at the chip end and the network port end. Parasitic parameter control and grounding design ensure that the protection mechanism has a low impact on high-frequency signal transmission, thereby significantly improving the surge immunity of the Ethernet port without sacrificing signal integrity.

[0075] Example 5

[0076] To address the common-mode noise coupling and impedance mismatch issues when PoE power signals and gigabit data signals are transmitted on the same line, this embodiment refines the circuit structure of the PoE power coupling module. Through the coordinated design of common-mode inductors and grounding capacitors, combined with the chip-side bypass capacitor network, a highly efficient coupling and transmission system for signals and power is constructed.

[0077] In the PoE power coupling module, the positive signal node RJ45_AP_P0 and negative signal node RJ45_AN_P0 on the network port are connected to the two winding input terminals of the common-mode inductor PT1, respectively. PT1 adopts a dual-wire parallel-wound toroidal core structure. The center tap CMCT1 is connected to the PoE power input node, and the two winding output terminals are connected to system ground SGND through grounding capacitors GPC1 and GPC21, respectively. The winding inductance of the common-mode inductor is typically 10μH to 30μH, and its DC resistance is controlled below 50mΩ to reduce the transmission loss of PoE power. At the same time, its impedance to common-mode noise is ≥1kΩ at 100MHz, effectively suppressing common-mode interference in the power signal. The design of the center tap CMCT1 allows the 48V DC power supply to be superimposed on the differential data signal through magnetic coupling. Utilizing the characteristics of the common-mode inductor—low impedance to differential signals and high impedance to common-mode signals—bidirectional interference-free transmission of power and data is achieved.

[0078] The ground terminal of the chip-side signal preprocessing module is connected in parallel with the first bypass capacitor GPC2 and the second bypass capacitor GPC18. The ground terminal of the intermediate transmission node is connected in parallel with the third bypass capacitor GPC4, the fourth bypass capacitor GPC13, and the fifth bypass capacitor GPC17. These capacitors, together with the first matching resistor GPR3, the second matching resistor GPR7, the third matching resistor GPR4, and the fourth matching resistor GPR8, form an impedance matching network. Specifically, GPC2 and GPC18 (10nF capacitance) bypass high-frequency noise at the chip side, while GPC4, GPC13, and GPC17 (47pF to 100pF capacitance) compensate for the parasitic inductance of the intermediate node. By adjusting the resistance values ​​(e.g., GPR3 ​​= 22Ω, GPR4 = 33Ω) and coordinating with the capacitive reactance of the capacitors, the characteristic impedance of the differential signal pair is precisely matched to the 100Ω standard value, with the error controlled within ±5%.

[0079] During the co-linear transmission of signal and power, the common-mode inductor PT1 not only suppresses common-mode noise introduced by the PoE power supply (such as switching power supply ripple), but also avoids interference from common-mode components in the data signal to the power system. Grounding capacitors GPC1 and GPC21 (1nF capacitance) serve as discharge paths for common-mode noise, with their equivalent series inductance (ESL) controlled below 5nH to ensure high-frequency noise can be quickly conducted to the ground plane. It is important to understand that the common-mode inductor's core material is made of ferrite with low high-frequency loss to prevent core saturation from distorting data signal transmission. Simultaneously, the center tap's solder joint is treated with anti-oxidation to ensure reliable PoE power supply connection.

[0080] Furthermore, the component layout of the impedance matching network follows the principle of "nearby grounding and symmetrical distribution." Bypass capacitors are placed close to the corresponding signal nodes and ground planes to reduce noise coupling paths. The common-mode inductor PT1 is placed near the RJ45 interface at the network port, shortening the distance between the power input node and the coupling point and reducing the impact of line impedance on power transmission efficiency. This integrated design ensures that the differential-mode loss of data signals passing through the common-mode inductor is less than 0.5dB, while the transmission efficiency of the PoE power supply remains above 95%.

[0081] The advantage of this embodiment lies in achieving efficient collinear transmission of data signals and PoE power through the magnetic coupling characteristics of the common-mode inductor. The grounding capacitor and bypass capacitor network, combined with the matching resistor, ensure impedance consistency and common-mode noise suppression throughout the entire link. Precise design and optimized layout of component parameters effectively solve the problems of noise interference and impedance mismatch during power coupling without increasing circuit complexity, providing a reliable hardware implementation solution for the PoE function of the Gigabit Ethernet port.

[0082] Example 6

[0083] To address compatibility issues and PoE power polarity adaptation problems during parallel transmission of multiple differential signal pairs on Gigabit Ethernet ports, this embodiment expands the overall architecture of the Ethernet port, clarifies the protection circuit configuration for the four differential signal pairs and the back-end processing mechanism for PoE power, ensuring interface specifications and power supply compatibility in accordance with the T568B standard.

[0084] The Gigabit Ethernet port includes four differential signal pairs: PAIR A, PAIR B, PAIR C, and PAIR D, corresponding to the T568B standard pins of the RJ45 interface: PAIR A connects to pins 1 and 2 (transmit positive / negative), PAIR B connects to pins 3 and 6 (receive positive / negative), PAIR C connects to pins 4 and 5 (reserved), and PAIR D connects to pins 7 and 8 (reserved). Each differential signal pair is independently configured with a chip-side signal preprocessing module, a dual RC isolation transmission module, a surge protection module, and a PoE power coupling module, forming four parallel protection circuit units. It is important to understand that the structure and component parameters of each protection circuit are consistent to ensure consistent signal transmission characteristics. Furthermore, the network port signal nodes of each pair strictly adhere to the T568B pin definitions to avoid communication failures caused by incorrect wiring.

[0085] The center taps (CMCT1, CMCT2, CMCT3, CMCT4) of the common-mode inductors for each differential signal pair are connected to the downstream Schottky diode rectifier bridge circuit. This rectifier bridge consists of four Schottky diodes forming a bridge structure. When selecting the diodes, their forward voltage drop (≤0.5V) and reverse withstand voltage (≥60V) characteristics are considered to adapt to the 48V input of the PoE power supply. The function of the rectifier bridge is to realize the polarity conversion of the PoE power supply. Regardless of the positive or negative polarity of the input power supply, it can be converted into a DC voltage of uniform polarity through the bridge structure for use by subsequent circuits. For example, when the polarity of the power supply input to the center tap of the common-mode inductor is CMCT1 positive and CMCT2 negative, the rectifier bridge adjusts the output to a fixed polarity through the unidirectional conduction characteristic of the diodes, avoiding the impact of uncertain polarity during network cable connection on the power supply to the device.

[0086] In the hardware implementation, the protection circuit units for the four differential signal pairs are arranged in an array on the PCB. The differential traces of each group are kept to be of equal length and spacing to avoid crosstalk between groups. The pin pads of the RJ45 interface are connected to the corresponding signal nodes with short stubs to reduce parasitic inductance in the signal path. The Schottky diode rectifier bridge is deployed close to the center tap of the common-mode inductor to shorten the power input path and reduce voltage drop caused by line impedance. At the same time, the heat dissipation pads of the diodes are connected to the PCB ground plane to improve heat dissipation in high-current scenarios.

[0087] Furthermore, considering that PAIR A and PAIR B in the four differential signal pairs bear the main data transmission function, the component parameters of their protection circuits can be optimized according to the requirements of high-speed signal transmission. For example, coupling capacitors and TVS devices with smaller parasitic capacitance can be selected, while the protection units of PAIR C and PAIR D can use general-purpose components, reducing costs while ensuring protection performance. A ferrite bead or inductor is connected in series between the input node of the PoE power supply and the output terminal of the rectifier bridge to form a power supply filter circuit, suppressing the interference of high-frequency noise generated during rectification on the data signal.

[0088] The advantages of this embodiment are that the standardized configuration of four differential signal pairs and the strict adaptation to the T568B pin layout ensure the compatibility and interchangeability of the Ethernet port; the introduction of the Schottky diode rectifier bridge solves the polarity uncertainty problem of the PoE power supply, improving the reliability of the device power supply. The parallel design and layout optimization of each protection circuit effectively controls the electromagnetic compatibility of the circuit while achieving full signal pair protection, providing a standardized hardware architecture for the application of industrial-grade Ethernet devices in multiple scenarios.

[0089] Although the present invention has been specifically described above with reference to preferred embodiments, it should be understood that the present invention is not limited to the embodiments described above. Rather, various modifications and variations can be made by those skilled in the art without departing from the essence of the present invention, and such modifications and variations should fall within the scope defined by the appended claims and their equivalents.

Claims

1. A Gigabit Ethernet port protection circuit supporting PoE, characterized in that, The protection circuit includes: The chip-side signal preprocessing module is configured between the differential signal node and the intermediate signal node on the chip side to achieve initial impedance matching of the signal input. A dual RC isolation transmission module is configured between the intermediate signal node and the differential signal node at the network port. It includes two stages of RC coupling units to achieve DC isolation, high-frequency signal transmission and noise filtering. The surge protection module includes a first surge suppression unit connected in parallel between the intermediate signal nodes and a second surge suppression unit connected in parallel between the intermediate transmission nodes, used to clamp and protect the transient overvoltage at the chip end and the network port end. The POE power coupling module is configured between the differential signal node at the network port and the POE power input node. It includes a common-mode inductor and a grounding filter unit to suppress common-mode noise and realize the coupling transmission of data signals and POE power signals.

2. The Gigabit Ethernet port protection circuit supporting PoE as described in claim 1, characterized in that, The chip-side signal preprocessing module includes: The positive signal node GPHY_MDIAP_P0 at the chip end is connected to the intermediate signal node GE_AP_TSP0 through the first matching resistor GPR3. The negative signal node GPHY_MDIAN_P0 at the chip end is connected to the intermediate signal node GE_AN_TSP0 through the second matching resistor GPR7; The first matching resistor GPR3 ​​and the second matching resistor GPR7 respectively constitute the positive and negative input impedance matching structures of the differential signal pair, which are used to suppress signal reflection and adjust the input impedance.

3. The Gigabit Ethernet port protection circuit supporting PoE as described in claim 1, characterized in that, The first-stage coupling unit of the dual RC isolation transmission module includes: Intermediate signal node GE_AP_TSP0 is connected to intermediate transmission node GE_AP_TMP0 through the first coupling capacitor GPC3, and intermediate signal node GE_AN_TSP0 is connected to intermediate transmission node GE_AN_TMP0 through the second coupling capacitor GPC19. The first-stage coupling unit is used to block the DC component and allow Gigabit Ethernet high-frequency signals to pass through; The second-stage filtering unit includes: Intermediate transmission node GE_AP_TMP0 is connected to the positive signal node RJ45_AP_P0 at the network port through the third matching resistor GPR4 and the third coupling capacitor GPC10, and intermediate transmission node GE_AN_TMP0 is connected to the negative signal node RJ45_AN_P0 at the network port through the fourth matching resistor GPR8 and the fourth coupling capacitor GPC14. The third matching resistor GPR4, the fourth matching resistor GPR8, the third coupling capacitor GPC10, and the fourth coupling capacitor GPC14 form a π-type filter network to suppress high-frequency noise during transmission.

4. The Gigabit Ethernet port protection circuit supporting PoE as described in claim 1, characterized in that, The first surge suppression unit of the surge protection module is a bidirectional transient voltage suppression device GPTTS1, whose two ends are respectively connected to the intermediate signal nodes GE_AP_TSP0 and GE_AN_TMP0. The second surge suppression unit is a bidirectional transient voltage suppression device GPTVS2, with its two ends connected to the intermediate transmission nodes GE_AP_TMP0 and GE_AN_TMP0, respectively. The bidirectional transient voltage suppression devices GPTVS1 and GPTVS2 clamp transient overvoltages at the chip end and network port end, respectively, limiting the voltage amplitude to a safe range.

5. The Gigabit Ethernet port protection circuit supporting PoE as described in claim 1, characterized in that, The PoE power coupling module includes: The positive signal node RJ45_AP_P0 and the negative signal node RJ45_AN_P0 of the network port are respectively connected to the two winding input terminals of the common mode inductor PT1. The center tap of the common mode inductor PT1 is connected to the POE power input node CMCT1. The two winding output terminals are respectively connected to the system ground SGND through grounding capacitors GPC1 and GPC21. The common-mode inductor PT1 is used to suppress common-mode noise, and the center tap CMCT1 is used to couple the POE power signal to achieve collinear transmission of data and power. The ground terminal of the chip-side signal preprocessing module is connected in parallel with a first bypass capacitor GPC2 and a second bypass capacitor GPC18. The ground terminals of the intermediate transmission nodes GE_AP_TMP0 and GE_AN_TMP0 are connected in parallel with a third bypass capacitor GPC4, a fourth bypass capacitor GPC13, and a fifth bypass capacitor GPC17. The first matching resistor GPR3, the second matching resistor GPR7, the third matching resistor GPR4, the fourth matching resistor GPR8, the first bypass capacitor GPC2, the second bypass capacitor GPC18, the third bypass capacitor GPC4, the fourth bypass capacitor GPC13, and the fifth bypass capacitor GPC17 together form an impedance matching and common-mode noise filtering network, matching the characteristic impedance of the differential signal pair to a 100Ω standard Ethernet impedance.

6. The Gigabit Ethernet port protection circuit supporting PoE as described in claim 1, characterized in that, The gigabit Ethernet port contains four differential signal pairs, namely PAIR A, PAIR B, PAIR C, and PAIR D; Each differential signal pair protection circuit unit includes the chip-side signal preprocessing module, dual RC isolation transmission module, surge protection module, and POE power coupling module. The network port signal nodes of each differential signal pair correspond to the T568B standard pin layout of the RJ45 interface. The center taps (CMCT1, CMCT2, CMCT3, CMCT4) of each common mode inductor are connected to the back-end Schottky diode rectifier bridge circuit. The rectifier bridge circuit consists of four Schottky diodes forming a bridge structure to realize the polarity conversion and current rectification of the PoE power supply to adapt to the power supply requirements of the Ethernet port.

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