Gigabit ethernet port protection circuit

Abstract

The utility model relates to communication field, concretely is a kind of 10-gigabit ethernet port protection circuit.The protection circuit includes: chip end signal preprocessing module, between chip end differential signal node (10GPHY_MD IAP_P0, 10GPHY_MD IAN_P0) and intermediate signal node (10GE_AP_TSP0, 10GE_AN_TSP0) are configured, for realizing initial impedance matching of signal input.The utility model constructs integrated chip end signal preprocessing, double resistance-capacitance isolation transmission, hierarchical surge protection and the synergic processing framework of POE power coupling, and systematically solves the core technical problem in 10-gigabit ethernet signal transmission.

Description

Technical Field

[0001] This utility model relates to the field of communications, specifically a 10 Gigabit Ethernet port protection circuit. Background Technology

[0002] In 10 Gigabit Ethernet signal transmission systems, signal processing circuits must simultaneously meet multiple technical requirements, including maintaining high-frequency signal integrity, suppressing complex noise, protecting against transient overvoltages, and enabling PoE (Power over Ethernet) power supply co-line transmission. However, existing 10 Gigabit Ethernet port signal processing solutions suffer from technical bottlenecks: insufficient impedance matching accuracy between the chip and port ends for high-frequency differential signals leads to increased signal reflection and attenuation; traditional single-stage RC coupling circuits struggle to effectively filter out high-frequency noise above 200MHz while blocking DC, affecting signal purity; the layout and selection of surge protection devices fail to provide graded protection based on the different interference characteristics at the chip and port ends, easily leading to clamping failures or the introduction of new noise by parasitic parameters; and in the co-line transmission of PoE power and 10 Gigabit data signals, the coupling efficiency and impedance matching of common-mode inductors are insufficient, causing power supply noise to crosstalk high-speed signals. Especially in scenarios with parallel transmission of four differential signal pairs, the design deficiencies of the functional modules become even more pronounced, making it difficult to meet the stringent requirements of the IEEE 802.3bz standard for 10 Gigabit Ethernet signal integrity and electromagnetic compatibility. Therefore, how to construct a multi-module collaborative optimization signal processing architecture to achieve high-precision impedance matching, efficient noise filtering, graded surge protection, and reliable PoE power coupling has become a technical challenge for improving the stability of 10 Gigabit Ethernet ports. Utility Model Content

[0003] This disclosure presents a 10 Gigabit Ethernet port protection circuit, which aims to overcome at least one of the defects existing in the prior art.

[0004] To achieve the above objectives, the technical solution disclosed in this utility model is as follows:

[0005] According to one aspect of this disclosure, a 10 Gigabit Ethernet port protection circuit is provided, the protection circuit comprising:

[0006] The chip-side signal preprocessing module is configured between the chip-side differential signal nodes (10GPHY_MDIAP_P0, 10GPHY_MDIAN_P0) and the intermediate signal nodes (10GE_AP_TSP0, 10GE_AN_TSP0) to achieve initial impedance matching of the signal input.

[0007] A dual RC isolation transmission module is configured between the intermediate signal nodes (10GE_AP_TSP0, 10GE_AN_TSP0) and the differential signal nodes at the network port (RJ45_AP_P0, RJ45_AN_P0), including two stages of RC coupling units, for realizing DC isolation, 10 Gigabit high-frequency signal transmission and noise filtering;

[0008] The surge protection module includes a first surge suppression unit connected in parallel between the intermediate signal nodes and a second surge suppression unit connected in parallel between the intermediate transmission nodes, used to clamp and protect the transient overvoltage at the chip end and the network port end.

[0009] The POE power coupling module is configured between the differential signal nodes (RJ45_AP_P0, RJ45_AN_P0) at the network port and the POE power input node (CT1). It includes a common-mode inductor and a grounding filter unit to suppress common-mode noise and realize the coupling transmission of data signals and POE power signals.

[0010] Furthermore, the chip-side signal preprocessing module includes:

[0011] The chip-side positive signal node 10GPHY_MDIAP_P0 is connected to the intermediate positive signal node 10GE_AP_TSP0 through the matching resistor 10GPR3;

[0012] The negative signal node 10GPHY_MDIAN_P0 at the chip end is connected to the intermediate negative signal node 10GE_AN_TSP0 through the matching resistor 10GPR7;

[0013] The ground terminal of the chip-side signal preprocessing module is connected in parallel with bypass capacitors 10GPC15 and 10GPC32. The intermediate transmission node 10GE_AP_TMP0 is grounded (GND) through bypass capacitor 10GPC17, and 10GE_AN_TMP0 is grounded (GND) through the fourth bypass capacitor 10GPC33. The matching resistors (10GPR3, 10GPR7, 10GPR4, 10GPR8) and the bypass capacitors (10GPC15, 10GPC32, 10GPC17, 10GPC33) together form an impedance compensation network to ensure that the characteristic impedance of the differential signal pair is accurately matched to the 100Ω standard.

[0014] Furthermore, the dual RC isolation transmission module includes:

[0015] First-stage RC coupling unit:

[0016] The intermediate positive signal node 10GE_AP_TSP0 is connected to the intermediate positive transmission node 10GE_AP_TMP0 through the first coupling capacitor 10GPC22, and the intermediate negative signal node 10GE_AN_TSP0 is connected to the intermediate negative transmission node 10GE_AN_TMP0 through the second coupling capacitor 10GPC26, which is used to block the DC component and allow the 10Gbps high-frequency signal to pass through.

[0017] Second-stage RC filter unit:

[0018] The intermediate positive transmission node 10GE_AP_TMP0 is connected to the positive signal node RJ45_AP_P0 at the network port through the third matching resistor 10GPR4 and the third coupling capacitor 10GPC23. The intermediate negative transmission node 10GE_AN_TMP0 is connected to the negative signal node RJ45_AN_P0 at the network port through the fourth matching resistor 10GPR8 and the fourth coupling capacitor 10GPC27. The third matching resistor 10GPR4, the fourth matching resistor 10GPR8, the third coupling capacitor 10GPC23, and the fourth coupling capacitor 10GPC27 form a π-type filter network to suppress common-mode and differential-mode noise during transmission.

[0019] Furthermore, the surge protection module includes:

[0020] The first surge suppression unit is a bidirectional transient voltage suppression device 10GTVS1, with its two ends connected to the intermediate positive signal node 10GE_AP_TSP0 and the intermediate negative signal node 10GE_AN_TSP0, respectively, to clamp transient common-mode overvoltage at the chip end;

[0021] The second surge suppression unit is a bidirectional transient voltage suppression device 10GTVS2, with its two ends connected to the intermediate positive transmission node 10GE_AP_TMP0 and the intermediate negative transmission node 10GE_AN_TMP0, respectively, to clamp transient differential mode overvoltage at the network port.

[0022] The bidirectional transient voltage suppression devices 10GTVS1 and 10GTVS2 limit the voltage amplitude within the safe operating range of the devices to meet the surge protection requirements of the IEEE 802.3bz standard.

[0023] Furthermore, the PoE power coupling module includes:

[0024] The two winding input terminals of the common mode inductor T1 are connected to the positive signal node RJ45_AP_P0 and the negative signal node RJ45_AN_P0 of the network port, respectively;

[0025] The center tap of the common mode inductor T1 is connected to the POE power input node CT1 for coupling the POE power signal;

[0026] The output terminals of the two windings are connected to signal ground SGND through grounding capacitors 10GPC14 and 10GPC34 respectively, to filter out high-frequency noise in the power supply path.

[0027] The common-mode inductor T1 suppresses common-mode interference and enables the co-line transmission of 10 Gigabit data signals and PoE power signals.

[0028] Furthermore, the 10 Gigabit Ethernet port includes four differential signal pairs PAIR A, PAIR B, PAIR C, and PAIR D. Each protection circuit unit includes a chip-side signal preprocessing module, a dual RC isolation transmission module, a surge protection module, and a POE power coupling module.

[0029] The network port signal nodes of each differential signal pair correspond to the standard pin layout of the RJ45 interface T568B, where PAIRA corresponds to pins 1 / 2, PAIR B corresponds to pins 3 / 6, PAIR C corresponds to pins 4 / 5, and PAIR D corresponds to pins 7 / 8.

[0030] In the chip-side signal preprocessing module, the chip-side differential signal nodes are connected to the intermediate signal nodes through matching resistors, and together with the grounding bypass capacitor, they form a differential impedance matching network.

[0031] The dual RC isolation transmission module includes two stages of RC units. The first stage coupling capacitor connects the intermediate signal node and the intermediate transmission node to block DC and pass high-frequency signals. The second stage consists of a matching resistor and a coupling capacitor forming a filter network to suppress common-mode and differential-mode noise.

[0032] In the surge protection module, bidirectional transient voltage suppression devices are connected in parallel between intermediate signal nodes and intermediate transmission nodes to clamp transient overvoltages between the chip end and the network port end.

[0033] In the POE power coupling module, the input terminals of each group of common-mode inductors are connected to the network port signal nodes, the center tap is connected to the front-end π-type power filter network composed of inductors and parallel capacitors, and the winding output terminals are filtered out by grounding capacitors to achieve collinear transmission of data signals and POE power; the circuit structures of the four differential signal pairs are consistent.

[0034] The beneficial effects of this utility model are:

[0035] This invention systematically solves the core technical problems in 10 Gigabit Ethernet signal transmission by constructing a collaborative processing architecture that integrates chip-side signal preprocessing, dual RC isolation transmission, graded surge protection, and POE power coupling. Specifically, the chip-side signal preprocessing module uses an impedance compensation network composed of matching resistors and bypass capacitors to precisely control the characteristic impedance of the differential signal pair to the 100Ω standard, effectively suppressing signal reflection and attenuation and improving the integrity of high-frequency signal transmission. The dual RC isolation transmission module adopts a two-stage RC unit design. The first-stage coupling capacitor blocks the DC component and provides a low-impedance path for the 10Gbps signal, while the second-stage π-type filter network effectively attenuates noise above 200MHz, achieving an organic unity of DC isolation and broadband noise suppression. The surge protection module sets bidirectional transient voltage suppression devices with different parameters between intermediate signal nodes and intermediate transmission nodes to perform graded clamping on local interference at the chip end and high-energy surges introduced at the network port end, meeting the IEEE 802.3bz standard while avoiding the influence of parasitic parameters on the signal. The POE power coupling module utilizes the common-mode noise suppression characteristics of common-mode inductors and a center-tap coupling design to achieve interference-free co-line transmission of 48V DC power and 10G data signals. The grounding capacitor further filters out high-frequency noise in the power path, ensuring the stability of bidirectional power and signal transmission. The modular design of the four differential signal pairs strictly follows the RJ45 interface T568B standard. Through the coordinated optimization of node layout and component parameters, a 10 Gigabit Ethernet signal processing solution with high-precision impedance matching, wideband noise suppression, graded surge protection and efficient PoE coupling capability is finally formed, which significantly improves the signal integrity, electromagnetic compatibility and long-term operational reliability of the high-speed communication system.

[0036] The above description is only an overview of the technical solution of this utility model. In order to better understand the technical means of this utility model and to implement it in accordance with the contents of the specification, the preferred embodiments of this utility model are described in detail below with reference to the accompanying drawings. Attached Figure Description

[0037] Figure 1 This is a flowchart of the method for implementing a 10 Gigabit Ethernet port supporting PoE in this utility model;

[0038] Figure 2 This is a schematic diagram of the differential signal interface on the 10 Gigabit Ethernet port chip side of this utility model;

[0039] Figure 3 This is a schematic diagram showing the pin definitions of the RJ45 interface differential signal and the T568B standard connection in this utility model;

[0040] Figure 4 This is a schematic diagram of the filtering and common-mode rejection circuit of the POE power conversion module in this utility model;

[0041] Figure 5 This is a schematic diagram of the dual RC isolation and protection circuit for PAIR A differential signals in this utility model;

[0042] Figure 6 This is a schematic diagram of the dual RC isolation and protection circuit for PAIR B differential signals in this utility model;

[0043] Figure 7 This is a schematic diagram of the dual RC isolation and protection circuit for PAIR C differential signals in this utility model;

[0044] Figure 8 This is a schematic diagram of the dual RC isolation and protection circuit for PAIR D differential signals in this utility model. Detailed Implementation

[0045] The technical solutions of the present utility model will be clearly and completely described below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are only some embodiments of the present utility model, not all embodiments. Based on the embodiments of the present utility model, all other embodiments obtained by those skilled in the art without creative effort are within the protection scope of the present utility model.

[0046] The term "comprising," and any variations thereof, used in the specification and claims of this application, is intended to cover a non-exclusive inclusion. For example, a process, method, system, product, or apparatus that includes a series of steps or units is not necessarily limited to those explicitly listed, but may include other steps or units not explicitly listed or inherent to such process, method, product, or apparatus. Furthermore, the use of "and / or" in the specification and claims indicates at least one of the connected objects, such as A and / or B, indicating the inclusion of A alone, B alone, or both A and B.

[0047] In this embodiment of the invention, the terms "exemplary" or "for example" are used to indicate that something is an example, illustration, or description. Any embodiment or design described as "exemplary" or "for example" in this embodiment of the invention should not be construed as being more preferred or advantageous than other embodiments or designs. Specifically, the use of the terms "exemplary" or "for example" is intended to present the relevant concepts in a specific manner.

[0048] refer to Figures 1 to 8 As shown, the present invention provides the following preferred embodiments:

[0049] Example 1

[0050] To address the integration challenges of multi-module collaborative design in 10 Gigabit Ethernet port signal processing, this embodiment provides a 10 Gigabit Ethernet port protection circuit, further clarifying the system architecture and physical connection relationships of each functional module. The protection circuit is built between the chip and the network port, achieving integrated functions of signal conditioning, noise suppression, overvoltage protection, and power coupling through modular design.

[0051] The chip-side signal preprocessing module is configured between the differential signal nodes (10GPHY_MDIAP_P0, 10GPHY_MDIAN_P0) and the intermediate signal nodes (10GE_AP_TSP0, 10GE_AN_TSP0) on the chip side. An initial impedance matching path is established through matching resistors, and a high-frequency bypass capacitor is connected in parallel at the ground terminal to form the first filtering barrier against coupled noise from the chip's power supply. It is important to understand that the layout of this module must adhere to the principle of equal length for differential pair traces, and the parasitic inductance parameter of the matching resistors must be controlled below 5nH to avoid introducing additional signal distortion.

[0052] The dual RC isolation transmission module serves as the core link for signal transmission, connecting intermediate signal nodes with the differential signal nodes at the network port (RJ45_AP_P0, RJ45_AN_P0). Its two-stage RC coupling units form a frequency-selective transmission channel: the first stage achieves DC isolation through coupling capacitors, ensuring independent bias between the preceding and following stages; the second stage forms a filter network through a series combination of resistors and capacitors to attenuate noise in non-target frequency bands. In the circuit design, the dielectric loss tangent of the two capacitor stages must be less than 0.01 to meet the low-loss requirement for 10Gbps signal transmission.

[0053] The surge protection module employs a tiered protection strategy. The first surge suppression unit is connected in parallel between intermediate signal nodes at the chip level to provide primary clamping protection against local transient interference. The second surge suppression unit is deployed between intermediate transmission nodes at the network port level to handle high-energy surge impacts introduced from the outside. The clamping voltage gradient settings of the two units are matched with the parasitic capacitance parameters to the signal transmission characteristics, avoiding the phase shift effect of the protection device on high-frequency signals.

[0054] The PoE power coupling module utilizes the magnetic coupling characteristics of a common-mode inductor to achieve collinear transmission of power and data signals. The input terminal of the common-mode inductor winding is connected to the differential signal node at the network port, and the center tap is connected to the PoE power input node (CT1). The output terminal of the winding is filtered for high-frequency noise via a grounding capacitor. It is important to note that the differential-mode insertion loss of the common-mode inductor must be less than 0.5dB@10GHz to ensure that the integrity of the data signal is not affected by power coupling.

[0055] The advantage of this embodiment is that, through modular functional division and hierarchical connection between nodes, an integrated protection circuit architecture including impedance matching, noise filtering, overvoltage protection and power coupling is constructed. The parameter design and layout rules of each module are coordinated with each other, providing a systematic hardware implementation solution for reliable transmission of 10 Gigabit Ethernet signals in complex electromagnetic environments.

[0056] Example 2

[0057] To address the issues of characteristic impedance deviation and high-frequency noise coupling during chip-side signal preprocessing, this embodiment further refines the circuit structure and component configuration of the impedance compensation network. The chip-side signal preprocessing module utilizes a symmetrical resistor-capacitor network to achieve impedance calibration and common-mode noise suppression for differential signal pairs.

[0058] The positive signal node 10GPHY_MDIAP_P0 on the chip is connected to the intermediate positive signal node 10GE_AP_TSP0 via matching resistor 10GPR3, and the negative signal node 10GPHY_MDIAN_P0 is connected to the intermediate negative signal node 10GE_AN_TSP0 via matching resistor 10GPR7. The resistance values ​​of the two resistors are designed according to the principle of transmission line characteristic impedance matching, forming a voltage divider network with the chip output impedance and the input impedance of subsequent links. The bypass capacitors 10GPC15 and 10GPC32 connected in parallel at the ground terminal are made of NPO ceramic material with excellent high-frequency characteristics, with capacitance values ​​of 47nF and 100nF respectively, providing low-impedance discharge paths for common-mode noise in the frequency bands below and above 1GHz.

[0059] Furthermore, intermediate transmission nodes 10GE_AP_TMP0 and 10GE_AN_TMP0 are grounded through bypass capacitors 10GPC17 and 10GPC33, respectively, forming high-frequency compensation for the parasitic inductance of the intermediate nodes. The four-port network formed by the matching resistor and the bypass capacitor has impedance-frequency characteristics that satisfy:

[0060] Among them, Z diff (f) represents the differential impedance, Z0 represents the target characteristic impedance (100Ω), and C b1 C b2 L is the capacitance value of the bypass capacitor. p This is for the parasitic inductance of the trace. By adjusting the resistance and capacitance values, the magnitude deviation of this expression within the 10GHz band can be controlled within ±5%.

[0061] In hardware implementation, matching resistors are selected with a precision of ±1% and a temperature coefficient of ±50ppm / ℃. Bypass capacitors are installed close to signal nodes to shorten the grounding path and reduce the influence of parasitic inductance. In PCB stack-up design, the spacing between the signal layer and the ground plane is controlled within 50μm to ensure the stability of the characteristic impedance of the differential pair.

[0062] The advantage of this embodiment is that, through parameter optimization and component selection of the symmetrical impedance compensation network, a preprocessing circuit with DC bias stability, high-frequency noise filtering and wideband impedance matching functions is constructed, providing high-quality signal input conditions for subsequent transmission links.

[0063] Example 3

[0064] To address the DC offset and non-target frequency band noise interference issues during the transmission of 10 Gigabit high-frequency signals, this embodiment further clarifies the hierarchical filtering structure design of the dual RC isolation transmission module. This module achieves selective signal transmission and noise suppression by leveraging the difference in frequency response characteristics between the two stages of RC units.

[0065] In the first-stage RC coupling unit, the intermediate positive signal node 10GE_AP_TSP0 is connected to the intermediate positive transmission node 10GE_AP_TMP0 via the first coupling capacitor 10GPC22. A second coupling capacitor 10GPC26 is symmetrically configured on the negative path. The capacitance of both capacitors is set to 2.2nF. Utilizing the capacitive reactance characteristics of the capacitors in the 10Gbps signal band (approximately 5GHz), X... C =1 / (2πfC)≈14.5Ω, providing a low-impedance path for high-frequency signals while blocking DC components to avoid mutual interference between the biases of the preceding and following stages.

[0066] The second-stage RC filter unit adopts a π-type network structure. The intermediate positive transmission node 10GE_AP_TMP0 is connected to the positive signal node RJ45_AP_P0 at the network port via a third matching resistor 10GPR4 (47Ω) and a third coupling capacitor 10GPC23 (68pF). The negative path is symmetrically configured with a fourth matching resistor 10GPR8 and a fourth coupling capacitor 10GPC27. The cutoff frequency of this network is determined by the resistor and capacitor parameters, and the calculation formula is as follows:

[0067] Where R is the resistance of the matching resistor and C is the capacitance of the coupling capacitor, it attenuates noise above 200MHz, and its insertion loss increases with frequency, reaching over 20dB at 1GHz. It is important to understand that the dielectric of the second-stage coupling capacitor is made of low-loss polytetrafluoroethylene (PTFE) to reduce energy loss during signal transmission.

[0068] During PCB layout, the two capacitors are placed close to their corresponding signal nodes, and the trace length of the matching resistor is controlled within 10mm to avoid introducing additional transmission delay. The differential pair traces adopt a design with a 50μm trace width and a 100μm trace spacing to ensure that the characteristic impedance is consistent with the module's input and output impedance.

[0069] The advantage of this embodiment is that, through the differentiated frequency response design of the two-stage resistor-capacitor unit, a three-stage filtering link with DC isolation, high-frequency transparency, and noise attenuation in a specific frequency band is constructed, which effectively improves the integrity and anti-interference capability of 10 Gigabit signals in long-distance transmission.

[0070] Example 4

[0071] To address the need for tiered protection against transient overvoltages at the chip and network port levels, this embodiment further clarifies the differentiated configuration and collaborative working mechanism of the two-stage suppression units in the surge protection module. This module, through the parameter gradient design of bidirectional transient voltage suppressor (TVS) devices, forms a progressive overvoltage protection system from the chip level to the network port level.

[0072] The first surge suppression unit uses a bidirectional TVS device 10GTVS1, connected in parallel between the intermediate signal nodes 10GE_AP_TSP0 and 10GE_AN_TSP0 on the chip. Its clamping voltage is set to be 1.2 times lower than the withstand voltage of the chip's I / O port. For example, if the chip port withstand voltage is 5V, the clamping voltage is controlled within 6V to quickly respond to local electrostatic discharge (ESD) or electrical fast transient (EFT) interference generated on the chip. The parasitic capacitance of this device must be less than 5pF to avoid phase distortion affecting 10Gbps high-frequency signals.

[0073] The second surge suppression unit uses a bidirectional TVS device 10GTVS2 with higher peak pulse power, connected in parallel between the intermediate transmission nodes 10GE_AP_TMP0 and 10GE_AN_TMP0 at the network port. Its peak pulse power is at least five times that of the first-stage device (e.g., above 400W), specifically designed to handle external high-energy transient interference such as lightning surges. The response time of both devices must be controlled within 1ns to ensure that clamping action is initiated at the rising edge of the overvoltage pulse.

[0074] In the circuit design, the ground pin of the TVS device uses an independent low-inductance grounding path, and the grounding pad is directly connected to the main ground plane to reduce ground loop impedance. The trace length between the signal node and the TVS device is controlled within 5mm to reduce the parasitic inductance effect during overvoltage transmission. It is important to understand that the clamping voltage and energy handling capability of the two stages of devices are matched in a gradient manner to avoid excessive voltage at the chip end and to prevent high-energy interference introduced at the network port from damaging the back-end circuitry.

[0075] The advantage of this embodiment is that, through the differentiated configuration and layout optimization of the parameters of the two-stage TVS devices, a hierarchical surge protection circuit with fast response speed, strong energy absorption capability, and small impact of high-frequency signals is constructed, which meets the stringent requirements for interface protection in the IEEE 802.3bz standard.

[0076] Example 5

[0077] To address the interference coupling issue when 10 Gigabit data signals and PoE power signals are transmitted along the same line, this embodiment further clarifies the magneto-electric coupling structure and noise suppression mechanism of the PoE power coupling module. This module utilizes the frequency selectivity of a common-mode inductor to achieve bidirectional, interference-free superposition of DC power and high-frequency data signals.

[0078] The common-mode inductor T1 employs a dual-wire parallel-wound toroidal ferrite core structure. The two winding inputs are connected to the differential signal nodes RJ45_AP_P0 and RJ45_AN_P0 on the Ethernet port, respectively. The center tap is connected to the PoE power input node CT1. The outputs are connected to signal ground SGND via grounding capacitors 10GPC14 and 10GPC34 (100nF). The common-mode inductor presents high impedance (>1kΩ@100MHz) for common-mode signals and low impedance (<10Ω@10GHz) for differential-mode signals, thereby suppressing common-mode interference in the power path from coupling to the data signal while allowing DC power and differential data signals to pass through.

[0079] A π-type filter network consisting of an inductor L1 (10μH) and a parallel capacitor C1 (47μF) is added to the front end of the power input node CT1 to further filter out low-frequency ripple in the PoE power supply. The common-mode inductor is designed with an inductance value of 20μH and a DC resistance controlled below 30mΩ to reduce energy loss during power transmission. The grounding capacitor is a multilayer ceramic capacitor with low equivalent series inductance (ESL) and a self-resonant frequency higher than 1GHz, ensuring effective filtering of high-frequency noise.

[0080] During signal transmission, the characteristic impedance of the differential signal after power supply superposition is controlled within 100Ω ± 5% by matching the parameters of the matching resistor and coupling capacitor. It is important to understand that the winding symmetry error of the common-mode inductor must be less than 1% to avoid introducing amplitude imbalance in the differential signal, which would affect signal transmission quality.

[0081] The advantage of this embodiment is that, through the synergistic effect of the magnetic coupling characteristics of the common-mode inductor and the grounding filter unit, a low-interference coupling channel for power and data co-line transmission is constructed, which not only achieves efficient transmission of PoE power but also ensures the integrity of 10 Gigabit data signals, meeting the power supply and communication compatibility requirements of industrial-grade Ethernet interfaces.

[0082] Example 6

[0083] To address the standardization and compatibility issues of parallel transmission of multiple differential pairs on 10 Gigabit Ethernet ports, this embodiment further clarifies the circuit structure and pin layout specifications for the four differential signal pairs. The 10 Gigabit Ethernet port conforms to the T568B standard, mapping the four differential signal pairs PAIR A, PAIR B, PAIR C, and PAIR D to pins 1 / 2, 3 / 6, 4 / 5, and 7 / 8 of the RJ45 interface, respectively. Each pair is equipped with an independent protection circuit unit to ensure signal transmission consistency and crosstalk immunity.

[0084] Each protection circuit unit includes a chip-side signal preprocessing module, a dual RC isolation transmission module, a surge protection module, and a PoE power coupling module. Its circuit structure is completely symmetrical, with only the node names and component numbers increasing sequentially by group. In the chip-side signal preprocessing module, each differential pair forms an impedance matching network through independent matching resistors and bypass capacitors. The resistance tolerance of the matching resistors is controlled within ±0.5%, ensuring that the characteristic impedance deviation of each signal pair is less than 1Ω.

[0085] The dual RC isolation transmission module employs a symmetrical layout for its two-stage RC units. The capacitance error of the first-stage coupling capacitor is controlled within ±2%, and the resistor and capacitor parameters of the second-stage π-type filter network are strictly consistent to reduce differences in signal transmission delay between groups. In the surge protection module, the bidirectional TVS devices in each group are installed adjacent to the corresponding intermediate signal node, with independent grounding paths to avoid mutual interference between protection units in different groups.

[0086] In the PoE power coupling module, the input terminals of each common-mode inductor are connected to the corresponding pins on the network port, and the center taps converge to a unified PoE power input node CT1. The output grounding capacitors are arranged in an array and connected to the main ground plane as close as possible. It is important to understand that the PCB traces of the four differential pairs are designed with equal length and spacing, and the dielectric constant consistency error of the interlayer insulation medium is less than 0.1% to reduce signal crosstalk and delay deviation.

[0087] The advantage of this embodiment is that, through standardized pin layout, symmetrical circuit structure and strict parameter consistency design, a 10 Gigabit Ethernet interface circuit supporting multi-differential pair parallel transmission is constructed, which meets the requirements of IEEE 802.3 standard for signal integrity and interface compatibility, and provides a reliable hardware platform for high-speed data transmission.

[0088] Although the present invention has been specifically described above with reference to preferred embodiments, it should be understood that the present invention is not limited to the embodiments described above. Rather, various modifications and variations can be made by those skilled in the art without departing from the essence of the present invention, and such modifications and variations should fall within the scope defined by the appended claims and their equivalents.

Claims

1. A 10 Gigabit Ethernet port protection circuit, characterized in that, The protection circuit includes: The chip-side signal preprocessing module is configured between the chip-side differential signal nodes (10GPHY_MDIAP_P0, 10GPHY_MDIAN_P0) and the intermediate signal nodes (10GE_AP_TSP0, 10GE_AN_TSP0) to achieve initial impedance matching of the signal input. A dual RC isolation transmission module is configured between the intermediate signal nodes (10GE_AP_TSP0, 10GE_AN_TSP0) and the differential signal nodes at the network port (RJ45_AP_P0, RJ45_AN_P0), including two stages of RC coupling units, for realizing DC isolation, 10 Gigabit high-frequency signal transmission and noise filtering; The surge protection module includes a first surge suppression unit connected in parallel between the intermediate signal nodes and a second surge suppression unit connected in parallel between the intermediate transmission nodes, used to clamp and protect the transient overvoltage at the chip end and the network port end. The POE power coupling module is configured between the differential signal nodes (RJ45_AP_P0, RJ45_AN_P0) at the network port and the POE power input node (CT1). It includes a common-mode inductor and a grounding filter unit to suppress common-mode noise and realize the coupling transmission of data signals and POE power signals.

2. The 10 Gigabit Ethernet port protection circuit as described in claim 1, characterized in that, The chip-side signal preprocessing module includes: The chip-side positive signal node 10GPHY_MDIAP_P0 is connected to the intermediate positive signal node 10GE_AP_TSP0 through the matching resistor 10GPR3; The negative signal node 10GPHY_MDIAN_P0 at the chip end is connected to the intermediate negative signal node 10GE_AN_TSP0 through the matching resistor 10GPR7; The ground terminal of the chip-side signal preprocessing module is connected in parallel with bypass capacitors 10GPC15 and 10GPC32. The intermediate transmission node 10GE_AP_TMP0 is grounded (GND) through bypass capacitor 10GPC17, and 10GE_AN_TMP0 is grounded (GND) through the fourth bypass capacitor 10GPC33. The matching resistors (10GPR3, 10GPR7, 10GPR4, 10GPR8) and the bypass capacitors (10GPC15, 10GPC32, 10GPC17, 10GPC33) together form an impedance compensation network to ensure that the characteristic impedance of the differential signal pair is accurately matched to the 100Ω standard.

3. The 10 Gigabit Ethernet port protection circuit as described in claim 1, characterized in that, The dual RC isolation transmission module includes: First-stage RC coupling unit: The intermediate positive signal node 10GE_AP_TSP0 is connected to the intermediate positive transmission node 10GE_AP_TMP0 through the first coupling capacitor 10GPC22, and the intermediate negative signal node 10GE_AN_TSP0 is connected to the intermediate negative transmission node 10GE_AN_TMP0 through the second coupling capacitor 10GPC26, which is used to block the DC component and allow the 10Gbps high-frequency signal to pass through. Second-stage RC filter unit: The intermediate positive transmission node 10GE_AP_TMP0 is connected to the positive signal node RJ45_AP_P0 at the network port through the third matching resistor 10GPR4 and the third coupling capacitor 10GPC23. The intermediate negative transmission node 10GE_AN_TMP0 is connected to the negative signal node RJ45_AN_P0 at the network port through the fourth matching resistor 10GPR8 and the fourth coupling capacitor 10GPC27. The third matching resistor 10GPR4, the fourth matching resistor 10GPR8, the third coupling capacitor 10GPC23, and the fourth coupling capacitor 10GPC27 form a π-type filter network to suppress common-mode and differential-mode noise during transmission.

4. The 10 Gigabit Ethernet port protection circuit as described in claim 1, characterized in that, The surge protection module includes: The first surge suppression unit is a bidirectional transient voltage suppression device 10GTVS1, with its two ends connected to the intermediate positive signal node 10GE_AP_TSP0 and the intermediate negative signal node 10GE_AN_TSP0, respectively, to clamp transient common-mode overvoltage at the chip end; The second surge suppression unit is a bidirectional transient voltage suppression device 10GTVS2, with its two ends connected to the intermediate positive transmission node 10GE_AP_TMP0 and the intermediate negative transmission node 10GE_AN_TMP0, respectively, to clamp transient differential mode overvoltage at the network port. The bidirectional transient voltage suppression devices 10GTVS1 and 10GTVS2 limit the voltage amplitude within the safe operating range of the devices to meet the surge protection requirements of the IEEE 802.3bz standard.

5. The 10 Gigabit Ethernet port protection circuit as described in claim 1, characterized in that, The PoE power coupling module includes: The two winding input terminals of the common mode inductor T1 are connected to the positive signal node RJ45_AP_P0 and the negative signal node RJ45_AN_P0 of the network port, respectively; The center tap of the common mode inductor T1 is connected to the POE power input node CT1 for coupling the POE power signal; The output terminals of the two windings are connected to signal ground SGND through grounding capacitors 10GPC14 and 10GPC34 respectively, to filter out high-frequency noise in the power supply path. The common-mode inductor T1 suppresses common-mode interference and enables the co-line transmission of 10 Gigabit data signals and PoE power signals.

6. The 10 Gigabit Ethernet port protection circuit as described in claim 1, characterized in that, The 10 Gigabit Ethernet port includes four differential signal pairs PAIR A, PAIR B, PAIR C, and PAIR D. Each protection circuit unit includes a chip-side signal preprocessing module, a dual RC isolation transmission module, a surge protection module, and a POE power coupling module. The network port signal nodes of each differential signal pair correspond to the standard pin layout of the RJ45 interface T568B, where PAIR A corresponds to pins 1 / 2, PAIR B corresponds to pins 3 / 6, PAIR C corresponds to pins 4 / 5, and PAIR D corresponds to pins 7 / 8. In the chip-side signal preprocessing module, the chip-side differential signal nodes are connected to the intermediate signal nodes through matching resistors, and together with the grounding bypass capacitor, they form a differential impedance matching network. The dual RC isolation transmission module includes two stages of RC units. The first stage coupling capacitor connects the intermediate signal node and the intermediate transmission node to block DC and pass high-frequency signals. The second stage consists of a matching resistor and a coupling capacitor forming a filter network to suppress common-mode and differential-mode noise. In the surge protection module, bidirectional transient voltage suppression devices are connected in parallel between intermediate signal nodes and intermediate transmission nodes to clamp transient overvoltages between the chip end and the network port end. In the POE power coupling module, the input terminals of each group of common-mode inductors are connected to the network port signal nodes, the center tap is connected to the front-end π-type power filter network composed of inductors and parallel capacitors, and the winding output terminals are filtered out by grounding capacitors to achieve collinear transmission of data signals and POE power; the circuit structures of the four differential signal pairs are consistent.

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