A front-facing LED chip and light emitting device

Abstract

A positive-mounted LED chip and a light-emitting device are disclosed. The positive-mounted LED chip includes: a substrate, an epitaxial stack, a first electrode, a second electrode, a passivation layer, and a protective layer. The epitaxial stack is located on one side surface of the substrate; the epitaxial stack includes a first type semiconductor layer, an active layer, and a second type semiconductor layer; the epitaxial stack has a groove exposing a portion of the surface of the first type semiconductor layer; the first electrode is disposed in the groove and electrically connected to the first type semiconductor layer; the second electrode is disposed on the surface of the second type semiconductor layer facing away from the substrate and electrically connected to the second type semiconductor layer; the passivation layer covers a portion of the exposed surface of the epitaxial stack; the protective layer covers the exposed sidewalls of the epitaxial stack, so as to encapsulate the epitaxial stack together with the passivation layer. Adding a protective layer to cover the exposed sidewalls of the epitaxial stack not covered by the passivation layer achieves full coverage of the sidewalls of the epitaxial stack, avoids moisture erosion, and increases the overall reliability of the chip.

Description

Technical Field

[0001] This utility model relates to the field of light-emitting diode technology, and more specifically, to a standard-mounted LED chip and a light-emitting device. Background Technology

[0002] Light-emitting diode (LED) chips are PN junction electroluminescent devices. As a new generation of lighting source, they have many advantages such as high efficiency, energy saving, environmental friendliness, and long service life, and are widely used in lighting, display, backlighting and other fields. With the continuous advancement of technology and the sustained growth of market demand, the LED chip industry has developed rapidly, and its manufacturing processes and technologies are constantly being innovated and improved.

[0003] The conventional chip structure typically includes steps such as MESA platform fabrication, electrode fabrication, and passivation layer (PV) fabrication. After the chip is cut from the wafer state, it becomes a chip. The passivation layer can only cover part of the sidewalls of the epitaxial stack, leaving some of the sidewall areas exposed. These areas are susceptible to moisture erosion, affecting the overall reliability of the chip.

[0004] The conventional approach to this problem is deep etching, which completely etches through the epitaxial stack at the die edge to expose the substrate, followed by passivation layer deposition. However, this method reduces the light-emitting area of ​​the active layer, affecting product brightness. For small-sized products aiming for high brightness, this is a counterproductive processing method. Furthermore, it reduces the number of dies that can be fabricated on the same size wafer, increasing production costs. Therefore, how to increase the overall reliability of the chip without reducing the light-emitting area has become a pressing issue. Utility Model Content

[0005] In view of this, the present invention provides a standard LED chip and a light-emitting device, which can increase the overall reliability of the chip without reducing the area of ​​the light-emitting area.

[0006] To achieve the above objectives, the technical solution adopted by this utility model is as follows:

[0007] A standard LED chip, comprising:

[0008] Substrate;

[0009] An epitaxial stack is located on one side surface of the substrate; the epitaxial stack includes a first type semiconductor layer, an active layer, and a second type semiconductor layer; the epitaxial stack has a groove exposing a portion of the surface of the first type semiconductor layer;

[0010] A first electrode is disposed in the groove and electrically connected to the first type of semiconductor layer;

[0011] The second electrode is disposed on the surface of the second type semiconductor layer away from the substrate and is electrically connected to the second type semiconductor layer.

[0012] A passivation layer that covers a portion of the exposed surface of the epitaxial stack;

[0013] A protective layer covers the exposed sidewalls of the epitaxial stack to encapsulate the epitaxial stack together with the passivation layer.

[0014] Optionally, it also includes an insulating coupling agent material filling layer, which is at least disposed on the sidewall of the protective layer.

[0015] Optionally, along the first direction, the height of the coupling agent material filling layer is lower than the height of the surface of the first electrode facing away from the substrate;

[0016] The first direction is perpendicular to the substrate and extends from the substrate toward the active layer.

[0017] Optionally, the groove surrounds the active layer, and the passivation layer covers the exposed surface of the epitaxial stack opposite to the substrate and the groove wall; the protective layer and the passivation layer have overlapping areas.

[0018] Optionally, the protective layer extends to the sidewall of the substrate to cover the contact interface between the epitaxial stack and the substrate.

[0019] Optionally, the sidewall of the epitaxial layer that contacts the protective layer is a slope;

[0020] The angle between the inclined plane and the substrate facing the active layer surface is less than 90°.

[0021] Optionally, the protective layer covers a portion of the sidewalls of the passivation layer near the substrate to form an overlapping region;

[0022] Alternatively, the protective layer may cover the entire passivation layer to form an overlapping area.

[0023] Optionally, the passivation layer also covers a portion of the exposed surfaces of the first and second electrodes.

[0024] This utility model also provides a light-emitting device, which includes the aforementioned upright LED chip.

[0025] Optionally, the light-emitting device includes a display device, and the display device includes the aforementioned positive-mounted LED chip.

[0026] Compared with the prior art, the technical solution provided by this utility model has at least the following advantages:

[0027] 1. A standard LED chip includes: a substrate; an epitaxial stack located on one side surface of the substrate; the epitaxial stack includes a first type semiconductor layer, an active layer, and a second type semiconductor layer; the epitaxial stack has a groove exposing a portion of the surface of the first type semiconductor layer; a first electrode disposed in the groove and electrically connected to the first type semiconductor layer; a second electrode disposed on the surface of the second type semiconductor layer away from the substrate and electrically connected to the second type semiconductor layer; a passivation layer covering a portion of the exposed surface of the epitaxial stack; and a protective layer covering the exposed sidewalls of the epitaxial stack, together with the passivation layer, to encapsulate the epitaxial stack. Based on the above structure, the LED chip, in addition to the passivation layer, also adds a protective layer to cover the exposed sidewalls of the epitaxial stack not covered by the passivation layer. Therefore, it is not necessary to perform deep etching followed by passivation layer deposition to achieve full coverage of the sidewalls of the epitaxial stack. That is, by encapsulating the exposed surface and sidewalls of the epitaxial stack with the passivation layer and the protective layer, moisture erosion is avoided, the overall reliability of the chip is increased, and the area of ​​the light-emitting area is not reduced, nor is the number of chips that can be fabricated on the wafer reduced. In the actual manufacturing process of LED chips, a protective layer can be made after the wafer is cut into dies to cover the exposed sidewalls of the epitaxial stack.

[0028] 2. The protective layer on the sidewalls of epitaxial laminates is typically thin and prone to poor film quality due to mechanical stress or contamination, resulting in decreased adhesion and poor water vapor retention. Furthermore, during the subsequent LED chip encapsulation, the shrinkage or thermal stress generated during the curing of the encapsulant tends to concentrate at corners (e.g., the junction of the passivation layer and the protective layer). Insufficient flowability or poor wetting properties of the encapsulant during filling can lead to voids or weak interfaces on the sides of the LED chip. These factors, along with the poor quality of the protective layer on the epitaxial laminate sidewalls, all contribute to the easy separation of the encapsulant from the LED chip sidewalls. Therefore, a coupling agent filling layer should be placed at least on the sidewalls of the protective layer. This not only fills microcracks (defects smaller than 100nm) in the protective layer, increasing its water vapor retention and overall chip reliability, but also increases the adhesion between the LED chip and the encapsulant, improving the separation of the encapsulant from the LED chip sidewalls at the chip end.

[0029] 3. Along the first direction, the height of the coupling agent material filling layer is lower than the height of the surface of the first electrode facing away from the substrate, so as to avoid the coupling agent material filling layer adhering to the exposed surface of the first electrode and affecting the bonding wire of the first electrode.

[0030] 4. The passivation layer covers the exposed surface of the epitaxial stack away from the substrate and the trench walls. The protective layer and the passivation layer have overlapping areas. Compared with areas without overlap, this can better prevent moisture from entering the epitaxial stack through the junction of the passivation layer and the protective layer, increasing the water vapor resistance and improving the overall reliability of the chip.

[0031] 5. The protective layer extends to the sidewall of the substrate to cover the contact interface between the epitaxial stack and the substrate, preventing moisture from entering the epitaxial stack from the contact interface, increasing water vapor resistance, and improving the overall reliability of the chip.

[0032] 6. The sidewalls where the epitaxial stack contacts the protective layer are beveled; the angle between the beveled surface and the substrate facing the active layer surface is less than 90°, providing a better coverage angle for the protective layer, allowing the protective layer to better cover the sidewalls of the epitaxial stack, increasing water vapor resistance and improving the overall reliability of the chip. Attached Figure Description

[0033] To more clearly illustrate the technical solutions in the embodiments of this utility model or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of this utility model. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0034] Figure 1 A schematic diagram of one embodiment of a positively mounted LED chip;

[0035] Figure 2 A schematic diagram of another embodiment of a positively mounted LED chip;

[0036] Figure 3 A schematic diagram of another embodiment of a positively mounted LED chip;

[0037] Figure 4 A schematic diagram of another embodiment of a positively mounted LED chip;

[0038] Figure 5 A schematic diagram illustrating the steps of one embodiment of a method for manufacturing a standard LED chip;

[0039] Figure 6 A schematic diagram illustrating the steps of another embodiment of the method for manufacturing a standard LED chip;

[0040] Figure 7 This is a schematic diagram of an epitaxial stack fabricated on a substrate in one embodiment;

[0041] Figure 8 In order to be in Figure 7 Based on this, a structural diagram of the MESA platform was created;

[0042] Figure 9 In order to be in Figure 8 A schematic diagram of the structure after fabricating a transparent conductive layer based on the above;

[0043] Figure 10 In order to be in Figure 9 Based on the above, a schematic diagram of the structure after fabricating the first and second electrodes is shown;

[0044] Figure 11 In order to be in Figure 10 A schematic diagram of the structure after the passivation layer is fabricated based on the above.

[0045] Figure 12 This is a schematic diagram of the cutting position for cutting into grains in one embodiment;

[0046] Figure 13 for Figure 12 A magnified view of part A in the image;

[0047] Figure 14 This is a schematic diagram of the structure of a single grain formed by cutting in one embodiment;

[0048] Figure 15-17 In order to be in Figure 14 A schematic diagram of an embodiment of fabricating a protective layer on a grain is shown.

[0049] Figure 18-20 In order to be in Figure 14 A schematic diagram of another embodiment of the formation of a protective layer on the grains is shown.

[0050] Figure label:

[0051] Substrate 1; Type I semiconductor layer 2; Active layer 3; Type II semiconductor layer 4; Groove 5; Transparent conductive layer 6; First electrode 7; Second electrode 8; Passivation layer 9; Protective layer 10; Coupling agent material filling layer 11; Adhesive film 12;

[0052] First direction D1; Second direction D2. Detailed Implementation

[0053] To make the content of this utility model clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.

[0054] Many specific details are set forth in the following description in order to provide a full understanding of this application. However, this application may also be implemented in other ways different from those described herein. Those skilled in the art can make similar extensions without departing from the spirit of this application. Therefore, this application is not limited to the specific embodiments disclosed below.

[0055] Secondly, this application provides a detailed description in conjunction with schematic diagrams. When detailing the embodiments of this application, for ease of explanation, the cross-sectional views illustrating the device structure may be partially enlarged, not adhering to the usual scale. Furthermore, the schematic diagrams are merely examples and should not limit the scope of protection of this application. In addition, actual fabrication should include three-dimensional spatial dimensions of length, width, and depth.

[0056] As described in the background section, conventional upright-structure chips transition from a wafer state to a chip state after dicing. The passivation layer only partially covers the sidewalls of the epitaxial stack, leaving some exposed areas susceptible to moisture corrosion, impacting overall chip reliability. A conventional solution is deep etching, completely exposing the substrate at the chip edge before passivation layer deposition. However, this method reduces the light-emitting area of ​​the active layer, affecting product brightness. For small-sized products aiming for high brightness, this is a counterproductive processing method. Furthermore, it reduces the number of chips that can be fabricated on a wafer of the same size, increasing production costs. Therefore, increasing overall chip reliability without reducing the light-emitting area is a pressing issue.

[0057] To address the aforementioned technical problems, this application provides a standard-mount LED chip, its manufacturing method, and a light-emitting device. Figure 1 , 2 As shown, a standard LED chip includes a substrate 1, an epitaxial stack, a first electrode 7, a second electrode 8, a passivation layer 9, and a protective layer 10.

[0058] An epitaxial stack is located on one side surface of substrate 1. The epitaxial stack includes a first type semiconductor layer 2, an active layer 3, and a second type semiconductor layer 4. The epitaxial stack has a groove 5 exposing a portion of the surface of the first type semiconductor layer 2. A first electrode 7 is disposed in the groove 5 and electrically connected to the first type semiconductor layer 2. A second electrode 8 is disposed on the surface of the second type semiconductor layer 4 facing away from substrate 1 and electrically connected to the second type semiconductor layer 4. A passivation layer 9 covers a portion of the exposed surface of the epitaxial stack. A protective layer 10 covers the exposed sidewalls of the epitaxial stack to encapsulate the epitaxial stack together with the passivation layer 9.

[0059] Based on the above structure, the LED chip, in addition to the passivation layer 9, also includes a protective layer 10 to cover the exposed sides of the epitaxial stack not covered by the passivation layer 9. Therefore, it eliminates the need for deep etching followed by passivation layer 9 deposition, achieving full coverage of the epitaxial stack sidewalls. In other words, by separately fabricating the passivation layer 9 and the protective layer 10, the exposed surfaces and sidewalls of the epitaxial stack are encapsulated, preventing moisture erosion, increasing the overall reliability of the chip, and without reducing the area of ​​the light-emitting region or the number of chips that can be fabricated on the wafer. In the actual manufacturing process of the LED chip, the protective layer 10 can be fabricated after the wafer is diced into chips to cover the exposed sidewalls of the epitaxial stack.

[0060] Preferably, the epitaxial stack further includes a transparent conductive layer 6, which is disposed on the surface of the second type semiconductor layer 4 away from the active layer 3.

[0061] In this embodiment, one of the first type semiconductor layer 2 and the second type semiconductor layer 4 is an N-type semiconductor layer, and the other is a P-type semiconductor layer. This embodiment uses an N-type semiconductor layer 2 and a P-type semiconductor layer 4 as an example. Optionally, the N-type semiconductor layer can be N-type GaN, and the P-type semiconductor layer can be P-type GaN. It should be understood that the materials are not limited to these; appropriate materials can be selected according to actual light emission requirements. The active layer 3 can be a multiple quantum well. Optionally, the materials of the first electrode 7 and the second electrode 8 can include one or more of gold, silver, titanium, nickel, aluminum, platinum, chromium, tin, copper, and alloy materials. Optionally, the transparent conductive layer 6 can be a single metal thin film, such as gold, silver, platinum, copper, aluminum, chromium, palladium, etc. The transparent conductive layer 6 can also be a metal oxide, such as indium oxide, indium tin oxide, zirconium oxide, cadmium oxide, titanium nitride, etc. The transparent conductive layer 6 can also be a mixture of various oxides doped in different proportions. Optionally, the passivation layer 9 is a transparent insulating material, such as one or more of silicon oxide, silicon nitride, aluminum oxide, and magnesium fluoride.

[0062] More preferably, the groove 5 surrounds the active layer 3, the passivation layer 9 covers the exposed surface of the epitaxial stack away from the substrate 1 and the groove wall of the groove 5, and the protective layer 10 and the passivation layer 9 have an overlapping area. The overlapping area between the protective layer 10 and the passivation layer 9, compared to a non-overlapping area, better prevents moisture from entering the epitaxial stack through the junction of the passivation layer 9 and the protective layer 10, increasing water vapor resistance and improving the overall reliability of the chip.

[0063] More preferably, the passivation layer 9 also covers a portion of the exposed surfaces of the first electrode 7 and the second electrode 8. Optionally, the passivation layer 9 covers the sidewalls of the first electrode 7 and the portion of the surface of the first electrode 7 facing away from the substrate 1. The passivation layer 9 also covers the sidewalls of the second electrode 8 and the portion of the surface of the second electrode 8 facing away from the substrate 1.

[0064] More preferably, the protective layer 10 extends to the sidewall of the substrate 1 to cover the contact interface between the epitaxial stack and the substrate 1. This arrangement prevents moisture from entering the epitaxial stack from the contact interface between the epitaxial stack and the substrate 1, increasing its moisture resistance and improving the overall reliability of the chip.

[0065] More preferably, the protective layer 10 covers a portion of the sidewalls of the passivation layer 9 near the substrate 1, forming an overlapping region. Alternatively, the protective layer 10 covers the entire passivation layer 9, forming an overlapping region.

[0066] Figure 1A schematic diagram of an embodiment of a positive-mounted LED chip is shown. As can be seen from the figure, the passivation layer 9 covers the exposed surface of the epitaxial stack away from the substrate and the trench walls. Some sidewalls around the first type semiconductor layer 2 are not protected by the passivation layer 9. The protective layer 10 covers the sidewalls of the first type semiconductor layer 2 that are not protected by the passivation layer 9 and the sidewalls around the substrate 1. The protective layer 10 also extends toward the passivation layer 9 to cover the part of the sidewalls of the passivation layer 9 near the substrate 1 to form an overlapping area. The height of the protective layer 10 along the first direction D1 is lower than the height of the surface of the first electrode 7 away from the substrate 1 along the first direction D1. The first direction D1 is perpendicular to the substrate 1 and points from the substrate 1 toward the active layer 3.

[0067] Figure 2 A schematic diagram of another embodiment of a positive-mounted LED chip is shown. As can be seen from the figure, the passivation layer 9 covers the exposed surface of the epitaxial stack away from the substrate 1 and the trench wall of the groove 5. Some of the sidewalls around the first type semiconductor layer 2 are not protected by the passivation layer 9. The protective layer 10 covers the sidewalls around the first type semiconductor layer 2 that are not protected by the passivation layer 9 and the sidewalls around the substrate 1. The protective layer 10 also completely covers the passivation layer 9 to form an overlapping area.

[0068] Based on any of the above embodiments, in a preferred embodiment, the upright LED chip further includes an insulating coupling agent material filling layer 11. The coupling agent material filling layer 11 is at least disposed on the sidewalls of the protective layer 10. Preferably, in this embodiment, the coupling agent material filling layer 11 is disposed only on the sidewalls of the protective layer 10. Figure 3 , 4 As shown, respectively in Figure 1 , 2 A coupling agent material filling layer 11 was added to the chip shown.

[0069] The inventors discovered that the protective layer 10 on the sidewalls of the epitaxial stack is typically thin and prone to poor film quality due to mechanical stress or contamination, resulting in decreased adhesion and poor water vapor barrier performance. Furthermore, during the subsequent LED chip encapsulation, the shrinkage or thermal stress generated during the curing of the encapsulant tends to concentrate at corners (e.g., the intersection of the passivation layer 9 and the protective layer 10). Insufficient flowability or poor wetting properties of the encapsulant during filling can lead to voids or weak interfaces on the sides of the LED chip. These factors, along with the poor film quality of the protective layer 10 on the sidewalls of the epitaxial stack, all contribute to the easy separation of the encapsulant from the LED chip surface. Therefore, the coupling agent filling layer 11 is at least disposed on the sidewalls of the protective layer 10. This not only fills the microcracks (defects smaller than 100nm) in the protective layer 10, increasing its water vapor barrier performance and overall chip reliability, but also increases the adhesion between the LED chip and the encapsulant, improving the separation of the encapsulant from the LED chip surface at the chip end. It should be understood that the exposed surfaces of the protective layer 10 and the passivation layer 9 can both be provided with a coupling agent material filling layer 11. However, considering that the encapsulant is prone to interface separation on the side of the LED chip, and for production cost considerations, it is preferable to provide the coupling agent material filling layer 11 only on the sidewall of the protective layer 10.

[0070] More preferably, along the first direction D1, the height of the coupling agent filling layer 11 is lower than the height of the surface of the first electrode 7 facing away from the substrate 1. The first direction D1 is perpendicular to the substrate 1 and points from the substrate 1 to the active layer 3. This arrangement prevents the coupling agent filling layer 11 from adhering to the surface of the first electrode 7 facing away from the substrate and affecting the bonding wires of the first electrode 7. Figure 3 As shown, along the first direction D1, H1 is the height of the coupling agent material filling layer 11, H2 is the height of the exposed surface of the first electrode 7, and H1 is less than H2.

[0071] More preferably, the material of the coupling agent filling layer 11 includes one or more of acrylate resin, polyurethane acrylate, epoxy acrylate, and silicone-modified acrylate.

[0072] Based on any of the above embodiments, in a preferred embodiment, such as Figure 1-4 As shown, the sidewalls of the epitaxial stack that contact the protective layer 10 are beveled; the angle between the beveled surface and the substrate 1 facing the active layer 3 is less than 90°. This configuration provides a better coverage angle for the protective layer 10, allowing it to better adhere to the sidewalls of the epitaxial stack, increasing water vapor resistance, and improving the overall reliability of the chip. Specifically, as... Figure 14 As shown, in this embodiment, the sidewall of the first type semiconductor layer 2 that is not covered by the passivation layer 9 is a slope. In the figure, ∠A and ∠B are the angles formed between the slope and the substrate 1 facing the surface of the active layer 3. ∠A is less than 90° and ∠B is less than 90°.

[0073] Based on any of the above embodiments, in a preferred embodiment, the adhesion between the protective layer 10 and the epitaxial stack is greater than the adhesion between the protective layer 10 and the substrate 1. Alternatively, the adhesion between the protective layer 10 and the passivation layer 9 is greater than the adhesion between the protective layer 10 and the first electrode 7 and the second electrode 8. This arrangement, due to the difference in adhesion of the protective layer 10, facilitates the removal of the protective layer 10 from areas where it is not needed during LED chip fabrication by a peeling method, eliminating the need for additional etching steps and simplifying the process. Optionally, the material of the protective layer 10 includes, but is not limited to, silicon dioxide, silicon nitride, and aluminum oxide.

[0074] Based on the same inventive concept, this application also provides a method for manufacturing a standard LED chip, which can be used to manufacture a standard LED chip of any of the above embodiments. Therefore, any parts not mentioned can be referred to each other, and the beneficial effects can also be referred to each other.

[0075] like Figure 5 As shown, a method for manufacturing a positive-mounted LED chip includes:

[0076] Step S01: Provide a substrate 1.

[0077] Step S02: As Figure 7-9 As shown, an epitaxial stack is fabricated on one side surface of substrate 1. Fabricating the epitaxial stack includes sequentially growing a first-type semiconductor layer 2, an active layer 3, and a second-type semiconductor layer 4, and fabricating a groove 5 that exposes a portion of the surface of the first-type semiconductor layer 2. Fabricating the groove 5 constitutes the fabrication of the MESA platform.

[0078] Optionally, the epitaxial stack further includes a transparent conductive layer 6, which is located on the surface of the second type semiconductor layer 4 facing away from the substrate 1. In step S02, after the second type semiconductor layer 4 is grown, the transparent conductive layer 6 and the groove 5 are fabricated. The fabrication order of the groove 5 and the transparent conductive layer 6 is not limited in this application, but is described by taking the fabrication of the groove 5 first as an example.

[0079] Step S03: As Figure 10 As shown, a first electrode 7 is fabricated; the first electrode 7 is disposed in the groove 5 and electrically connected to the first type semiconductor layer 2; a second electrode 8 is fabricated; the second electrode 8 is disposed on the surface of the second type semiconductor layer 4 facing away from the substrate 1 and electrically connected to the second type semiconductor layer 4. The fabrication order of the first electrode 7 and the second electrode 8 is not limited in this application; they can be fabricated together or separately. The second electrode 8 may only contact the transparent conductive layer 6, or a hole may be made in the transparent conductive layer 6 so that the second electrode 8 partially directly contacts the second type semiconductor layer 4.

[0080] Step S04: As Figure 11 As shown, a passivation layer 9 is fabricated, which covers part of the exposed surface of the epitaxial stack.

[0081] More preferably, the passivation layer 9 also covers a portion of the exposed surfaces of the first electrode 7 and the second electrode 8. Optionally, the passivation layer 9 covers the sidewalls of the first electrode 7 and the portion of the surface of the first electrode 7 facing away from the substrate 1. The passivation layer 9 also covers the sidewalls of the second electrode 8 and the portion of the surface of the second electrode 8 facing away from the substrate 1.

[0082] Step S05: Cut the substrate to form several independent grains. The substrate 1 is adhered to the blue film after cutting. After cutting, the blue film can be expanded to increase the spacing between the grains, facilitating subsequent steps. For example... Figure 12 As shown, the direction indicated by the arrow is the second direction D2, and cutting is performed at the position indicated by the arrow to form several independent grains. Figure 12 The diagram has been simplified, showing only two dies; in reality, a chip in wafer form comprises many dies. Figure 7-11 The drawings have been simplified, showing only the fabrication process of one die region. In reality, a chip in the wafer state comprises many dies. Figure 14 This is a schematic diagram of the structure of a single grain formed after cutting.

[0083] Step S06: A protective layer 10 is fabricated on each grain. The protective layer 10 covers the exposed sidewalls of the epitaxial stack, thus encapsulating the epitaxial stack together with the passivation layer 9. That is, in Figure 12 A protective layer is formed on the grains shown. Figure 1 or Figure 2 The image shows a properly mounted LED chip.

[0084] In this embodiment, the protective layer 10 is fabricated after the wafer is cut into individual grains using the above method. This eliminates the need for deep etching followed by passivation layer 9 deposition, thus achieving full coverage of the epitaxial stack sidewalls. In other words, in addition to the passivation layer 9, a protective layer 10 is added to cover the exposed surface and sidewalls of the epitaxial stack, preventing moisture erosion, increasing the overall reliability of the chip, and without reducing the area of ​​the light-emitting region or the number of grains that can be fabricated on the wafer.

[0085] Based on any of the above embodiments, in a preferred embodiment of this application, in step S02, as follows: Figure 8 , 11 As shown, the groove 5 surrounds the active layer 3, and the passivation layer 9 covers the exposed surface of the epitaxial stack away from the substrate 1 and the groove wall of the groove 5.

[0086] In step S06, as Figure 3 , 4 As shown, the protective layer 10 extends to the sidewall of the substrate 1 to cover the contact interface between the epitaxial stack and the substrate 1. Furthermore, the protective layer 10 and the passivation layer 9 have an overlapping region.

[0087] In step S06, as Figure 15-17 As shown, the fabrication of the protective layer 10 on each grain includes: Figure 15 As shown, each grain is flipped and transferred onto the adhesive film 12, with the substrate 1 facing away from the adhesive film 12; as Figure 16 As shown, a protective material layer is deposited to cover the exposed surface and sides of the grains; as... Figure 17 As shown, a protective material layer on the surface of substrate 1 away from the active layer 3 is removed by a film peeling process to form a protective layer 10; the adhesion of the protective layer 10 to the epitaxial stack is greater than the adhesion of the protective layer 10 to the substrate 1.

[0088] Figure 1 A schematic diagram of an embodiment of a positive-mounted LED chip fabricated using this method is shown. As can be seen from the figure, the passivation layer 9 covers the exposed surface of the epitaxial stack away from the substrate 1 and the trench wall of the groove 5. Some sidewalls around the first type semiconductor layer 2 are not protected by the passivation layer 9. The protective layer 10 covers the sidewalls of the first type semiconductor layer 2 that are not protected by the passivation layer 9 and the sidewalls around the substrate 1. The protective layer 10 also extends toward the passivation layer 9 to cover the part of the sidewalls of the passivation layer 9 near the substrate 1 to form an overlapping area. The height of the protective layer 10 along the first direction D1 is lower than the height of the surface of the first electrode 7 away from the substrate 1 along the first direction D1. The first direction D1 is perpendicular to the substrate 1 and points from the substrate 1 toward the active layer 3.

[0089] Alternatively, in step S06, such as Figure 18-20 As shown, the fabrication of the protective layer 10 on each grain includes: Figure 18 As shown, each grain is transferred onto the adhesive membrane 12, and the substrate 1 contacts the adhesive membrane 12; as Figure 19 As shown, a protective material layer is deposited to cover the exposed surface and sides of the grains; as... Figure 20 As shown, a film-peeling process is used to remove the protective material layer on the surface of the first electrode 7 and the second electrode 8 away from the substrate 1 to form a protective layer 10; the adhesion between the protective layer 10 and the passivation layer 9 is greater than the adhesion between the protective layer 10 and the electrode.

[0090] Figure 2 A schematic diagram of an embodiment of a positive LED chip manufactured using this method is shown. As can be seen from the figure, the passivation layer 9 covers the exposed surface of the epitaxial stack away from the substrate 1 and the trench wall of the groove 5. Some sidewalls around the first type semiconductor layer 2 are not protected by the passivation layer 9. The protective layer 10 covers the sidewalls around the first type semiconductor layer 2 that are not protected by the passivation layer 9 and the sidewalls around the substrate 1. Furthermore, the protective layer 10 completely covers the passivation layer 9 to form an overlapping area.

[0091] In the two different methods described above for fabricating the protective layer 10 on each grain, the adhesive film 12 can be made of polyimide-based adhesive film, silicone-based adhesive film, ceramic-based adhesive material, etc. The temperature used to fabricate the protective layer 10 must be within the temperature range that the adhesive film 12 can withstand. For example, a polyimide-based adhesive film can withstand a maximum temperature of 400℃ for long-term use, and higher temperatures for short-term use. A silicone-based adhesive film can withstand a maximum temperature of 300℃ for long-term use (up to 350℃ for short-term use). Ceramic-based adhesive materials have a temperature resistance of over 500℃. A suitable adhesive film 12 can be selected according to actual needs. The film removal process can use either a blue film or a white film to remove the unwanted protective material layer.

[0092] Based on any of the above embodiments, in a preferred embodiment, in step S05, cutting to form a plurality of independent grains includes: cutting along a second direction D2 using a laser stealth cutting method; the second direction D2 is perpendicular to the substrate 1 and points from the active layer 3 to the substrate 1; during the cutting process using the laser stealth cutting method, there are at least two focal points, and the laser energy used at different focal points along the second direction D2 gradually decreases, so that the sidewall of the epitaxial stack in contact with the protective layer 10 is a slope; the angle between the slope and the substrate 1 facing the surface of the active layer 3 is less than 90°. Figure 13 for Figure 12 A magnified view of part A in the image. Figure 13 The black dots in the image exemplify the location of each focal point.

[0093] In this embodiment, during the laser stealth cutting process, there are at least two focal points, and the laser energy used at different focal points along the second direction D2 gradually decreases, so that the sidewall of the epitaxial stack in contact with the protective layer 10 is a slope; the angle between the slope and the substrate 1 facing the surface of the active layer 3 is less than 90°, which provides a better coverage angle for the protective layer 10, so that the protective layer 10 can better cover the sidewall of the epitaxial stack, providing overall chip reliability, and the slope can be formed by changing the laser energy of different focal points, which is a simple method.

[0094] Based on the above embodiments, in a preferred embodiment of this application, after forming a protective layer 10 on each grain, an insulating coupling agent material filling layer 11 is further formed; the coupling agent material filling layer 11 is at least disposed on the sidewall of the protective layer 10. Figure 6 As shown, after step S06, step S07 is included: fabricating a coupling agent material filling layer 11, which is at least disposed on the sidewall of the protective layer 10. Specifically, fabricating the coupling agent material filling layer 11 in step S07 includes: coating at least the sidewall of the protective layer 10 with coupling agent material and curing it to form the coupling agent material filling layer 11. Ultraviolet irradiation can be used to cure the coupling agent material. Figure 1 , 2The upright LED chip shown is formed by fabricating a coupling agent material filling layer 11. Figure 3 , 4 The image shows a properly packaged LED chip.

[0095] In this implementation, since the protective layer 10 covers the sidewall of the epitaxial stack, and this sidewall is a cut surface, the protective layer 10 is usually thin and prone to poor film quality, decreased adhesion, and poor water vapor barrier performance due to mechanical stress or contamination. Furthermore, during the subsequent LED chip encapsulation process, the shrinkage stress or thermal stress generated during the curing of the encapsulant tends to concentrate at corners (e.g., the intersection of the passivation layer 9 and the protective layer 10); the encapsulant may form voids or weak interfaces on the side of the LED chip due to insufficient flowability or poor wetting properties during filling. These factors, along with the poor film quality of the protective layer 10 on the sidewall of the epitaxial stack, all contribute to the easy separation of the encapsulant from the LED chip side. Therefore, the coupling agent filling layer 11 is at least disposed on the sidewall of the protective layer 10. This not only fills the microcracks (defects smaller than 100nm) in the protective layer 10, increasing its water vapor barrier performance and overall chip reliability, but also improves the separation of the encapsulant from the LED chip side at the chip end.

[0096] More preferably, along the first direction D1, the height of the coupling agent material filling layer 11 is lower than the height of the surface of the first electrode 7 facing away from the substrate 1; the first direction D1 is perpendicular to the substrate 1 and points from the substrate 1 to the active layer 3. This arrangement prevents the coupling agent material filling layer 11 from adhering to the exposed surface of the first electrode 7 and affecting the bonding wires of the first electrode 7. Specifically, as... Figure 3 As shown, along the first direction D1, H1 is the height of the coupling agent material filling layer 11, H2 is the height of the exposed surface of the first electrode 7, and H1 is less than H2.

[0097] Optionally, to avoid applying the coupling agent material to the surface of the first electrode 7 facing away from the substrate 1, when applying the coupling agent material, the front side (electrode side) of the LED chip faces upward and the back side (substrate 1 side) adheres to the blue film.

[0098] More preferably, the coupling agent material filling layer 11 includes one or more of acrylate resin, polyurethane acrylate, epoxy acrylate, and silicone-modified acrylate.

[0099] Based on the same inventive concept, this application also provides a light-emitting device, which includes a standard-mount LED chip of any of the above embodiments. Further, the light-emitting device includes a display device, which includes a standard-mount LED chip of any of the above embodiments. Of course, the standard-mount LED chip in the light-emitting device can also be manufactured using the manufacturing method of the standard-mount LED chip of any of the above embodiments.

[0100] Those skilled in the art should understand that in the disclosure of this utility model, the terms "lateral", "longitudinal", "upper", "lower", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings. They are only for the convenience of describing this utility model and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, the above terms should not be construed as a limitation of this utility model.

[0101] It should be noted that the various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other.

[0102] The above description of the disclosed embodiments enables those skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A standard-mount LED chip, characterized in that, include: Substrate; An epitaxial stack is located on one side surface of the substrate; the epitaxial stack includes a first type semiconductor layer, an active layer, and a second type semiconductor layer; the epitaxial stack has a groove exposing a portion of the surface of the first type semiconductor layer; A first electrode is disposed in the groove and electrically connected to the first type of semiconductor layer; The second electrode is disposed on the surface of the second type semiconductor layer away from the substrate and is electrically connected to the second type semiconductor layer. A passivation layer that covers a portion of the exposed surface of the epitaxial stack; A protective layer covers the exposed sidewalls of the epitaxial stack to encapsulate the epitaxial stack together with the passivation layer.

2. The upright LED chip as described in claim 1, characterized in that, It also includes an insulating coupling agent material filling layer, which is at least located on the sidewall of the protective layer.

3. A standard-mount LED chip as described in claim 2, characterized in that, Along the first direction, the height of the coupling agent material filling layer is lower than the height of the surface of the first electrode facing away from the substrate; The first direction is perpendicular to the substrate and extends from the substrate toward the active layer.

4. A standard-mount LED chip as described in claim 1, characterized in that, The groove surrounds the active layer, and the passivation layer covers the exposed surface of the epitaxial stack away from the substrate and the groove wall; the protective layer and the passivation layer have overlapping areas.

5. A standard-mount LED chip as described in claim 1, characterized in that, The protective layer extends to the sidewall of the substrate to cover the contact interface between the epitaxial stack and the substrate.

6. A standard-mount LED chip as described in claim 1, characterized in that, The sidewall of the epitaxial layer that contacts the protective layer is an inclined surface; The angle between the inclined plane and the substrate facing the active layer surface is less than 90°.

7. A standard-mount LED chip as described in claim 4, characterized in that, The protective layer covers a portion of the sidewall of the passivation layer near the substrate, forming an overlapping area; Alternatively, the protective layer may cover the entire passivation layer to form an overlapping area.

8. A standard-mount LED chip as described in claim 1, characterized in that, The passivation layer also covers part of the exposed surfaces of the first and second electrodes.

9. A light-emitting device, characterized in that, Includes a standard-mounted LED chip as described in any one of claims 1-8.

10. A light-emitting device as described in claim 9, characterized in that, The light-emitting device includes a display device, and the display device includes the aforementioned type of upright LED chip.

Images