Detector device

Abstract

Embodiments of the present application provide a detector device including a photon detector and a multilayer reflector. The photon detector includes a substrate, an isolation structure in a first side of the substrate, a guard ring adjacent to the isolation structure and in the first side of the substrate, a sensor node in the first side of the substrate, the guard ring between the sensor node and the isolation structure, a shared node in the first side of the substrate, the shared node between the guard ring and the isolation structure, an isolation extension structure in a second side of the substrate opposite the first side, the isolation extension structure extending from the second side to the isolation structure. The multilayer reflector is on the first side of the substrate. Using the multilayer reflector can improve collection of photons in an avalanche region.

Description

Technical Field

[0001] Embodiments of this utility model relate to a detector device, and more particularly to a detector device including a single-photon avalanche diode. Background Technology

[0002] The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advancements in IC materials and design have yielded several generations of ICs, each with smaller and more complex circuits than the previous one. Throughout IC development, functional density (the number of interconnected devices per chip area) has generally increased, while shape geometry (the smallest component (or line) that can be created using manufacturing processes) has decreased. Miniaturization typically brings benefits such as increased production efficiency and reduced associated costs. This size reduction also increases the complexity of handling and manufacturing ICs. Utility Model Content

[0003] An embodiment of this utility model provides a detector device including a photon detector and a multilayer reflector. The photon detector includes a substrate, an isolation structure in a first side of the substrate, a protective ring adjacent to the isolation structure and in the first side of the substrate, a sensor node in the first side of the substrate, a shared node between the sensor node and the isolation structure in the first side of the substrate, an isolation extension structure between the shared node and the isolation structure in a second side of the substrate opposite to the first side, the isolation extension structure extending from the second side to the isolation structure. The multilayer reflector is located on the first side of the substrate.

[0004] Based on the above, the detector device of this embodiment can realize the development of ultra-high resolution images in extreme ultraviolet (EUV) inspection systems. Utilizing single-photon avalanche diode (SPDB) photon counting can mitigate gain noise and circuit noise caused by binarization of the detector response. Most SPDBs require a trade-off between efficiency and wider bandwidth; however, in this embodiment, the EUV SPDB operates online with EUV light having a 13.5 nm bandwidth, which improves efficiency. Multifunctional systems can use SPDB-based detectors to incorporate both detection and monitoring functions.

[0005] To make the above features and advantages of the embodiments of this utility model more apparent and understandable, specific embodiments are described below in conjunction with the accompanying drawings. Attached Figure Description

[0006] Figure 1A , Figure 1B and Figure 1CThis is a schematic plan view of a portion of an IC device according to an embodiment of this disclosure.

[0007] Figure 2 It is a layout diagram of the various areas of the IC device according to this disclosure.

[0008] Figures 3A-3D This is a schematic diagram of detector pixels according to various embodiments.

[0009] Figure 4 This is a schematic cross-sectional side view of a detector device according to various embodiments.

[0010] Figure 5 This is a detailed side view of a detector device according to various embodiments.

[0011] Figure 6A and Figure 6B This is a detailed schematic diagram of a conductive deep isolation trench according to various embodiments.

[0012] Figure 7A-7N These are views of various embodiments of IC devices at various stages of manufacturing, based on various aspects of this disclosure.

[0013] Figure 8 This is a schematic diagram of a system for detecting EUV photons according to various embodiments.

[0014] Figure 9 This is a flowchart of a method for forming an IC device according to various embodiments.

[0015] Figure 10 This is a flowchart of a method for detecting photons according to various embodiments. Detailed Implementation

[0016] The following disclosure provides numerous different embodiments or examples for implementing various features of this disclosure. Specific examples of components and arrangements are described below to simplify this disclosure. Of course, these are merely examples and are not intended to limit the scope of this disclosure. For example, in the following description, the first feature being formed "on" or "on" a second feature may include embodiments where the first and second features are formed in direct contact, or embodiments where an additional feature is formed between the first and second features such that the first and second features are not in direct contact. Furthermore, component numbers and / or letters may be repeated in various examples of this disclosure. Such repetition is for simplification and clarity of description of this disclosure, and is not intended to limit the relationship between various embodiments and / or configurations.

[0017] Furthermore, for ease of explanation, spatially relative terms such as "below," "under," "lower," "above," and "upper" may be used herein to describe the relationship between one component or feature shown in the figures and another component or feature. In addition to the orientations depicted in the figures, these spatially relative terms also cover different orientations of the device during use or operation. The device may have other orientations (rotated 90 degrees or in other orientations), and the spatially relative descriptions used therein can be interpreted in the same manner.

[0018] Terms representing relative degrees, such as “about” or “substantially”, should be interpreted as understood by one of ordinary skill in the art in light of current technical specifications.

[0019] The terms “first,” “second,” “third,” etc., may be used in this document to describe a sequence of events or a sequential order of components, but may be interchanged or changed in some contexts. For example, a second layer may form on top of a first layer (e.g., sequentially following a first layer), but in some contexts, the first layer may be referred to as “second layer,” “third layer,” “fourth layer,” or similar, and the second layer may be referred to as “first layer,” “third layer,” “fourth layer,” or similar.

[0020] The term "surround" is used in this document to describe, for example, completely or partially enclosing another component or structure in three dimensions. For instance, a first structure might "surround" a second structure on four lateral sides (e.g., left, right, front, and back), rather than on two vertical sides (e.g., top and bottom). In other examples, a first structure might partially enclose a second structure, for example, by surrounding three sides (e.g., top, front, and back) while exposing other sides (e.g., left, right, and bottom).

[0021] One or more source / drain regions may refer to the source or drain individually or together, depending on the context.

[0022] This disclosure generally relates to semiconductor devices, and more specifically to backside illuminated (BSI) single photon avalanche diodes (SPADs) for extreme ultraviolet (EUV) photon detection, and related methods of manufacture and use.

[0023] As semiconductor manufacturing technology advances towards the EUV era, the challenges of mask inspection have increased dramatically, making it difficult to use deep ultraviolet (DUV) laser sources as inspection light sources. DUV sources face three main difficulties: limited resolution, inability to detect phase defects, and inability to perform thin-film inspection.

[0024] First, the resolution of DUV is limited by a physical formula that is proportional to its wavelength. Specifically, EUV, with a wavelength of approximately 13.5 nm, offers about 14 times higher resolution than DUV. Second, DUV cannot expose phase defects within multilayer masks or "photomasks," which can distort the photoresist pattern on the wafer during exposure. Third, choosing silicon as the thin film to improve transmission levels in EUV systems absorbs DUV wavelengths, thus limiting the development of particle protection. Without addressing these challenges, high-volume manufacturing (HVM) may not be feasible.

[0025] Currently, the power of EUV light sources used for photochemical inspection is constantly improving. However, the development of EUV sensors remains limited. Inspection devices (such as time-delay integration (TDI) sensors, charge-coupled device (CCD) sensors, and complementary metal-oxide-semiconductor (CMOS) sensors) focus on visible or infrared wavelengths to meet the growing demands of automotive technologies such as autonomous vehicles. In many EUV sensors, the signal-to-noise ratio (SNR) is limited, which can interfere with defect detection, or so-called "defect inspection." Poor SNR affects the sensitivity of detection algorithms, and if sensitivity is tightened to compensate for the poor SNR, false alarms in defect detection increase due to noise, thus increasing the likelihood of inspection failures.

[0026] In the embodiments disclosed herein, a detector device with high resolution is provided. A single-photon CMOS device (e.g., SPAD) is provided that can detect a single EUV photon and significantly reduce noise through device and associated analog setting selection. The device can be used as an EUV photon detector for inspecting a system, or as a monitoring sensor for verifying source power intensity and / or depth of focus on the reflector, thereby improving real-time monitoring capabilities.

[0027] The detector device offers several advantages. It enables the development of ultra-high resolution images in EUV inspection systems. Utilizing SPAD photon counting mitigates gain noise and circuit noise caused by binarization of the detector response. While most SPADs require a trade-off between efficiency and wider bandwidth, in this embodiment, the EUV SPAD operates online with EUV light having a 13.5 nm bandwidth, which improves efficiency. Multifunctional systems can use SPAD-based detectors to incorporate both detection and monitoring capabilities. It should be noted that although embodiments have been described with reference to EUV inspection and monitoring, the SPAD and detector devices described herein can also be used in fields such as deep space laser communications, microscopy, astronomy, and other similar applications.

[0028] Figure 1A , Figure 1B and Figure 1C This is a schematic plan view of a portion of a detection or detector apparatus 10 according to various embodiments. Figure 1A-1C The view in the XY plane is depicted.

[0029] refer to Figure 1A A single-photon avalanche diode (SPAD) 100 is located on and / or within the substrate 11 of the detector device 10 (also referred to as the image sensor 10). In some embodiments, the detector device 10 or the image sensor 10 is a sensor region of an integrated device. For example, the sensor region may occupy a portion of the substrate 11, and other circuitry (e.g., driving and / or processing) may occupy another adjacent portion of the substrate 11. The substrate 11 may comprise one or more layers of dopants doped with a first and / or second conductivity type (e.g., p-type and / or n-type). In some embodiments, the substrate 11 is a silicon substrate doped with p-type or n-type dopants. The bulk doping concentration of the substrate 11 may be approximately 1 e 15 / cm 3 To about 1e 17 / cm 3 The degree of doping, and the additional doped region exceeding the bulk material, can be embedded in the bulk material of substrate 11. (Refer to...) Figure 5 Substrate 11 is described in more detail.

[0030] like Figure 1AAs shown, SPAD 100 can be arranged to form multiple rows and columns of an array. SPAD 100 can have a consistent size in a first direction (e.g., the X-axis direction) and a second direction (e.g., the Y-axis direction). For example, the width of SPAD 100 can be uniform across the entire array, and the length of SPAD 100 can be uniform across the entire array. In some embodiments, the width and / or length of SPAD 100 can range from about 5 micrometers (μm) to about 30 μm. The distance between SPAD 100 can be uniform across the entire array. For example, the spacing and / or pitch of SPAD 100 in each row can be uniform in the Y-axis direction, and the spacing and / or pitch of SPAD 100 in each row can be uniform in the X-axis direction. The SPAD 100 of the array can be associated with pixel merging and / or one or more algorithms.

[0031] exist Figure 1B In this process, SPADs of different sizes, such as 100A, 100B, 100C, 100D, and 100E (instead of SPAD 100 of uniform size), can be arranged on the substrate 11. SPADs 100A, 100B, 100C, 100D, and 100E can be collectively referred to as SPAD 100A-100E. Figure 1B Five SPADs 100A-100E of different sizes are depicted, but in some embodiments, fewer or more SPADs may be included. SPAD 100E may be larger than SPAD 100D, SPAD 100D may be larger than SPAD 100C, SPAD 100C may be larger than SPAD 100B, and SPAD 100B may be larger than SPAD 100A. SPAD 100E may be arranged to the right of SPAD 100D, SPAD 100D may be arranged to the right of SPAD 100C, SPAD 100C may be arranged to the right of SPAD 100B, and SPAD 100B may be arranged to the right of SPAD 100A. In some embodiments, SPADs 100A-100E may be arranged with sizes (e.g., width and / or length) increasing from left to right or from right to left. In some embodiments, the size of SPAD 100A-100E may increase along one or more of directions X and Y from the center of substrate 11 (or the sensor region of substrate 11) to the periphery of substrate 11 (or the sensor region). Figure 1C An example of variation along the direction X is depicted. Figure 1CAn image sensor 10B including SPAD 100A-100E is depicted, the size of SPAD 100A-100E gradually decreasing from the center of the image sensor 10B to the periphery of the image sensor 10B along the X-axis direction.

[0032] In some embodiments, SPAD 100 or 100A-100E can be used with Figure 1A-1C The different arrangements shown are illustrated. For example, SPADs of different sizes (e.g., different widths, lengths, spacings, pitches, or combinations thereof) may be arranged on the image sensor 10 (or 10A or 10B) along the X-axis, Y-axis, or both in a uniform or non-uniform, periodic or aperiodic manner. For example, a pair of SPAD rows may have a first row comprising a first SPAD with a uniform first width and a first length, and a second row comprising a second SPAD with a uniform second width and a second length different from the first width and the first length. An array may include two or more of the row pairs described above. In another example, the first or second row, or both, may comprise SPADs with inconsistent widths and lengths along the respective rows. In yet another example, instead of a pair of rows, an array of three, four, or more rows may be arranged, wherein the first, second, third, fourth, or additional rows each have SPADs of uniform or non-uniform size within the respective row.

[0033] Each of SPAD 100, 100A-100E can be included in pixels of image sensors 10, 10A, 10B, respectively. In operation, for example during image capture for inspecting an EUV photomask, a single line of SPAD 100 or 100A-100E can perform the capture function, while other lines of SPAD 100 or 100A-100E can be used for calibration, gain feedback, or both. For example, a single line of SPAD 100 extending along the X-axis can be used to capture image data associated with the EUV photomask, while other lines of SPAD 100 can be used to calibrate the single line. In some embodiments, two or more lines of SPAD 100 or 100A-100E can be used to capture image data.

[0034] Figure 2 Depicting Figure 1A A detailed view of region 20 of the depicted image sensor 10. Region 20 includes at least four SPADs 100, each SPAD 100 having a first doped region 102 and a second doped region 104, the second doped region 104 being adjacent to the first doped region 102 and offset from the first doped region 102 along at least four sides of the first doped region 102. In some embodiments, the first doped region 102 has a doping density greater than about 1e 16 / cm 3The n-type doped region has a doping concentration of [value missing], and the second doped region 104 has a doping concentration exceeding approximately 1e[value missing]. 16 / cm 3 The p-type doped region with a certain doping concentration. In some embodiments, such as Figure 2 As shown, the first doped region 102 is a substantially square region that may have chamfered edges. Although for simplicity... Figure 2 Not specifically shown, but each SPAD 100 can be isolated from adjacent SPAD 100 by one or more isolation structures, which will be referred to Figure 5 See Figure 6 for a more detailed description.

[0035] Figures 3A-3D These are schematic diagrams of SPAD 300S, 300R, 300C, and 300H with different shapes according to various embodiments. SPAD 300S, 300R, 300C, and 300H can be used as a reference. Figure 1A-2 Examples of SPAD 100 or SPAD 100A-100E described above. Figure 3A A SPAD 300S with a square shape is depicted, where its width x2 is equal to its length x1. Figure 3B The SPAD 300R is depicted with a rectangular shape, where its length x1 exceeds its width x2. For example, the width x2 may be less than approximately 3 / 4 of the length x1. Figure 3C The SPAD 300C is depicted as having a circular shape with a diameter D. Figure 3D A SPAD 300H with a polygonal shape is depicted, such as a hexagonal shape with a maximum value / maximum diameter D. The width x2, length x1, diameter D, and maximum diameter D described above can each range from approximately 5 μm to approximately 30 μm. In some embodiments, SPAD 100 or SPAD 100A-100E has... Figures 3A-3D The shapes depicted are different. For example, the polygonal shape of SPAD 300H can be a pentagon, an octagon, etc. In some embodiments, the shape of SPAD 100 or SPAD 100A-100E can refer to the shape of the first doped region 102. That is, replacing Figure 2The square first doped region 102 shown may have a rectangular, circular, polygonal, or other similar shape. In some embodiments, one or more of SPAD 100 or SPAD 100A-100E may have a shape different from that of one or more of SPAD 100, 100A-100E (e.g., circular). When image sensors 10, 10A, 10B are incorporated into microscope devices, astronomical devices, etc., a circular shape may be advantageous for image sensors 10, 10A, 10B. A hexagonal shape may facilitate a more compact sensor layout and increased pixel density for image sensors 10, 10A, 10B.

[0036] Figure 4 This is a schematic diagram of a portion of an image sensor device 40 according to various embodiments. Figure 4 The portion of the image sensor device 40 in the XZ plane is depicted. The image sensor device 40 may include an image sensor 400 stacked with an integrated circuit (IC) 410. The image sensor device 40 includes one or more SPADs 450, which are similar in most respects to Figure 1A-3D The SPADs 100, 100A-100E, 300S, 300R, 300C, and 300H mentioned herein are referenced. Integrated circuit 410 may be or include application-specific integrated circuits (ASICs), which may include logic circuits such as processor circuits, memory circuits, and data interface (I / O) circuits.

[0037] exist Figure 4In this design, a SPAD-based image sensor 400 can be used to perform a first set of functions, and an ASIC 410 can be used to perform a different second set of functions. For example, the image sensor 400 can detect photons and perform avalanche multiplication, temporal resolution, and pixel-level processing during operation. Photon detection can be a function of the SPAD-based image sensor 400 and includes the detection of a single photon. Each SPAD 450 of the image sensor 400 can act as a highly sensitive photosensor, capable of generating a detectable signal by absorbing a single photon. When a photon is detected, the detecting SPAD 450 initiates an avalanche multiplication process, amplifying the initial signal to a detectable level. The SPAD sensor 400 provides improved timing resolution, making it suitable for applications that benefit from precise photon arrival times, such as time-of-flight (ToF) measurements and fluorescence lifetime imaging. The SPAD sensor 400 can integrate basic pixel-level processing functions, such as time gating or photon counting, to improve the efficiency of photon detection and signal processing.

[0038] The ASIC 410 can handle complex signal processing, including noise reduction, signal amplification, and data conversion from analog to digital formats, each of which can be performed by associated circuitry, such as noise reduction circuitry, signal amplification circuitry, and data conversion circuitry (e.g., analog-to-digital conversion circuitry). This processing facilitates the preparation of raw data captured by the SPAD sensor 400 for further analysis. The ASIC 410 manages data streams, including the storage, buffering, and transmission of image data generated by the image sensor 400. This may include organizing data from multiple SPAD 450 pixels, compressing data (if beneficial), and preparing data for output. The ASIC 410 controls the timing and synchronization of the image sensor 400's operation, including pulse generation for active illumination (if used) and synchronization with external devices. This is highly advantageous for applications such as 3D imaging and ranging, where accuracy between emission and detection can improve performance. Efficient power management is highly beneficial for portable or battery-powered devices. The ASIC 410 improves power efficiency by regulating the power supply of the SPAD sensor 400 and implementing power-saving modes. The ASIC410 provides an interface for communicating with external devices, such as calculators, displays, or other sensors. This includes implementing data transfer protocols and receiving instructions from external processors or controllers.

[0039] In some embodiments, although not described for the sake of simplicity... Figure 4While described in detail, ASIC 410 may include one or more integrated devices, such as metal-oxide-semiconductor (MOS) transistors, capacitors, resistors, sensors, diodes, memory devices, and combinations thereof. MOS transistors may include field-effect transistors (FETs), which can be planar FETs, finned FETs, nanostructured FETs, and combinations thereof. Nanostructured FETs may include nanosheet FETs (NSFETs), nanowire FETs (NWFETs), gate-all-around FETs (GAAFETs), etc.

[0040] Image sensor 400 may include a substrate 110 having SPAD 450 therein and one or more pads 430, 440 thereon or therein. Back-side passivation layer 180 may be located on the back side of substrate 110. Front-side interconnect structure 460 may be located on the front side of substrate 110.

[0041] The front interconnect structure 460 may include metallization structures (464, 466) embedded in one or more dielectric layers 462. The metallization structures (464, 466) may include conductive traces 464 and vias 466. The metallization structures (464, 466) may be electrically coupled to pads (430, 440) and SPAD 450 to provide electrical connections therebetween.

[0042] For example, the first pad 430 can be coupled to the SPAD 450 via a metallization structure (464, 466) located only in the dielectric layer 462 of the front interconnect structure 460. The first pad 430 can receive a high voltage HV from a first power supply external to the image sensor 400. In some embodiments, during operation, the high voltage HV can be transferred through the front interconnect structure 460 to the second doped region 454 of the SPAD 450, such as... Figure 4 As shown.

[0043] The second pad 440 can be coupled to the SPAD 450 via the front-side interconnect structure 460 included in the ASIC 410 and the metallization structures (464, 466) of the additional metallization structures (414, 416). The second pad 440 can receive a power supply voltage V from a second power supply external to the image sensor 400. DD In some embodiments, during operation, the power supply voltage V DD It can be transferred to the first doped region 452 of SPAD 450 through the interconnection within the front internal interconnection structure 460 and ASIC 410.

[0044] In some embodiments, the image sensor 400 and the ASIC 410 are bonded to each other. For example, the image sensor 400 and the ASIC 410 can be bonded to each other by a hybrid bonding, which includes at least one metallographic bond 420 between the metallized structures of the image sensor 400 and the metallized structures of the ASIC 410. Additional bonding (e.g., dielectric bonding) may exist between the respective dielectric layer of the image sensor 400 and the ASIC 410 adjacent to the metallographic bond 420.

[0045] Passivation layer 180 may be located on the back surface of substrate 110, including SPAD 450. In some embodiments, passivation layer 180 may include SiN, SiC, SiON, SiO2, SiCN, polymers, or the like, selected for protective, optical, and electrical properties. For example, passivation layer 180 may be an insulating layer that prevents leakage current and oxidation of the underlying layer (e.g., substrate 110). In some embodiments, passivation layer 180 may be a monolayer epitaxially grown and providing a capping function. Passivation layer 180 may have a thickness greater than about 10 nm or less than about 5 nm. For example, when the radiance of the EUV light source is about 50 W / mm². 2 Sr up to approximately 200W / mm 2 When Sr is within the range, the thickness of the passivation layer 180 can exceed approximately 10 nm. This is when the radiance of the EUV light source is less than approximately 50 W / mm². 2 When using Sr, the thickness of the passivation layer 180 can be less than 5 nm.

[0046] Passivation layer 180 provides a number of beneficial functions designed to enhance the performance, lifetime, and reliability of image sensor 400. Passivation layer 180 provides a protective barrier against environmental factors such as moisture, oxygen, and contaminants that may damage image sensor 400. Considering the thinning processes in the fabrication of BSI sensor 400, the back-side surface may be exposed to the environment; therefore, this protection helps maintain the integrity of the sensitive areas of SPAD 450. The back-side surface of the silicon wafer or substrate 110 may introduce trapped states, which can adversely affect the performance of SPAD 450 by increasing dark counts or reducing quantum effects. Passivation layer 180 helps mitigate these effects by smoothing the surface and reducing the number of surface defects and trapped states. For BSI SPAD sensors (such as image sensor 400), improving the pathway of light to the active region is beneficial. Passivation layer 180 can be selected to improve the optical properties of the back-side surface, including enhancing reflectivity or reducing scattering, thereby increasing the number of photons reaching the corresponding avalanche regions of SPAD 450. This is particularly advantageous for improving sensitivity and efficiency. The passivation layer 180 also serves as electrical isolation, preventing leakage current and ensuring the retention of the electrical characteristics of the SPAD 450. This isolation helps maintain the performance of the image sensor 400 over time and under varying environmental conditions. During manufacturing and operational use, the image sensor 400 may be subjected to mechanical stresses that could affect its performance. The passivation layer 180 helps manage these stresses, improving the mechanical stability of the image sensor device 400.

[0047] Figure 5 This is a schematic diagram depicting a portion of an image sensor device 50 according to various embodiments. The image sensor device 50 may be a reference... Figure 4 The embodiments of the image sensor device 40 are described, and in most respects may be similar to the image sensor device 40.

[0048] Image sensor device 50 may include image sensor structure 55, system-on-a-chip (SOC) 500, and ASIC 510. ASIC 510 may be similar to ASIC 410 in most respects, and will not be described further here. In some embodiments, SOC 500 includes image sensor structure 55 and pads 530, 540 thereon. SOC 500 may include similar references. Figure 4 The interconnect structure of the front internal interconnect structure 460 described herein. In some embodiments, the SOC 500 includes... Figure 4The ASIC 500 may include one or more of the functions described in ASIC 410. For example, ASIC 500 may include one or more image sensor structures 55, pads (530, 540), analog-to-digital converters (ADCs), digital signal processors (DSPs), memory circuitry, control logic circuitry, interface circuitry, power management unit (PMU) circuitry, and the like, and ASIC 510 may include one or more higher-order image processing circuitry, additional interface circuitry, control logic (e.g., for focusing lens assemblies), security circuitry, and the like. Pads (530, 540) may be similar to pads (430, 440) in most respects.

[0049] The image sensor structure 55 includes features that improve resolution, reduce gain noise and circuit noise, and increase efficiency.

[0050] The image sensor structure 55 may include one or more SPADs 550, a multilayer reflector or "reflective multilayer" 570, and a passivation or capping layer 572. The multilayer reflector 570 may, for example, be a structure coated on the front side 550f of the SPAD 550. The capping layer 572 may, in most respects, be similar to the referenced layer. Figure 4 The passivation layer 180 described herein may be an epitaxial growth layer located on the back side 550b of the SPAD 550.

[0051] The SPAD 550 is similar to the reference in most respects. Figure 4 The SPAD 450 described herein. See reference [reference needed]. Figure 5 The SPAD 550 is described in more detail.

[0052] exist Figure 5 In this embodiment, SPAD 550 may include sensor node 552 in substrate 560. SPAD 550 may also include shared node 554, guard ring 556, isolation structure 558, and isolation extension structure 5600.

[0053] Sensor node 552 may be a region of substrate 560, said region being heavily doped with a dopant of a first conductivity type (e.g., n-type), such as Figure 5 The designation "N+" indicates this. Sensor node 552 may be formed in substrate 560 and may extend downward (e.g., inward) from the front side 550f of SPAD 550. In some embodiments, the doping concentration of sensor node 552 is greater than about 1e. 18 / cm 3 The extent, for example, about 1e 20 / cm 3 .

[0054] In the fabrication of BSI SPADs (e.g., SPAD 550), n-type dopants are introduced into sensor node 552 to facilitate an electron-induced avalanche multiplication process. The choice of n-type dopant can depend on the semiconductor material (e.g., silicon) of the substrate 560 and the selected electrical properties. n-type dopants for silicon can include phosphorus, arsenic, antimony, etc. Phosphorus facilitates the easy provision of electrons to the conduction band of silicon, thereby generating free carriers (electrons) for conduction. Arsenic is another n-type dopant that produces a high concentration of electrons in silicon and facilitates rapid diffusion rates and the establishment of highly doped n+ regions. Although antimony is less common than phosphorus and arsenic, it can be used where slower diffusion is advantageous for the doping process. The doping process can be controlled to obtain a concentration and depth distribution favorable for the operation of the SPAD 550. n-type doping facilitates the formation of multiplication regions 566, where avalanche breakdown occurs in response to incident photons.

[0055] A shared node 554 is formed in a substrate 560 and may extend downward (e.g., inward) from the front side 550f of the SPAD 550. In some embodiments, the shared node 554 may be a region of the substrate 560 heavily doped with a dopant of a second conductivity type (e.g., p-type) that is different from or opposite to the first conductivity type. The shared node 554 may be... Figure 5 The term "P+" is used to indicate that it is a heavily doped p-type region. In some embodiments, the doping concentration of the shared node 554 is greater than approximately 1e 18 / cm 3 The extent, for example, about 1e 20 / cm 3 .

[0056] like Figure 5 As shown, sensor node 552 and shared node 554 are adjacent to the front side 550f of SPAD 550. The multiplication region 566 (or "avalanche region") is located below sensor node 552 in the Z-axis direction, as shown... Figure 5As shown. The guard ring 556 may extend further downward from the front side 550f of the SPAD 550 than the multiplication region 566. The guard ring 556 may have a width sufficient to prevent premature breakdown and ensure a uniform electric field distribution. In at least some embodiments, the sensor node 552 may have a width (in the X-axis direction) between 0.1 μm and 10.0 μm (inclusive) and a height (in the Z-axis direction) less than or equal to 0.5 μm. The shared node 554 may have a width between 0.1 μm and 1.0 μm (inclusive) and a height less than or equal to 0.5 μm. The guard ring 556 may have a width between 0.1 μm and 5.0 μm (inclusive) and a height between 0.5 μm and 1.5 μm (inclusive). The multiplication region 566 may have a width between 0.5 μm and 10.0 μm (inclusive) and a height between 0.1 μm and 1.0 μm (inclusive).

[0057] Biasing the BSI SPAD 550 for photon detection may involve applying a reverse voltage to the PN junction of the diode to initiate and sustain the avalanche multiplication process upon photon detection. The SPAD 550 can be reverse biased, meaning a positive voltage (e.g., the supply voltage V at pad 540) is required. DD A bias voltage is applied to the n-type region (e.g., sensor node 552) and a negative voltage (e.g., a high voltage HV at pad 530) is applied to the p-type region (e.g., shared node 554), thereby generating an electric field at the junction. This bias voltage is set at a level higher than the diode's breakdown voltage; this state is called "Geiger mode." The breakdown voltage can be the minimum reverse voltage at which the diode junction can conduct a large reverse current in the absence of light. For photon detection, the bias voltage is set slightly above this threshold; this state is called "over-biasing," which puts the diode in a metastable state, ready for avalanche multiplication upon photon arrival. Because the SPAD 550's bias voltage is higher than its breakdown voltage, the SPAD 550's gain can be very high via impact ionization, allowing a single photon to trigger a rapid avalanche current exceeding approximately 10 microamperes or more.

[0058] When a photon enters the SPAD through the backside 550b, if the photon has sufficient energy, it can generate an electron-hole pair, such as an electron 568, in the substrate 560 of the SPAD 550. The resulting charge carriers (e.g., electron-hole pairs) are accelerated towards the sensor node 552 by an electric field. If the electric field is strong enough (due to over-biasing), these carriers gain enough kinetic energy to ionize other atoms in the avalanche region 566 through collisional ionization, thereby generating more carriers. This process chain, leading to a rapid multiplication or "avalanche" of charge carriers. The avalanche generates a sharp current pulse, which can be detected as a signal that a photon has been absorbed. The avalanche region 566 can be a region bordering or adjacent to the sensor node 552 and the guard ring 556, such as... Figure 5 As shown. Avalanche zone 566 may extend outward from sensor node 552 and may not be along the vertical direction (e.g., Figure 5 The avalanche region 566 extends beyond the guard ring 556 along the Z-axis direction. The avalanche region 566 can be a region formed in relation to the location of the sensor node 552 and the thickness of the substrate 560. For example, when the silicon thickness of the substrate 560 exceeds approximately 5 micrometers, the avalanche region 566 may not form.

[0059] Once an avalanche is triggered, the current is rapidly quenched to prevent thermal damage to the SPAD 550 and reset the diode to detect the next photon. Quenching can be achieved by passively (using resistors) or actively (using electronic circuitry) reducing the bias voltage below the breakdown voltage. After quenching, the voltage returns to an initial level above the breakdown voltage, re-establishing the Geiger mode conditions and preparing the SPAD for the next photon detection event. The bias voltage and subsequent operation of the BSI SPAD benefit from careful control of the applied voltage and the timing of the quenching and reset processes to ensure sensitive, accurate, and repeatable photon detection.

[0060] A multilayer reflector 570 may be located between the front side 550f of the SPAD 550 and the SOC 500. In some embodiments, the multilayer reflector 570 may include multiple or "double layers" coated on the front side 550f of the SPAD 550. In some embodiments, the multilayer reflector 570 may include a three-layer, four-layer, or other structure. The double layer may be or include separate molybdenum and silicon layers. In some embodiments, the double-layer, three-layer, four-layer, or other layer structures may include additional materials with high extinction coefficients, such as ruthenium, strontium, niobium, beryllium, etc. In one example, the double layer may include a first layer and a second layer, the first layer comprising molybdenum having a thickness of about 3.5 nm, the second layer comprising silicon having a thickness of about 3.5 nm, and the number of double layers in the multilayer reflector 570 may range from about 5 double layers to about 40 double layers. Including the multilayer reflector 570 can enhance the intensity of EUV light to improve the detection of photons by the SPAD 550. In some embodiments, the multilayer reflector 570 includes one or more additional layers, such as a protective top cover layer that protects the double layers of the multilayer reflector 570 from moisture or other similar environmental factors that may damage the double layers. One or more buffer or dielectric layers may be present between the front side 550f of the SPAD 550 and the multilayer reflector 570.

[0061] A guard ring 556 is located between sensor node 552 and shared node 554. The guard ring 556, which may be included in the BSI SPAD 550, improves prevention of premature edge breakdown and isolates sensor node 552 from other structures, such as shared node 554. The guard ring 556 may comprise the same semiconductor material as the substrate 560 of the SPAD 550, such as silicon. The guard ring 556 may be doped with the same type of dopant as the sensor node 552 of the SPAD 550, but at a different concentration. For example, the guard ring 556 may be doped to form a PN junction around the active region of the SPAD 550. For example, in an n-type SPAD 550, the guard ring 556 may be p-type doped to establish a PN junction. In some embodiments, multiple guard rings 556 with different doping levels may be included to establish a smoother electric field gradient. For example, the guard ring 556 may have multiple concentric rings or a single ring, the width of which is selected to advantageously and effectively control the electric field. A guard ring 556 may be positioned around and separated from sensor node 552 by a selected distance to ensure that the electric field does not trigger unintended avalanche breakdown at the edges of sensor node 552. In some embodiments, a passivation layer, such as silicon dioxide (SiO2) or silicon nitride (Si3N4), may be applied to the guard ring 556 (not shown for simplicity). This passivation layer helps protect the underlying semiconductor and electrically isolated guard ring. The guard ring 556 benefits the performance of SPAD 550 because it helps reduce the dark count rate and increase the photon detection probability by ensuring that sensor node 552 operates within the expected voltage range without being affected by edge effects.

[0062] SPAD 550 can be physically, optically, and electrically isolated from adjacent SPADs via isolation structure 558 and isolation extension structure 5600. In some embodiments, isolation structure 558 is a shallow trench isolation (STI) structure. Isolation structure 558 may abut or be adjacent to shared node 554. In some embodiments, although Figure 5 Two isolation structures 558 are depicted, but the isolation structure 558 may be multiple parts of a single continuous isolation structure 558 surrounding the shared node 554, the guard ring 556, and the sensor node 552. The isolation structure 558 may be or includes a dielectric material, such as an oxide (e.g., silicon oxide), a nitride (e.g., silicon nitride or silicon oxynitride), a low dielectric constant dielectric, another suitable dielectric, a combination thereof, etc.

[0063] The isolation extension structure 5600 may include a metal or conductive layer 564 and a side isolation layer 562 on the conductive layer 564. The conductive layer 564 may help prevent emission distribution between adjacent SPADs due to recombination of electrons and holes. In some embodiments, the conductive layer 564 may serve as a conduction path for electrons and holes. The conductive layer 564 may be or include one or more of W, Ta, Cu, etc. The width of the conductive layer 564 in the horizontal direction (e.g., the X-axis direction) may be less than about 0.3 micrometers (μm). The height of the conductive layer 564 in the vertical direction (e.g., the Z-axis direction) may be less than about 2.5 μm. The side isolation layer 562 may be an oxide layer (e.g., silicon oxide), a nitride layer (e.g., silicon nitride or silicon oxynitride), a low dielectric constant dielectric layer, another suitable dielectric layer, or a combination thereof. The side isolation layer 562 may help prevent photoelectron leakage to nearby SPADs. The width of the side isolation layer 562 may be less than about 0.1 μm. The height of the side isolation layer 562 may be less than approximately 2.5 μm. The material of the side isolation layer 562 may be different from the material of the isolation structure 558. The upper surface of the side isolation layer 562 may be in direct contact with the lower surface of the isolation structure 558. In at least some embodiments, the side isolation layer 562 may extend along the X-axis direction to overlap at least a portion of the shared node 554 (in the Z-axis direction). One side surface of the side isolation layer 562 may be in direct contact with the substrate 560, and the other side surface of the side isolation layer 562 may be in direct contact with the conductive layer 564. The height of the side isolation layer 562 may be the same as or substantially the same as the height of the conductive layer 564.

[0064] The combination of isolation structure 558 and isolation extension structure 5600 extends vertically from the front side 550f of substrate 560 to the back side 550b of substrate 560. For example, isolation structure 558 may extend from the front side 550f to a first level near the lower surface of shared node 554 or between the lower surface of shared node 554 and the lower surface of guard ring 556. Isolation extension structure 5600 may extend from the first level to the back side 550b. Figure 5 As shown, the isolation structure 558 may have a smaller width at its bottom and a larger width at its top, wherein the width gradually (e.g., linearly) increases from the bottom to the top of the isolation structure. In at least some embodiments, the isolation extension structure 5600 may have a uniform width from its top to its bottom.

[0065] Figure 6A and Figure 6B This is a view of the isolation extension structures 60 and 60A, which can be embodiments of the isolation extension structure 5600. The isolation extension structures 60 and 60A can prevent emission distribution between adjacent devices through the recombination of electrons and holes. The isolation extension structures 60 and 60A can serve as conduction paths for electrons and holes. Figure 6AIn this embodiment, the isolation extension structure 60 is or includes a conductive layer 664, which may be or includes a metal layer formed of W, Ta, Cu, or combinations thereof. The isolation extension structure 60 may have a width W1 less than about 0.3 micrometers in the X-axis direction. The isolation extension structure 60 may have a height H1 less than about 2.5 micrometers in the Z-axis direction. A height H1 less than about 2.5 micrometers is advantageous for a substrate 560 thinner than about 5 micrometers, which facilitates the formation of avalanche regions 566. In some embodiments, the isolation extension structure 60 does not include a side isolation layer. That is, the metal layer of the isolation extension structure 60 may be in direct contact with the substrate 560.

[0066] In some embodiments, such as Figure 6B As shown, the isolation extension structure 60A may include a side isolation layer 662 between the conductive layer 664 and the substrate (e.g., substrate 560). The side isolation layer 662 may be a dielectric layer, such as SiO, SiC, SiN, SiOC, SiON, SiCN, SiOCN, etc. The side isolation layer 662 electrically isolates the conductive layer 664 from the substrate (e.g., substrate 560). Because the conductive layer 664 is electrically isolated from the substrate, a bias voltage can be applied to the conductive layer 664, which is beneficial for generating... Figure 6B The electric field is indicated by the middle arrow 670. This electric field can improve the flow of electrons 668 toward sensor node 552 and avalanche region 566, such as... Figure 6B and Figure 6A Compared to the depicted version, electrons 668 are more uniformly distributed across the entire substrate, even within the conductive layer 664. A bias voltage can be applied via the front electrode 668f and the back electrode 668b, which are in contact with the conductive layer 664. (Refer to...) Figure 7L In more detail, the conductive layer 664 can be electrically connected to a bias power supply via contacts extending through the multilayer reflector 570 and the passivation layer 572.

[0067] Figure 9 and Figure 10 Flowcharts of methods 1000 and 2000 according to one or more aspects of this disclosure for forming an IC device (method 1000) or a portion thereof from a workpiece and detecting photons via the IC device (method 2000) are depicted. Methods 1000 and 2000 are merely examples and are not intended to limit this disclosure to what is expressly shown in methods 1000 and 2000. Additional actions may be provided before, during, and after methods 1000 and 2000, and some actions may be replaced, eliminated, or moved for additional embodiments of the methods. For simplicity, not all actions are described in detail herein. The following describes different manufacturing stages in conjunction with embodiments of method 1000. Figure 7A-7NMethod 1000 is described by perspective and / or cross-sectional views of the image sensor 70 or a fragment of the workpiece. Method 2000 is described in conjunction with a schematic diagram of the system 80 for detecting or monitoring EUV photons. For the avoidance of doubt, in all figures, the X direction is perpendicular to the Y direction and the Z direction is perpendicular to both the X and Y directions. It should be noted that, since the workpiece can be manufactured as a semiconductor device, the workpiece may be referred to as a semiconductor device depending on the context.

[0068] exist Figure 7A The image sensor 70 includes a substrate 760. The substrate 760 is similar in most respects to the reference citation. Figure 4 and Figure 5 The substrates 110 and 560 are described above. Substrate 760 may be a semiconductor substrate, such as a bulk semiconductor or the like, which may be doped (e.g., with p-type or n-type dopants) or undoped. The semiconductor material of substrate 760 may include silicon, germanium, compound semiconductors (including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide), alloy semiconductors (including silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide, and / or gallium arsenide phosphide), or combinations thereof. Other substrates may be used, such as monolayer, multilayer, or gradient substrates. In some embodiments, substrate 760 is doped using a low-damage implantation process, which corresponds to... Figure 9 Action 1010. Substrate 760 can be doped with p-type dopant to approximately 1e. 16 / cm 3 The doping concentration.

[0069] As a non-limiting example, a low-damage implantation process that dops a silicon substrate 760 with a p-type dopant, such as boron (B), gallium (Ga), or indium (In), can introduce the dopant into the silicon substrate 760 to alter its electrical properties and reduce crystal damage. This is beneficial for maintaining the integrity of the semiconductor lattice structure, thereby affecting device performance. Based on the selected electrical properties and application, the low-damage implantation process may include p-type dopants such as boron (B), gallium (Ga), or indium (In). Boron is chosen as the p-type dopant for silicon because it integrates efficiently into the silicon lattice and has a suitable energy level. Relatively low implantation energies can be used to reduce lattice damage. Low energies allow the dopant to be introduced near the surface of the substrate 760 without causing deep lattice disruption. The dosage, or the amount of dopant implanted, is controlled to achieve the selected doping concentration without causing excessive damage. Surface preparation can be performed prior to implantation to clean the silicon substrate and remove any contaminants or native oxides. This step helps reduce the likelihood of implantation penetrating or entering unwanted material, which could affect dopant distribution or cause additional damage. Implantation can be performed at reduced temperatures, such as around room temperature or even below room temperature. During implantation, cooling the substrate 760 can reduce defect formation by suppressing dynamic annealing, which would otherwise repair some damage during implantation, thus keeping the process under control and reducing unwanted dopant diffusion. Dopant can be introduced at a small angle rather than perpendicular to the surface of the substrate 760. This technique helps reduce channeling effects, where dopant penetrates deep along crystal planes, leading to uneven dopant distribution and excessive damage. The use of dopant clusters or molecular ions can be included in implantation, which can reduce damage by dispersing the effects of implantation over a larger area of ​​the silicon lattice, reducing the concentration of energy transferred to silicon atoms, and thus reducing damage. After implantation, a thermal annealing process can be performed at a selected temperature. This step repairs lattice damage by allowing silicon atoms to move back to their correct positions, activating the dopant (i.e., allowing them to occupy alternative sites in the silicon lattice), and restoring the crystal structure. Ultra-low thermal budget annealing techniques (such as spike annealing or flash annealing) can be selected to activate the dopant while reducing diffusion.

[0070] exist Figure 7B and Figure 7C In this process, an isolation structure 758 can be formed in the substrate 760, which corresponds to Figure 9 Action 1020. The isolation structure 758 is, in most respects, similar to reference [reference]. Figure 5 The isolation structure 558 is described above. The isolation structure 758 may be a shallow trench isolation (STI) structure. Figure 7B Two isolation structures 758 are depicted, but in some embodiments, the isolation structure 758 is a plurality of parts of a single continuous isolation structure 758, such as Figure 7C As shown in the floor plan. Figure 7C The isolation structure 758 depicted includes horizontal and vertical lines that intersect along the X and Y axes, forming pixel regions 75P associated with each SPAD (e.g., SPAD 550).

[0071] Example processes for forming isolation structures may include several photolithography, etching, and chemical vapor deposition (CVD) processes, as briefly described below. The example process begins with a clean silicon substrate 760. A thin oxide or nitride layer may be prepared on the surface of substrate 760 to facilitate further processing steps. A thin silicon dioxide (pad oxide) layer may be thermally grown on substrate 760. The pad oxide layer acts as a buffer to alleviate stress between the silicon substrate and the subsequently formed silicon nitride (Si3N4) layer, which has a different coefficient of thermal expansion. A silicon nitride layer is then deposited on the pad oxide layer using, for example, chemical vapor deposition (CVD). The silicon nitride layer acts as a hard shield during trench etching processes and protects areas of the silicon substrate 760 that should not be etched away. Photoresist may be applied to the surface of the silicon nitride layer, and photolithography may be used to expose the photoresist according to the trench pattern. Photoresist is exposed to ultraviolet (UV) light through or from a photomask, thereby transferring the trench pattern onto the photoresist. Then, depending on the type of photoresist used, the exposed or unexposed areas of the photoresist are developed to reveal the pattern. As the pattern is transferred to the photoresist, the substrate undergoes an etching process, such as reactive ion etching (RIE), to remove silicon nitride, pad oxide, and silicon from the exposed areas to form trenches in the silicon substrate 760. The trench depth can be less than about 2.5 nm. After etching, the remaining photoresist is stripped using a plasma ashing process or chemical solvents to leave patterned silicon nitride and trenches in the silicon substrate 760. Optionally, a thermal oxidation process can be used to round the corners of the trenches. This step reduces the electric field concentration at the corners, thereby improving device reliability. A dielectric material (e.g., silicon dioxide) for the isolation structure 758 is deposited in the trenches, which can be done via a CVD process. Following the deposition process, chemical mechanical polishing (CMP) can be performed to remove excess dielectric material and planarize the surface, leaving the dielectric of the isolation structure 758 flush with the silicon nitride layer. The silicon nitride and the underlying pad oxide layer are then removed. The nitride layer can be stripped with thermal phosphoric acid, while the pad oxide can be removed using hydrofluoric acid (HF), thus exposing the planarized trenches filled with oxide and the surface of the silicon substrate 760. The STI process can form electrically isolated regions 75P in the silicon substrate 760, enabling the fabrication of densely packaged SPADs while reducing leakage and crosstalk.

[0072] exist Figure 7D and Figure 7E In the middle, a protective ring 756 is formed, which corresponds to Figure 9 Action 1030. The protective ring 756 is similar in most respects to reference [reference]. Figure 5 The protective ring 556 is described above. The protective ring 556 may have a hollow quadrilateral profile, such as... Figure 7E As shown in the plan view. In some embodiments, the protective ring 556 has a shape different from the depicted contour, such as a rhombus, a polygon (e.g., a hexagon), a circle, or other suitable shape. The protective ring 756 may extend to a depth beyond the depth to which the isolation structure 758 extends (e.g., in the Z-axis direction).

[0073] The following is a brief description of an example process for forming the guard ring 756. The guard ring 756 prevents premature edge breakdown and improves the uniformity of the electric field distribution across the SPAD. Formation of the guard ring 756 can begin with a clean, lightly doped p-type or n-type silicon substrate 760, depending on the selected electrical characteristics of the SPAD. In some embodiments, a suitable well is formed in the substrate 760 where the active region of the SPAD will be located. The well can be formed by an ion implantation or diffusion process, wherein donor atoms (e.g., phosphorus or arsenic for n-type doping or boron for p-type doping) are introduced into the substrate 760. Around the periphery of the intended active region, the guard ring 756 can be formed by implanting or diffusing a dopant of the same type as the substrate but at a higher concentration. For p-type substrates, a higher concentration of p-type dopant (e.g., boron) is introduced to form a p+ guard ring 756. The guard ring 756 can be used to control the electric field and prevent edge breakdown by smoothly grading the potential from a high-field region within the active region to a low-field region outside the active region.

[0074] Figure 7F and Figure 7G The formation of sensor node 752 and shared node 754 according to various embodiments is depicted, respectively corresponding to Figure 9 Actions 1040 and 1050. Sensor node 752 is similar to reference in most respects. Figure 5 The sensor node 552 is described above. The shared node 754 is similar in most respects to the referenced node. Figure 5 The shared node 554. In some embodiments, sensor node 752 is a heavily doped n-type implantation region formed within guard ring 756, and shared node 754 is a heavily doped p-type implantation region formed outside guard ring 756. Sensor node 752 typically abuts directly against guard ring 756 on all sides. Shared node 754 may be adjacent to isolation structure 758, such as... Figure 7F and 7G As shown, it may be slightly separated from the isolation structure 758.

[0075] Forming the N+ sensor node 752 may involve a series of semiconductor fabrication operations aimed at establishing a highly doped n-type region within the substrate 760, which is beneficial for single-photon detection. The N+ sensor node 752 serves as the primary site for photon-triggered avalanche multiplication. An example process for forming the N+ sensor node in the substrate 760 is briefly described below. The process may begin with a clean silicon substrate 760, which is p-type to establish a PN junction with the N+ sensor node 752. In some embodiments, an optional N-well or deep N-well may be formed in the p-type substrate 760 prior to forming the sensor node 752 to establish a selected electric field distribution or to electrically isolate the sensor node 752 from the substrate 760. This step may include ion implantation or diffusion of an n-type dopant (e.g., phosphorus or arsenic). The surface of the substrate 760 may then be oxidized to grow a thin silicon dioxide (SiO2) layer. Photolithography may be used to pattern a photoresist on the oxide layer to expose the area where the N+ sensor node 752 is to be formed. The exposed region is ion-implanted with a high-energy n-type dopant (e.g., phosphorus or arsenic) to form an N+ sensor node 752. The doping concentration of sensor node 752 can be significantly higher than that of the substrate 760 or optional well to increase conductivity and effective charge collection area. After implantation, an annealing step can be performed to repair lattice damage caused by implantation and activate the dopant in sensor node 752, enabling it to occupy alternative lattice sites. This step is beneficial for restoring the crystal structure of silicon and improving the electrical activation of the implanted dopant.

[0076] In the example above, sensor node 752 is an N+ sensor node 752. In such embodiments, the guard ring 756 is typically doped with a type complementary to that of the sensor node 752, effectively preventing edge breakdown. For an N+ sensor node 752 comprising a highly doped N-type region designed for photon detection, the guard ring 756 can be p-type doped. This p-type guard ring 756 has several advantageous uses. The p-type guard ring 756 around the N+ sensor node 752 helps manage the electric field gradient at the edges of the N+ region of the N+ sensor node 752. Appropriate selection of the doping concentration and distribution of the p-type guard ring 756 results in a more uniform electric field distribution, which helps prevent electric field concentration at the edges, thus preventing premature edge breakdown. The p-type guard ring 756 can act as a barrier confining the high electric field within the N+ sensor node 752. This constraint helps prevent edge breakdown because it increases the likelihood that avalanche breakdown will occur uniformly across the sensor region 766, rather than at the edges (e.g., outside the guard ring 756), where avalanche breakdown can lead to noise and reduced detection efficiency. The presence of the P-type guard ring 756 around the N+ sensor node 752 also allows for better control of the breakdown voltage across the SPAD. By selecting the doping concentration and depth of the P-type guard ring 756, the breakdown voltage can be adjusted to select the operating parameters of the SPAD. It should be noted that in some embodiments, the sensor node 752 can be a P+ sensor node 752, in which case the guard ring 756 can be an N-type guard ring 756.

[0077] The formation of the shared node 754 can be similar in many respects to the formation of the sensor node 752. In some embodiments, the sensor node 752 is a heavily doped N-type (or N+) sensor node 752, and the shared node 754 is a heavily doped P-type (or P+) shared node 754. The P+ shared node 754 can serve as an electrical contact for the SPAD, ensuring efficient charge collection and providing a path for avalanche currents generated during photon detection. In some embodiments, the shared node 754 extends into the substrate 760 to the same or similar depth as the isolation structure 758 and is shallower than the guard ring 756. The sensor node 752 can extend to a depth shallower than the shared node 754 and the guard ring 756, which can help prevent edge breakdown outside the avalanche region 766.

[0078] In an example process for forming the P+ shared node 754, outside the p+ guard ring 756, in the p-type substrate 760, the substrate 760 may be doped with a high concentration of p-type dopant to establish a heavily doped region that serves as the primary electrical contact of the device. For example, a lithography mask may be used to expose the region of the substrate 760 associated with the P+ shared node 754. The mask protects regions that should not receive additional doping, isolating these regions from the P+ shared node 754. After the mask is positioned, a high concentration of p-type dopant (e.g., boron) is implanted into the exposed shared node region of the substrate 760. This step can benefit from high-energy implantation to increase the depth of dopant penetration into the substrate 760, thereby establishing a heavily doped P+ region for the P+ shared node 754. The high doping concentration helps reduce the resistance of the shared node 754, improving charge collection and removal efficiency. After implantation, the substrate 760 may undergo an annealing process, typically performed in a rapid thermal annealer (RTA). High-temperature annealing allows the implanted dopant in the heavily doped P+ region of the P+ shared node 754 to become electrically active by moving it to an alternative lattice site. This step also repairs damage to the silicon lattice caused by the implantation process, improving the structural integrity of the substrate 760.

[0079] In the above description, an isolation structure 758 is formed, followed by a protective ring 756, then a sensor node 752, and finally a shared node 754. In some embodiments, one or more of the steps described above are used in conjunction with a reference... Figures 7A-7G The different sequences of execution described herein. For example, shared node 754 may be formed before sensor node 752. In another example, guard ring 756 may be formed after shared node 754 is formed.

[0080] exist Figure 7HAfter forming the isolation structure 758, guard ring 756, sensor node 752, and shared node 754, the substrate 760 can be flipped to prepare for thinning. While preparing the substrate 760 for flipping, the front side 760f of the substrate 760 (which contains fabricated devices or circuitry, such as the isolation structure 758, sensor node 752, shared node 754, and guard ring 756) can be cleaned to remove any contaminants. This helps prevent damage or contamination during subsequent processing steps. A carrier wafer (not shown for simplicity) can then be prepared and bonded to the front side 760f of the substrate 760. The carrier wafer serves as a mechanical support during the subsequent thinning process. The bonding material used can be advantageously strong enough to withstand the thinning process and can be removed after the thinning process is complete. Materials such as temporary adhesives, glass powder, or polymer-based bonding agents can be selected as bonding materials. After the bonding process, the substrate 760 is flipped to expose the back side 760b and prepare for thinning. The carrier wafer is now bonded to the front 760f, providing stability and protecting the devices on the front 760f during the thinning process.

[0081] exist Figure 7I In this process, substrate 760 is thinned by removing material from its back side. For example, the exposed back side of substrate 760 can be thinned to a selected thickness T1. This can be achieved through mechanical polishing, chemical mechanical polishing (CMP), or a combination of both. Mechanical polishing rapidly removes most of the material from substrate 760, while CMP is used for fine polishing to achieve a smooth and uniform surface with a precise final thickness T1. The thinning process may introduce stress and potential damage into substrate 760. Selective stress relief steps (e.g., mild thermal annealing) can be performed to relieve stress and repair damage in the substrate material. Once the thinning process is complete and substrate 760 is at the selected thickness T1, the carrier wafer can be peeled off from the front side of substrate 760. Exemplary peeling techniques may include one or more of heating, solvent dissolution, or mechanical force. After peeling, substrate 760 can be cleaned to remove any residue from the bonding and peeling processes. In some embodiments, the thickness T1 or “height” of substrate 760 after the thinning process may be less than about 5 micrometers. A thickness T1 of less than approximately 5 micrometers is conducive to the formation of avalanche zones 766. That is, a thickness T1 exceeding approximately 5 micrometers may lead to insufficient formation of avalanche zones 766, which may reduce the operation of the image sensor 70.

[0082] exist Figure 7J In the process, after thinning the substrate 760, an isolation extension structure 7600 is formed, which corresponds to Figure 9 Action 1060. The isolation extension structure 7600 is, in most respects, similar to the reference. Figure 5 , Figure 6A and Figure 6B The isolation extension structures 5600, 60, and 60A described herein. In one example, the process for forming the isolation extension structure 7600 may begin by coating a photoresist onto a silicon substrate 760. Photolithography is then used to pattern the photoresist, exposing the areas of the trenches to be etched. Deep trenches can be created in the silicon substrate 760 using an etching process (e.g., reactive ion etching (RIE)). In some embodiments, the deep trenches expose an isolation structure 758. After etching the trenches, a thin silicon oxide liner may be formed on the trench walls, corresponding to the side isolation layer 762, which may be... Figure 5 and Figure 6B An embodiment of side isolation layer 562 of the side isolation layers 562 and 662 described herein. The formation of a thin silicon oxide layer can be performed by thermal oxidation, wherein the substrate 760 is exposed to oxygen at a high temperature, resulting in the growth of a thin silicon dioxide layer on all silicon surfaces exposed by the deep trench. Alternatively, a CVD process can be used to deposit a uniform silicon oxide layer inside the trench. This method is advantageous for improving the uniformity of the oxide layer over complex morphologies. To make contact with the underlying isolation structure 758 in a selected area, a portion of the silicon oxide liner is removed. The oxide layer can be removed without damaging the silicon substrate 760 using a selective etching process (e.g., wet etching or dry etching using hydrofluoric acid (HF)). A selective barrier layer (e.g., titanium nitride) can be applied before depositing the conductive material of the conductive layer 764 to prevent the conductive material from diffusing into the silicon substrate 760. The barrier layer also promotes adhesion between the conductive layer and the silicon oxide of the side isolation layer 562. A conductive material, such as tungsten, tantalum, or copper, is then deposited into the trenches on the isolation structure 758 and the side isolation layer 762. Depending on the material, deposition processes such as chemical vapor deposition (CVD) for tungsten, physical vapor deposition (PVD) for tantalum, or electrochemical deposition (ECD) for copper, or other suitable deposition processes, can be used. For example, a CVD process can deposit tungsten hexafluoride (WF6), which is reduced to tungsten in the presence of hydrogen. A PVD process can sputter tantalum atoms onto the surface exposed by the trenches. An ECD process can deposit copper onto the surface by circulating a current through a copper sulfate solution. After deposition, excess conductive layer 764 and selective barrier layer are removed from the top surface of the silicon substrate 760, leaving a flat surface.

[0083] It should be noted that although the above description of forming the isolation extension structure 7600 indicates that the isolation extension structure 7600 is formed after the substrate 760 is thinned, in some embodiments, the isolation extension structure 7600 may be formed from the front side 760f of the substrate 760 before thinning. For example, a deep trench may be formed through the isolation structure 758 and extending below the isolation structure 758 to a depth of less than about 2.5 micrometers. An oxide layer 762 may then be formed on the exposed surface of the substrate 760 as described above, followed by the formation of a conductive layer 764 on the oxide layer 762. When the substrate 760 is thinned, the thinning may stop at or after reaching the bottom surface of the isolation extension structure 7600. It should also be noted that in the above embodiments and the embodiments just described, the formation of the side isolation layer 762 may be omitted, which will be referred to Figure 6A The isolation extension structure 60 is described above. That is, in some embodiments, the conductive layer 764 may be in direct contact with the substrate 760.

[0084] exist Figure 7K In the process, after forming the isolation extension structure 7600, a passivation layer 772 is formed on the back side of the substrate 760, the exposed upper surface of the conductive layer 764, and the selectively side-mounted isolation layer 762, which corresponds to Figure 9 Action 1070. Passivation layer 772 is similar to the reference in most respects. Figure 5The passivation layer 572 is described above. The passivation layer 772 may cover the entire surface of the image sensor 70. Forming a passivation layer 722, or protective layer, on the incident surface of the back-illuminated SPAD image sensor 70 helps protect the image sensor 70 from environmental damage, reduces surface recombination, and improves photon detection efficiency. The incident surface in a BSI SPAD is the back-side surface 760b from which photons enter. In an example process, the back-side surface 760b may be cleaned to remove any contaminants, residues, or particles. Cleaning may include a series of wet chemical cleanings, such as Radio Corporation of America (RCA) cleaning, which may include a mixture of ammonium hydroxide (NH4OH), hydrogen peroxide (H2O2), and water to remove organic residues, followed by a mixture of hydrochloric acid (HCl), H2O2, and water to remove metallic contaminants. Selective chemical mechanical polishing (CMP) steps may be performed to improve smoothness and remove defects from the back-side surface 760b. This helps reduce surface irregularities that may reduce detection efficiency. The passivation layer 772 may be made of SiN, SiC, SiON, SiO2, SiCN, or combinations thereof. These materials are advantageous, at least for their chemical stability and ability to form a high-quality interface with the silicon substrate 760. The passivation layer 772 may be thermally grown in an oxidation furnace, deposited using CVD (e.g., plasma-enhanced CVD, PECVD) or by another suitable process. The thickness of the passivation layer 772 is beneficial for reducing the absorption and reflection losses of incident EUV photons. In some embodiments, for approximately 50 W / mm²... 2 Sr up to approximately 200W / mm 2 For EUV light sources in the Sr range, the thickness of the passivation layer 772 can exceed approximately 10 nm. However, for EUV light sources with an intensity less than approximately 50 W / mm², the passivation layer 772 can be thicker. 2 In the Sr embodiment, the thickness of the passivation layer 772 may be less than about 5 nm. After depositing the passivation layer 772, an annealing step may be performed to improve the quality of the passivation layer by reducing defects and improving the interface between the passivation layer 772 and the silicon substrate 760. The annealing process may include heating the device under processing (image sensor 70) to a selected temperature and continuing for a selected duration in a controlled gas pressure (e.g., nitrogen or syngas).

[0085] In addition, Figure 7K In the process, before or after the formation of the passivation layer 772, a multilayer reflector 770 is formed on the front side 760f of the substrate 760, which corresponds to Figure 9Action 1080. The multilayer reflector 770 may comprise a stack of molybdenum / silicon (Mo / Si) bilayer pairs selected for their high reflectivity at EUV wavelengths. An example process for forming the multilayer reflector 770 may involve a series of deposition operations to obtain a selected thickness and uniformity for each layer and the total thickness of the multilayer reflector 770. The process may begin with the preparation of a substrate 760. The substrate 760 may be cleaned to remove contaminants or particles that may interfere with the deposition process. The Mo / Si bilayer may be deposited using physical vapor deposition (PVD) methods, such as magnetron sputtering or molecular beam epitaxy (MBE), which allows for precise control of layer thickness and composition. The process may comprise alternating layers of deposited molybdenum (Mo) and silicon (Si). The thickness of each layer may be selected to improve reflectivity at EUV wavelengths. In some embodiments, the silicon layer is approximately thicker than the molybdenum layer. As an example, the bilayer may comprise a silicon layer approximately 4 nm thick and a molybdenum layer approximately 1 nm thick. In some embodiments, the silicon and molybdenum layers have substantially the same thickness. For example, the silicon and molybdenum layers may each have a thickness of approximately 3.5 nm. The total number of Mo / Si bilayer pairs in the stack can range from 5 to 40, but in some embodiments, it can be 50 or more. This stack can be terminated with a silicon capping layer, which helps protect the multilayer reflector 770 from oxidation and contamination. The capping layer can be deposited on top of the final silicon layer, and the capping layer can be a ruthenium (Ru) layer or another oxidation-resistant material layer with suitable optical properties. The capping layer protects the multilayer reflector 770 from degradation and enhances its durability and performance in EUV lithography systems. After deposition, the multilayer reflector 770 can be annealed to improve the crystallinity of the individual Si and Mo layers and further reduce interface roughness, which enhances the overall EUV reflectivity.

[0086] exist Figure 7LIn the image sensor 70, after the passivation layer 772 and the multilayer reflector 770 are formed, electrical contacts (e.g., vias) 780, 782, 784f, and 784b may be formed to provide electrical connections to various components of the image sensor 70. A first contact 780 may extend through the multilayer reflector 770 and be electrically connected (e.g., in direct contact) to a sensor node 752. A second contact 782 may extend through the multilayer reflector 770 and be electrically connected (e.g., in direct contact) to a shared node 754. A front contact 784f may extend through the multilayer reflector 770 and the isolation structure 758 and be electrically connected (e.g., in direct contact) to a first side of the conductive layer 764. A back contact 784b may extend through the multilayer reflector 770 and the isolation structure 758 and be electrically connected (e.g., in direct contact) to a second side of the conductive layer 764 opposite to the first side. In embodiments where the conductive layer 764 extends through the isolation structure 758, for example when the conductive layer 764 is formed from the front side 760f of the substrate 760 before the substrate 760 is thinned, the front contact 784f may extend through the multilayer reflector 770 and land at or slightly below the level of the front side 760f of the substrate 760 on the conductive layer 764.

[0087] The formation of the contacts (780, 782, 784f) may include photolithography of a patterned mask layer to expose the areas of the multilayer reflector 770 where the contacts (780, 782, 784f) will form. The exposed material can then be removed by appropriate etching or other removal processes. The removal process removes Si and Mo material from the areas exposed by the patterned mask layer, forming vias or holes that expose underlying components such as sensor node 752, shared node 754, and conductive layer 764. Alternatively, focused ion beam (FIB) or laser sintering can be used to form contact holes through the Si and Mo layers of the multilayer reflector 770.

[0088] These holes are then filled with a conductive metal to establish electrical contacts. The conductive metal can be, or includes, copper, tungsten, aluminum, etc. Metal filling can be performed by various methods, including electrochemical plating (ECP) for copper, CVD for tungsten, or other suitable deposition processes. After metal filling, the surface of the multilayer reflector 770 can be planarized using chemical mechanical polishing to remove any excess metal and ensure a flat surface for subsequent processing steps. This leaves only metal in the contact holes, forming a smooth, horizontal surface with the multilayer reflector 770. In some embodiments, to avoid electrical short circuits between contacts (780, 782, 784f) extending through the molybdenum layer of the multilayer reflector 770, a dielectric liner or spacer layer can be formed in the contact holes associated with the contacts (780, 782, 784f) before depositing the conductive material of the contacts (780, 782, 784f). The dielectric liner can include one or more dielectric materials, such as SiN, SiC, SiON, SiO2, SiCN, etc.

[0089] exist Figure 7M In the middle, the SOC 900 is bonded to the image sensor 70. The SOC 900 can be... Figure 5 An embodiment of SOC 500. SOC 900 may include a first pad 730 and a second pad 740 on its surface. The first pad 730 may be electrically connected to the second contact 782 via an interconnect structure 790. The interconnect structure 790 may be or include one or more vias and conductive traces formed in different metal layers embedded in one or more dielectric layers. The interconnect structure 790 may form a local interconnect between the first pad 730 and the second contact 782 via SOC 900.

[0090] The SOC 900 may include an interconnect structure 792 that electrically connects the second pad 740 to a contact metal 798 on the opposite side of the SOC 900. The SOC 900 may also include an interconnect structure 794 that electrically connects the first contact 780 to a contact metal 796 on the opposite side of the SOC 900. The interconnect structures (790, 792) and the contact metals (796, 798) may be or include one or more conductive materials, such as copper, tungsten, aluminum, tantalum, ruthenium, cobalt, etc.

[0091] exist Figure 7N In the process, integrated circuit (IC) 910 is mounted onto SOC 900. Integrated circuit 910 is a reference... Figure 5The embodiment of integrated circuit 510 described herein is similar to it in most respects. Integrated circuit 910 includes an interconnect structure 804 that electrically connects a second pad 740 to a first contact 780. When IC 910 is attached to SOC 900, IC 910 and SOC 900 can be bonded to each other. For example, contact metal 798 of SOC 900 can be bonded to a metal feature of IC 910 to form a metal bond 802, and contact metal 796 of SOC 900 can be bonded to a metal feature of IC 910 to form another metal bond 800. The electrical connection between the second pad 740 and the first contact 780 can be achieved through interconnect structure 792, metal bond 802, interconnect structure 804, metal bond 800, and interconnect structure 794. The interconnect structure 804 and metallic features of IC 910 may be or include one or more conductive materials, such as copper, tungsten, aluminum, tantalum, ruthenium, cobalt, etc.

[0092] Figure 8 This is a schematic diagram of a system 80 according to various embodiments. The system 80 may be an inspection system 80 or a monitoring system 80 that can detect photons of incident light 86 reflected when an EUV photomask 88 fixed by a mask platform 92 is exposed to EUV light 84 generated by an EUV light source 810. Figure 10 This is a flowchart of a method 2000 that can be executed by system 80. In some embodiments, method 2000 may be executed by a system having more, fewer, and / or different components than system 80.

[0093] Light source 810 is configured to generate light radiation having a wavelength in a specific embodiment between about 1 nm and about 300 nm. In a specific example, light source 810 generates EUV radiation with a wavelength centered at about or substantially 13.5 nm. Therefore, light source 810 is also referred to as an EUV radiation source. However, it should be understood that light source 810 is not limited to emitting EUV radiation. Light source 810 can be used to perform any high-intensity photon emission from excited target fuel.

[0094] Mask platform 92 is configured to hold mask 88. In some embodiments, mask platform 92 includes an e-chuck to hold mask 88. One reason for the advantage of an e-chuck is that gas molecules absorb EUV radiation, and the e-chuck can be operated in lithography exposure systems used for EUV lithography patterning or inspection, which are maintained in a vacuum environment to avoid loss of EUV intensity. The terms “mask,” “photomask,” and “reticle” are used interchangeably. Mask 88 is a reflective mask. An example structure of mask 88 includes a substrate of a suitable material, such as a low thermal expansion material (LTEM) or fused silica. In various examples, LTM includes TiO2-doped SiO2 or other suitable materials with low thermal expansion. Mask 88 includes a reflective multilayer 870 deposited on the substrate. Mask platform 92 is operable to translate in two horizontal directions to expose multiple different regions of mask 88 to EUV light 84. The reflective multilayer 870 or multilayer reflector 870 may be similar to the multilayer reflector 770 in many respects and may include additional components, such as an absorbing layer 820 having openings 82 that expose areas of the reflective multilayer 870 according to a pattern.

[0095] System 80 detects photons of light 86 using an image sensor 830 comprising multiple SPADs 850. The image sensor 830 can be a reference... Figure 1A , Figure 1B , Figure 1C , Figure 4 , Figure 5 and Figure 7A-7N Any one of the image sensor / image sensor devices (10, 10A, 10B, 40, 50, 70) described herein.

[0096] In action 2010 of method 2000, photons of EUV wavelength can be generated by a light source, such as reference... Figure 8 The light source 810 is described above. Photons can, for example, be referenced... Figure 5 , Figure 6A , Figure 6B and Figure 7A-7N The back side of the substrate of the said substrate (560, 660, 760) is received.

[0097] Then, in action 2020 of method 2000, an avalanche current may be generated in response to a photon. For example, the photon may be received by a photon detector (e.g., SPAD 550) in substrate 560. The photon can excite electrons that can travel toward the sensor node of the photon detector, as shown in reference... Figure 5As shown. Photons can pass through a passivation layer (e.g., passivation layer 772) on the back side of the substrate. When the intensity of EUV light 84 is less than 50 W / mm². 2 In Sr, the passivation layer on the back side of the substrate can have a thickness of less than about 5 nanometers. When the intensity of EUV 84, which includes photons, exceeds 50 W / mm²... 2 Sr and less than 200W / mm 2 When Sr is used, the passivation layer on the back side of the substrate has a thickness of more than about 10 nanometers.

[0098] Then, in action 2030 of method 2000, the avalanche current is detected. For example, the avalanche current can be detected by referring to... Figure 5 and Figure 9 The SOCs 500, 900 and / or ICs 510, 910 are used for detection. Avalanche current can flow between sensor node 752 and shared node 754 and can be detected via pads (730, 740) electrically connected to sensor node 752 and shared node 754. In some embodiments, avalanche current is detected by circuitry within the SOCs 500, 900, without requiring detection by ICs 510, 910.

[0099] The embodiments offer several advantages. SPAD photon counting reduces gain noise and circuit noise because the detector response is binarized. The EUV SPAD in the embodiments operates on EUV light with a bandwidth of 13.5 nm, which improves efficiency. The use of multilayer reflectors improves photon collection in avalanche regions. The isolated extension structure, including a conductive layer carrying a voltage bias, also improves electron flow to the sensor node.

[0100] A common embodiment includes a method. The method includes doping a substrate with a first dopant material to form a doped substrate. The method further includes forming an isolation structure on the front side of the doped substrate. The method further includes forming an isolation extension structure extending from the back side of the doped substrate to the isolation structure. The method further includes forming a guard ring adjacent to the isolation structure on the front side of the doped substrate, the guard ring including the first dopant material. The method further includes forming a sensor node adjacent to the guard ring, the guard ring being between the sensor node and the isolation structure, the sensor node including a second dopant material of a different type than the first dopant material. The method further includes forming a shared node on the front side of the doped substrate, the shared node being located between the isolation structure and the guard ring, the shared node including the first dopant material. The method further includes forming a multilayer reflector on the front side of the substrate.

[0101] In some embodiments, the method further includes forming a passivation layer on the back side of the doped substrate, the passivation layer comprising a dielectric material. In some embodiments, forming the passivation layer includes forming the passivation layer with a thickness greater than about 10 nanometers. In some embodiments, forming the isolation extension structure includes forming a conductive layer with a height less than about 2.5 micrometers. In some embodiments, forming the isolation extension structure further includes forming an electrical contact on an opposite side of the conductive layer. In some embodiments, the method further includes forming a sidewall insulator layer between the doped substrate and the isolation extension structure. In some embodiments, forming the isolation extension structure includes forming the isolation extension structure having a conductive layer laterally abutting an oxide layer on its opposite side. In some embodiments, the method further includes forming a first contact extending through the multilayer reflector and electrically connected to the sensor node; and forming a second contact extending through the multilayer reflector and electrically connected to the shared node. In some embodiments, the method further includes attaching a system-on-a-chip substrate to the multilayer reflector; and attaching an integrated circuit to the system-on-a-chip substrate. In some embodiments, forming the multilayer reflector includes forming a plurality of bilayers, each of the bilayers comprising a molybdenum layer and a silicon layer, each of the molybdenum layer and the silicon layer having a thickness in the range of about 3 nanometers to about 4 nanometers and a number of the bilayers in the range of about 5 to about 40.

[0102] One general aspect includes an apparatus comprising a photon detector and a substrate. The apparatus further includes an isolation structure located on a first side of the substrate. The apparatus also includes a guard ring adjacent to the isolation structure and within the first side of the substrate. The apparatus further includes a sensor node on the first side of the substrate, the guard ring being between the sensor node and the isolation structure. The apparatus also includes a shared node on the first side of the substrate, the shared node being between the guard ring and the isolation structure. The apparatus further includes an isolation extension structure on a second side of the substrate opposite to the first side, the isolation extension structure extending from the second side to the isolation structure. The apparatus also includes a multilayer reflector on the first side of the substrate.

[0103] In some embodiments, the device further includes a dielectric layer between the isolation extension structure and the substrate. In some embodiments, the isolation extension structure includes a conductive layer, a front contact on the conductive layer, and a second side contact on the conductive layer. In some embodiments, the device further includes a first contact extending through the multilayer reflector and electrically connected to the sensor node, and a second contact extending through the multilayer reflector and electrically connected to the shared node. In some embodiments, the device further includes a system-on-a-chip (SoC) attached to the multilayer reflector, the SoC including a first pad on a surface of the SoC electrically connected to the sensor node via the first contact, and a second pad on the surface of the SoC electrically connected to the shared node via the second contact. In some embodiments, the device further includes an integrated circuit die attached to the SoC, wherein the first pad is electrically connected to the first contact via the integrated circuit die.

[0104] One general aspect includes a method comprising receiving photons of extreme ultraviolet wavelengths at the back side of a substrate. The method further includes receiving the photons via a photon detector in the substrate, with a multilayer reflector attached to the front side of the substrate. The method also includes detecting the photons by generating an avalanche current in response to the photons.

[0105] In some embodiments, receiving the photons includes the photons passing through a passivation layer on the back side of the substrate. In some embodiments, the intensity of the extreme ultraviolet light including the photons is less than 50 W / mm². 2 When Sr is used, the passivation layer on the back side of the substrate has a thickness of less than about 5 nanometers. In some embodiments, when the intensity of the extreme ultraviolet light including the photons exceeds 50 W / mm². 2 Sr and less than 200W / mm 2 When Sr is used, the passivation layer on the back side of the substrate has a thickness of more than about 10 nanometers.

[0106] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the embodiments of this utility model, and are not intended to limit it. Although the embodiments of this utility model have been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this utility model.

Claims

1. A detector device, characterized by include: Photon detectors, including: Substrate; An isolation structure is located on the first side of the substrate; A protective ring is adjacent to the isolation structure and is located on the first side of the substrate; A sensor node is located on the first side of the substrate, and the protective ring is located between the sensor node and the isolation structure. A shared node, located on the first side of the substrate, between the guard ring and the isolation structure; and An isolation extension structure, wherein on a second side of the substrate opposite to the first side, the isolation extension structure extends from the second side to the isolation structure; and A multilayer reflector on the first side of the substrate.

2. The detector device of claim 1, wherein, Also includes: A dielectric layer is located between the isolation extension structure and the substrate.

3. The detector device of claim 1, wherein, The isolation extension structure includes: Conductive layer; Front contact, on the conductive layer; and The back contact is located on the conductive layer.

4. The detector device of claim 1, wherein, Also includes: The first contact extends through the multilayer reflector and is electrically connected to the sensor node; and The second contact extends through the multilayer reflector and is electrically connected to the shared node.

5. The detector device of claim 4, wherein, Also includes: A system-on-a-chip (SoC) is attached to the multilayer reflector, the SoC comprising: A first pad is electrically connected to the sensor node via a first contact on the surface of the system chip. as well as The second pad is electrically connected to the shared node via the second contact on the surface of the system chip.

6. The detector device of claim 5, wherein, Also includes: An integrated circuit die is attached to the system chip, wherein the first pad is electrically connected to the first contact through the integrated circuit die.

7. The detector device of claim 1, wherein, The multilayer reflector includes: It has two layers, including a molybdenum layer and a silicon layer.

8. The detector device of claim 1, wherein, Also includes: A passivation layer is applied to the second side of the substrate.

9. The detector device of claim 1, wherein, in: The guard ring includes a first dopant type; and The sensor node includes a second dopant type that is different from the first dopant type.

10. The detector device of claim 9, wherein, The shared node includes the first dopant type.

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