Semiconductor structure

Abstract

The utility model provides a kind of semiconductor structure. Structure includes first die and second die are located on substrate;And heat dissipation structure is located on substrate. Heat dissipation structure includes porous metal around first die;And through passage is located on second die. Structure further includes first thermal interface material and second thermal interface material. First thermal interface material contacts first die and heat dissipation structure. Second thermal interface material contacts second die and passes through through passage.

Description

Technical Field

[0001] This utility model relates to a semiconductor structure, and more particularly to a heat dissipation structure. Background Technology

[0002] In advanced electronic circuit applications, multiple integrated circuit chips (such as system-on-a-chip (SoC) chips and memory chips) can be integrated onto the same substrate to form an integrated circuit package. Since the performance of integrated circuit chips is affected by the heat they generate, heat dissipation is a critical issue in the design of integrated circuit packages. Utility Model Content

[0003] The purpose of this invention is to propose a semiconductor structure to solve at least one of the above-mentioned problems.

[0004] In some embodiments, the semiconductor structure includes a first die and a second die located on a substrate; and a heat dissipation structure located on the substrate. The heat dissipation structure includes porous metal surrounding the first die; and a through-channel located on the second die. The semiconductor structure also includes a first thermal interface material and a second thermal interface material. The first thermal interface material contacts the first die and the heat dissipation structure. The second thermal interface material contacts the second die and passes through the through-channel.

[0005] In some embodiments, the coverage of the first thermal interface material on the first grain is greater than 90%.

[0006] In some embodiments, a groove structure is also included on the second grain and connected to the through-channel.

[0007] In some embodiments, the groove structure includes four grooves extending from the periphery of the through-channel to a plurality of edges aligned with a region on the second grain.

[0008] In some embodiments, the groove structure includes four grooves extending from the periphery of the through-channel to a plurality of corners aligned with a region on the second grain.

[0009] In some embodiments, the groove structure includes sixteen grooves extending from the periphery of the through-channel to multiple edges and multiple corners aligned with a region on the second grain.

[0010] In some embodiments, the groove structure includes four grooves extending from the periphery of the through-channel to a plurality of edges of a region aligned with the second grain, some grooves extending beyond the four grooves extending from the periphery of the through-channel to the plurality of edges of the region aligned with the second grain, and some other grooves located around the periphery of the region aligned with the second grain.

[0011] In some embodiments, the groove structure includes four grooves extending from the periphery of the through-channel to a plurality of corners aligned with a region on the second grain, and some grooves extending beyond the four grooves extending from the periphery of the through-channel to the plurality of corners aligned with the region on the second grain.

[0012] In some embodiments, the ratio of the depth of the groove structure to the thickness of the heat dissipation structure is between 0.1 and 0.5. Attached Figure Description

[0013] Figure 1A This is a side view of a semiconductor package containing a heat dissipation structure in some embodiments.

[0014] Figure 1B This is a bottom view of the heat dissipation structure in some embodiments.

[0015] Figures 2A to 2F The image shows a pattern of a groove structure in one of the embodiments.

[0016] Figure 3 This is a flowchart of a method for forming a semiconductor package structure with a heat dissipation structure in some embodiments.

[0017] Figures 4 to 8 This is a side view of an intermediate structure of a semiconductor package with a heat dissipation structure during the manufacturing process, as shown in some embodiments.

[0018] The attached figures are labeled as follows:

[0019] θ: angle

[0020] A,L: Length

[0021] B,D,d1,d2,Q,W: Width

[0022] C, C5, C6, H, h: Thickness

[0023] G: Distance

[0024] S: Depth

[0025] 100: Structure

[0026] 102:Substrate

[0027] 103: Supporting Structure

[0028] 104: System-on-a-Chip Die

[0029] 106: Memory chip

[0030] 110: Heat dissipation structure

[0031] 114:Porous metal

[0032] 116: Passing through the passage

[0033] 118: Groove structure

[0034] 124: First type of area

[0035] 126: Second type of area

[0036] 134,534,634: Metal thermal interface materials

[0037] 136,836: Thermal interface material for memory

[0038] 300: Method

[0039] 305, 310, 315, 320, 325, 330: Steps

[0040] 540, 840: Syringe

[0041] 730: Flux vapor Detailed Implementation

[0042] The following detailed description, accompanied by accompanying drawings, is provided to facilitate understanding of the embodiments of this utility model.

[0043] The different embodiments or examples provided below can implement different structures of the present invention. The embodiments of specific components and arrangements are intended to simplify this disclosure and not to limit the present invention. For example, a description of forming a first component on a second component includes situations where the two are in direct contact, or where the two are spaced apart by other additional components rather than in direct contact.

[0044] In addition, spatial relative terms such as "below," "under," "lower side," "above," "upper side," or similar terms can be used to simplify the description of the relative relationship between one element and another in the illustration. Spatial relative terms can be extended to elements used in other directions, rather than being limited to the direction shown in the illustration. Elements can also be rotated 90 degrees or other angles, so directional terms are only used to describe the direction shown in the illustration.

[0045] In some embodiments, the terms "approximately" and "substantially" refer to a given value that varies within 20% (e.g., a target value ±1%, ±2%, ±3%, ±4%, ±5%, ±10%, ±20%). These values ​​are for illustrative purposes only and are not intended to limit the embodiments of the present invention. The percentage values ​​referred to by the terms "approximately" and "substantially" may be varied by those skilled in the art in accordance with the teachings herein.

[0046] In semiconductor electronic devices, multiple integrated circuit (IC) dies with different designated functions can be embedded on the same substrate to form an IC package. For example, a system-on-a-chip (SoC) die responsible for processing data and one or more memory dies responsible for storing data can be embedded on the substrate, with one or more memory dies surrounding the SoC die. In this structure, heat generated by the IC dies can be transferred to a heat dissipation structure embedded on the IC dies and then dissipated. The thermal interface material contacting the upper surface of the IC die and the lower surface of the heat dissipation structure facilitates heat conduction between the IC die and the heat dissipation structure. To optimize the performance of different IC dies according to their designated characteristics and functions, different thermal interface materials and different processes can be selected to create a reliable physical interface between the IC die and the heat dissipation structure. For example, a metallic thermal interface material can be applied to the upper surface of the SoC die and further processed using a reflow process. A memory thermal interface material can be applied to the upper surface of the memory die and further processed using a curing process. Compared to memory thermal interface materials, metal thermal interface materials applied to system-on-a-chip (SoC) dies can have higher thermal conductivity to effectively dissipate the larger amount of heat generated by the processor on the SoC die. Metal thermal interface materials may contain metallic elements. Multiple memory dies may surround a configured SoC die, and the metal thermal interface material may be applied prior to the application of the memory thermal interface material.

[0047] In some cases, different processes handling different thermal interface materials can interfere with each other and impair the thermal conductivity of the thermal interface materials. For example, once a metal thermal interface material and a memory thermal interface material are applied, the reflow process handling the metal thermal interface material may cause the metal thermal interface material to shrink and reduce the coverage of the metal thermal interface material on the system-on-die (SoC) die because of the memory thermal interface material on the adjacent memory die. This is because the memory thermal interface material is harder than the metal thermal interface material and avoids the shrinkage of the heat dissipation structure due to the deformation of the metal thermal interface material during the reflow process. Therefore, the capillary action of the narrow gap between the lower surface of the heat dissipation structure and the upper surface of the SoC die causes surface tension, resulting in the shrinkage of the metal thermal interface material. In some cases, bubbles and discontinuities may form in the metal thermal interface material after the reflow process, and the coverage of the metal thermal interface material on the SoC die may be reduced by about 30%. Specifically, reducing the coverage of the metal thermal interface material on the SoC die can significantly affect the characteristics of the area around the corners of the upper surface of the SoC die, which can be quantified by corner thermal resistance. In some cases, the corner thermal resistance can increase by about 2 times after a reflow process.

[0048] To overcome the aforementioned challenges, the embodiments described herein provide a method for forming a semiconductor package structure with a heat dissipation structure for heat dissipation. In some embodiments, a metal thermal interface material may be delivered onto the upper surface of a system-on-a-chip (SoC) die. Before applying the memory thermal interface material to the memory die, a heat dissipation structure may be embedded in the metal thermal interface material, with porous metal in the heat dissipation structure aligned with the SoC die and vias in the heat dissipation structure aligned with the memory die. A reflow process may then be performed to process the metal thermal interface material, and flux vapor released from the metal thermal interface material during the reflow process may be discharged through the vias. The memory thermal interface material may then be injected through the vias and delivered onto the memory die, followed by a curing process. In some embodiments, during the reflow process, shrinkage of the metal thermal interface material is avoided due to the absence of memory thermal interface material, and the metal thermal interface material maintains sufficient coverage on the upper surface of the SoC die. In some embodiments, during the reflow process, flux vapor released from the metal thermal interface material may pass through the porous metal and be discharged through the vias to prevent condensation and contamination of the internal surfaces of the structure. In some embodiments of the reflow process, the porous metal can effectively absorb any overflowing metal thermal interface material on the edge of the system on-chip die, ensuring that the metal thermal interface material is within the range of the upper surface of the system on-chip die and avoiding contamination of other parts of the structure by the metal thermal interface material.

[0049] Figure 1A This is a side view of a semiconductor package with a heat dissipation structure in some embodiments. Figure 1B This is a bottom view of the heat dissipation structure in some embodiments. For example... Figure 1A As shown, structure 100 may include substrate 102. Substrate 102 may extend along a horizontal direction (e.g., x and / or y axis), and its upper surface may be perpendicular to a vertical direction (e.g., z axis). Substrate 102 may include a semiconductor material such as silicon. In some embodiments, substrate 102 may include a crystalline silicon substrate such as a silicon wafer. In some embodiments, substrate 102 may include (i) semiconductor elements such as silicon or germanium; (ii) semiconductor compounds such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; (iii) semiconductor alloys such as silicon germanium carbide, silicon germanium, gallium arsenide phosphide, gallium indium phosphide, gallium indium arsenide, gallium indium arsenide phosphide, aluminum indium arsenide, and / or aluminum gallium arsenide; or (iv) combinations thereof. Furthermore, substrate 102 may be doped according to design requirements (e.g., p-type substrate or n-type substrate). In some embodiments, substrate 102 may be undoped. In some embodiments, substrate 102 may be doped with p-type dopants (e.g., boron, indium, aluminum, or gallium) or n-type dopants (e.g., phosphorus, arsenic, or antimony). In some embodiments, the crystal orientation of the substrate 102 may be (100), (110), or (111).

[0050] Structure 100 may include several integrated circuit chips for different functions. Figure 1A For example, structure 100 may include a first integrated circuit die (such as a system-on-a-chip die 104) and one or more second integrated circuit dies (such as memory dies 106) adjacent to and / or surrounding the first integrated circuit die. Structure 100 may also include a heat dissipation structure 110 embedded on the integrated circuit die to provide heat dissipation required by the integrated circuit die. Structure 100 may also include a support structure 103 located on the substrate 102 and supporting the edge of the heat dissipation structure 110. The heat dissipation structure 110 may have a thickness H between its upper and lower surfaces. Structure 100 may also include several thermal interface materials located between the heat dissipation structure 110 and the integrated circuit die to transfer heat generated by the integrated circuit die to the heat dissipation structure 110. Some embodiments take into account the characteristics and functional differences of integrated circuit dies (such as the heat generated by the crystal circuit die and the characteristics of the upper surface of the integrated circuit die), and different types of thermal interface materials may be placed on the integrated circuit die according to design requirements. Figure 1A For example, a first thermal interface material (such as metal thermal interface material 134) may be located on the upper surface of the system-on-a-chip (SoC) die 104 to form a thermal contact between the heat dissipation structure 110 and the SoC die 104. One or more second thermal interface materials (such as memory thermal interface material 136) may be located on the upper surface of the memory die 106 to form a thermal contact between the heat dissipation structure 110 and the memory die 106. The metal thermal interface material 134 and the memory thermal interface material 136 must be treated differently to form a reliable physical interface between the corresponding integrated circuit die and the heat dissipation structure 110. For example, the metal thermal interface material 134 may be processed in a reflow process, and the memory thermal interface material 136 may be processed in a curing process. Figure 1A As shown, the metal thermal interface material 134 may have a thickness C. In some embodiments, the thickness C may be less than about 120 micrometers. For example, the thickness C may be about 97 micrometers. In some embodiments, the metal thermal interface material 134 may cover all or nearly all of the upper surfaces of the system-on-wafer die 104. For example, the coverage of the metal thermal interface material 134 on the upper surface of the system-on-wafer die 104 may be greater than about 90%. In another example, the coverage of the metal thermal interface material 134 on the upper surface of the system-on-wafer die 104 may be about 99.8%. In some embodiments, the corner thermal resistance of the metal thermal interface material 134 may be less than about 0.3 °C / W. For example, the corner thermal resistance of the metal thermal interface material 134 may be about 0.24 °C / W.

[0051] In some embodiments, the lower surface of the heat dissipation structure 110 may include different regions, each aligned with one of the upper surfaces of the integrated circuit die. For example... Figure 1A As shown, the heat dissipation structure 110 may include a first region 124 aligned with the upper surface of a first integrated circuit die (such as a system-on-a-chip die 104). Figure 1B In some embodiments shown, the first region 124 may be located in the central region of the lower surface of the heat dissipation structure 110. In some embodiments, the first region 124 and the upper surface of the system-on-wafer die 104 may be rectangular, having a width B and a length A. In some embodiments, the first region 124 and the upper surface of the system-on-wafer die 104 may be square, with a width B and a length A that are substantially the same. The heat dissipation structure 110 may also include one or more second regions 126 aligned with the upper surface of a second integrated circuit die (such as the memory die 106 shown in FIG. 2). Figure 1B In some embodiments shown, the second region 126 may be adjacent to and / or surround the first region 124. The first region 124 and each of the second regions 126 may be separated by a distance G. In some embodiments, the second region 126 and the upper surface of the memory die 106 may be rectangular, having a width W and a length L. In some embodiments, the second region 126 and the upper surface of the memory die 106 may be square, with a width W and a length L that are substantially the same.

[0052] like Figure 1A In some embodiments shown, the heat dissipation structure 110 may include a through-channel 116 aligned with the memory thermal interface material 136. After reflowing the metal thermal interface material 134, the memory thermal interface material 136 may be injected through the through-channel 116 onto the upper surface of the memory die 106. In some embodiments, during reflow, the through-channel 116 facilitates the passage and venting of flux vapors released from the metal thermal interface material 134. In some embodiments, the through-channel 116 may be partially or completely filled with the memory thermal interface material 136. Each through-channel 116 may extend through the heat dissipation structure 110, having a first port located on the upper surface of the heat dissipation structure 110 and a second port located on the lower surface of the heat dissipation structure 110. The second port may be located in one of the second regions 126. Figure 1B For example, the second port of each of the passageways 116 is located around the center of each of the second types of regions 126. Figure 1B In some embodiments shown, the through-channels 116 may each have a circular cross-section. In some embodiments, the cross-section of the through-channels 116 may be other shapes such as triangular, rectangular, hexagonal, elliptical, or irregular. Figure 1A In some embodiments shown, the inner sidewall of the through-channel 116 may be perpendicular to the upper surface of the heat dissipation structure 110, making the through-channel 116 cylindrical. In some embodiments, the inner sidewall of the through-channel 116 may be inclined relative to a vertical direction (such as the z-axis). For example, the through-channel 116 may be tapered, such that the widths of the first port and the second port are different. Figure 1AAs shown, each of the passageways 116 may have a width D. In some embodiments, the ratio of width D to length L of the second region 126 may be less than about 0.1. In some embodiments, the ratio of width D to width W of the second region 126 may be less than 0.1.

[0053] like Figure 1A and 1B As shown, porous metal 114 may be located on the lower surface of heat dissipation structure 110. In some embodiments, porous metal 114 may be embedded on the lower surface of heat dissipation structure 110 by a forging process. In some embodiments, porous metal 114 may be located between metal thermal interface material 134 and memory metal thermal interface material 136, or between system-on-a-chip die 104 and memory die 106, or between first region 124 and second region 126. Figure 1A In some embodiments shown, the porous metal 114 may partially or completely enclose the metal thermal interface material 134. For example... Figure 1B In some embodiments shown, the porous metal 114 may partially or completely enclose the first region 124. In some embodiments, the porous metal 114 may include pores that can absorb overflow of the metal thermal interface material 134 during reflow soldering to prevent the overflow of the metal thermal interface material 134 from contaminating areas outside the first region 124. In some embodiments, during reflow soldering, the pores of the porous metal 114 facilitate the passage of flux vapors released from the metal thermal interface material 134 through the pores and through the passage channel 116. In some embodiments, the porosity of the porous metal 114 may be between about 1% and about 70%. For example, the porosity of the porous metal 114 may be about 5%, about 10%, about 20%, about 30%, about 40%, about 50%, about 60%, or about 70%. The porous metal 114 may include a metallic element or a metallic alloy. For example, porous metal 114 may include tungsten, titanium, silver, ruthenium, molybdenum, copper, cobalt, aluminum, iridium, nickel, or a combination thereof.

[0054] In some embodiments, the shape of the porous metal 114 may conform to the periphery of the first region 124. Figure 1BFor example, the porous metal 114 may be a rectangular ring, including a first edge of width d1 and a second edge of width d2. The first edge is located between a first region 124 and a second region 126. In some embodiments, the ratio of width d1 to distance G may be between about 0.1 and about 1. For example, the ratio of width d1 to distance G may be about 0.1, about 0.2, about 0.3, about 0.4, about 0.5, about 0.6, about 0.7, about 0.7, about 0.9, or about 1. If the ratio of width d1 to distance G is greater than 1, the first edge of the porous metal 114 may not be able to be installed between the first region 124 and the second region 126, affecting the coverage of the metal thermal interface material 134 on the upper surface of the system on wafer die 104 and / or the coverage of the memory thermal interface material 136 on the upper surface of the memory die 106. If the ratio of width d1 to distance G is less than about 0.1, then width d1 may be too small to adequately absorb the overflow of metal thermal interface material 134 during reflow.

[0055] like Figure 1A As shown, the porous metal 114 may have a thickness h. In some embodiments, the ratio of thickness h to the thickness C of the metal thermal interface material 134 may be between about 0.1 and about 1. For example, the ratio of thickness h to thickness C may be about 0.1, about 0.2, about 0.3, about 0.4, about 0.5, about 0.6, about 0.7, about 0.8, about 0.9, or about 1. If the ratio of thickness h to thickness C is greater than 1, there is a risk that the porous metal 114 may come into contact with the integrated circuit die due to misalignment and / or vibration, affecting the function of the integrated circuit die. If the ratio of thickness h to thickness C is less than 0.1, the thickness h may be too small to adequately absorb the overflow of the metal thermal interface material 134 during reflow processing.

[0056] like Figure 1A and 1B In some embodiments shown, the heat dissipation structure 110 may include a groove structure 118 located on the lower surface of the heat dissipation structure 110 and connected to the through-channel 116. The groove structure 118 may be located in the second region 126 and aligned with the upper surface of the memory die 106. When the memory thermal interface material 136 is injected through the through-channel 116, the memory thermal interface material 136 can be distributed along the groove structure 118 via capillary force and delivered onto the upper surface of the memory die 106. The groove structure 118 may include a plurality of grooves extending radially from each of the through-channels 116. Figure 1BFor example, the through-channel 116 can each connect to eight recesses extending from the periphery of the through-channel 116 to the corners of the second region 126. The angle θ between adjacent recesses can depend on the width W and length L (e.g., arctan(W / L) or arctan(L / W)). For example, if the second region 126 is square, the angle θ can be approximately 45 degrees. Each recess can have a width Q, such as... Figure 1B As shown. In some embodiments, the ratio of width Q to width W of the second region 126 may be between about 0.01 and about 0.1. Each groove has a depth S between the lower surface of the heat dissipation structure 110 and the bottom of the groove structure 118, as shown. Figure 1A As shown. In some embodiments, the ratio of depth S to thickness H of heat dissipation structure 110 may be between about 0.1 and about 0.5. If the ratio of width Q to width W is less than about 0.01 and / or the ratio of depth S to thickness H is less than about 0.1, the profile of the groove may be too small to effectively distribute the memory thermal interface material 136 to the edge of the second region 126. If the ratio of width Q to width W is greater than about 0.1 and / or the ratio of depth S to thickness H is greater than 0.5, the profile of the groove may be too large to provide sufficient capillary force to drive the memory thermal interface material 136 to the edge and / or corner of the second region 126. In some embodiments, the profile of the groove may be rectangular, triangular, arc-shaped, semi-circular, arched, or an irregular pattern.

[0057] like Figures 2A to 2F As shown, the groove structure 118 in some embodiments may have different patterns. The above description of the groove structure 118 can be used for... Figures 2A to 2F Unless otherwise stated. Figure 2A The groove structure 118 may have Figure 1B The same pattern shown. Figure 2B The groove structure 118 has four grooves extending from the periphery of the self-penetrating channel 116 to the edge of the second region 126, the four grooves being parallel to the edge and the angle between adjacent grooves being approximately 90 degrees. Figure 2C The groove structure 118 has four grooves extending from the periphery of the self-penetrating channel 116 to the corner of the second region 126. The four grooves are along the diagonal of the second region 126, and the angle between adjacent grooves is approximately 90 degrees. Figure 2D The groove structure 118 has sixteen grooves extending from the periphery of the self-penetrating channel 116 to the corners and edges of the second region 126, and the angle between adjacent grooves is approximately 22.5 degrees. Figure 2E Apart from Figure 2B In addition to the pattern shown, the groove structure 118 may further include some grooves extending beyond the four grooves (from the periphery of the through-channel 116 to the corner of the second region 126), and some grooves located around the periphery of the second region 126. Figure 2F Apart from Figure 2C In addition to the pattern shown, the groove structure 118 may further include some grooves extending beyond the four grooves (from the periphery of the self-penetrating channel 116 to the corner of the second region 126).

[0058] In some embodiments, the pattern of all the groove structures 118 of the heat dissipation structure 110 can be as follows: Figures 2A to 2F The same pattern of any of them. In some embodiments, the patterns of the different groove structures 118 of the heat dissipation structure 110 may be: Figures 2A to 2F Different patterns in the picture.

[0059] In some embodiments, Figure 3 Showing formation Figure 1A and 1B The flowchart of method 300 with structure 100 shown is provided. This embodiment of the invention is not limited to the description of these steps, and additional steps may be performed. Other steps may be performed between the various steps of method 300, but descriptions of these other steps are omitted for clarity. Furthermore, not all steps provided herein need to be performed. Additionally, some steps may be performed simultaneously, or in a manner different from... Figure 3 The steps are performed in the order shown. In some embodiments, one or more additional steps may be performed, or the steps described herein may be replaced with one or more other steps. For illustrative purposes, they will be paired with... Figures 4 to 8 The intermediate structure shown is illustrated in method 300. Figure 1A and 1B The same reference numerals in the cell description can be used Figures 4 to 8 Unless otherwise stated.

[0060] Figure 3 The method 300 shown initially provides structure 100 in step 305, as follows: Figure 4 As shown. The structure 100 of this stage of method 300 may include a substrate 102 with a plurality of integrated circuit dies located on the substrate 102. Figure 4 For example, structure 100 may include a first integrated circuit die (such as a system-on-a-chip die 104), a second integrated circuit die, and a third integrated circuit die (such as memory dies 106 located on a first side and a second side adjacent to the system-on-a-chip die 104, respectively). Structure 100 may also include a support structure 103 located on substrate 102 to support a heat dissipation structure installed in subsequent steps.

[0061] Figure 3 Step 310 of method 300, as shown, involves distributing a first thermal interface material onto the first integrated circuit die, such as... Figure 5 As shown. Figure 5 In some embodiments shown, the first thermal interface material may be a metallic thermal interface material 534. For example... Figure 5In some embodiments shown, the first thermal interface material may be a metal thermal interface material 534. In some embodiments, the metal thermal interface material 534 prior to being delivered onto the system-on-wafer die 104 may be in the form of a liquid, grease, or epoxide originally stored in the syringe 540. In some embodiments, the volume of the metal thermal interface material 534 delivered onto the system-on-wafer die 104 can be controlled so that the metal thermal interface material 534 can cover all upper surfaces of the system-on-wafer die 104, such as... Figure 5 As shown. In some embodiments, the volume of the metal thermal interface material 534 delivered onto the system-on-wafer die 104 can be controlled, such that the metal thermal interface material 534 can partially cover the upper surface of the system-on-wafer die 104 (e.g., the central region of the upper surface). The volume of the metal thermal interface material 534 delivered onto the system-on-wafer die 104 can be controlled, such that the metal thermal interface material 534 can have a thickness C5, such as... Figure 5 As shown.

[0062] Figure 3 Step 315 of method 300 shown can then be used to install a heat dissipation structure onto the substrate, such as... Figure 6 As shown. For example, the heat dissipation structure 110 may be placed or embedded on the system-on-a-chip (SoC) die 104 and the memory die 106. In some embodiments, the first thermal interface material may be deformed due to the presence of the heat dissipation structure 110. For example, the metal thermal interface material 534 may be deformed into a metal thermal interface material 634, and the thickness C6 of the metal thermal interface material 634 may be different from the thickness C5. In some embodiments, since the metal thermal interface material 634 is in the form of liquid, grease, or epoxide, it may physically fill the space (e.g., gap) between the lower surface of the heat dissipation structure 110 and the upper surface of the SoC die 104. In some embodiments, the heat dissipation structure 110 may not contact the support structure 103 due to the presence of the metal thermal interface material 634. In some embodiments, the heat dissipation structure 110 may contact the support structure 103. In some embodiments, the method of mounting the heat dissipation structure 110 may include aligning the heat dissipation structure 110 and the SoC die 104 such that a porous metal 114 on the lower surface of the heat dissipation structure 110 surrounds or encloses the metal thermal interface material 634. In some embodiments, the method of installing the heat dissipation structure 110 may include aligning the heat dissipation structure 110 with the memory die 106, such that the through-channel 116 in the heat dissipation structure 110 is located on the memory die 106 (e.g., on the central region of the memory die 106). In some embodiments, the method of installing the heat dissipation structure 110 may include aligning the heat dissipation structure 110 with the memory die 106, such that the recess structure 118 of the heat dissipation structure 110 is located on the memory die 106.

[0063] Step 320 of method 300 then involves reflowing the first metal thermal interface material, such as... Figure 7As shown. The reflow process can be a hot reflow process, and during this stage, the structure can be heated by 100° to soften and reshape it. Figure 6 Metal thermal interface material 634 Figure 7 The metal thermal interface material 134 is mechanically bonded to the system-on-chip die 104 and the heat dissipation structure 110. This mechanical bonding ensures reliable thermal junctions are formed between the metal thermal interface material 134 and the system-on-chip die 104, and between the metal thermal interface material 134 and the heat dissipation structure 110. In some embodiments, a... Figure 7 The structure 100 shown is placed in a ventilated oven or furnace for reflow soldering. In some embodiments, during reflow soldering, the metal thermal interface material 134 releases flux vapor 730 due to heating, which can flow through the porous metal 114 and exit via through-channels 116. In some embodiments, the through-channels 116 present in the heat dissipation structure 110 facilitate the release of flux vapor 730 outside the structure 100 to prevent flux vapor 730 from condensing and contaminating surfaces in the structure 100. In some embodiments, the reflow soldering process may reduce the volume of the metal thermal interface material 134 (due to the release of flux vapor 730). Due to the support of the metal thermal interface material 134, the heat dissipation structure 110 can be correspondingly recessed to accommodate the volume reduction of the metal thermal interface material 134. This ensures that the metal thermal interface material 134 maintains sufficient coverage on the upper surface of the system-on-a-chip (SoC) die 104, without shrinking towards the center region of the SoC die 104 or generating bubbles between the metal thermal interface material 134 and the SoC die 104 or between the metal thermal interface material 134 and the heat dissipation structure 110. In some embodiments, after reflow soldering, the thickness C of the metal thermal interface material 134 is less than... Figure 6 The thickness C6 of the metal thermal interface material 634 shown. In some embodiments, the heat dissipation structure 110 after reflow may be recessed and contact the support structure 103. In some embodiments, the corner thermal resistance of the metal thermal interface material 134 may be maintained at the same level as before the reflow. For example, the corner thermal resistance may be maintained to be less than about 0.25°C / W. In some embodiments, the porous metal 114 during reflow may absorb the overflow of the metal thermal interface material 134 on the edge of the system-on-wafer die 104, ensuring that the metal thermal interface material 134 is within the range of the upper surface of the system-on-wafer die 104 and preventing the metal thermal interface material 134 from contaminating other parts of the structure 100.

[0064] Figure 3 Step 325 of method 300, as shown, involves injecting a second thermal interface material onto the second and / or third grains, such as... Figure 8 As shown. Figure 8In some embodiments shown, the second thermal interface material may be a memory thermal interface material 836. In some embodiments, the memory thermal interface material 836 prior to delivery onto the memory die 106 may be a liquid, grease, or epoxide stored in the syringe 840. The injectable memory thermal interface material 836 passes through the through-channel 116 and flows along the groove structure 118 to be evenly distributed and transferred onto the upper surface of the memory die 106. In some embodiments, the volume of the memory thermal interface material 836 delivered onto the memory die 106 can be controlled so that the memory thermal interface material 836 covers all upper surfaces of the memory die 106, such as... Figure 8 As shown. In some embodiments, the volume of the memory thermal interface material 836 distributed on the memory die 106 can be controlled, such that the memory thermal interface material 836 contacts the upper surface of the memory die 106 and the lower surface of the heat dissipation structure 110. In some embodiments, the volume of the memory thermal interface material 836 distributed on the memory die 106 can be controlled, such that the memory thermal interface material 836 can partially or completely fill the through-channel 116. Figure 8 For example, the upper surface of the memory thermal interface material 836 may be coplanar with the upper surface of the heat dissipation structure 110. In some embodiments, during the delivery of the memory thermal interface material 836, a porous metal 114 aligned between the memory die 106 and the system-on-a-chip (SoC) die 104 can absorb the overflow of the memory thermal interface material 836 outside the upper surface of the memory die 106, so as to prevent the memory thermal interface material 836 from contaminating other parts of the structure 100 (such as the SoC die 104).

[0065] Figure 3 Step 330 of method 300, as shown, involves curing the second thermal interface material. For example, the curing process can harden... Figure 8 The memory thermal interface material 836 in Figure 1 forms a solid memory thermal interface material 136 and forms a mechanical bond between the memory die 106 and the heat dissipation structure 110 to ensure a reliable thermal junction. In some embodiments, a curing process can be performed at a temperature above room temperature for a rapid curing time, and the curing process can be considered as a rapid curing process. In some embodiments, the curing process on structure 100 can be performed in an oven or furnace such as a rapid heat treatment furnace.

[0066] The embodiments described herein relate to a method for forming a semiconductor package structure with a heat dissipation structure for heat dissipation. The method includes distributing a first thermal interface material onto a first integrated circuit die on a substrate; embedding a heat dissipation structure onto the first thermal interface material; performing a reflow process on the first thermal interface material to form a first thermal contact between the heat dissipation structure and the first integrated circuit die; injecting a second thermal interface material through a through-channel in the heat dissipation structure onto a second integrated circuit die on the substrate, aligning the second thermal interface material with the second integrated circuit die; and performing a curing process on the second thermal interface material to form a second thermal contact between the heat dissipation structure and the second integrated circuit die. Because the reflow process on the first thermal interface material is performed before distributing the second thermal interface material onto the second integrated circuit, the first thermal contact is not affected by the second thermal interface material. Therefore, a reduction in the coverage of the first thermal interface material on the first integrated circuit die can be avoided, thereby preventing deterioration of the quality of the first thermal contact. Furthermore, features of the heat dissipation structure can provide additional advantages to the method, including (i) the porous metal on the lower surface of the heat dissipation structure being aligned between the first integrated circuit die and the second integrated circuit die, which can absorb overflow of the first thermal interface material and / or the second thermal interface material; (ii) the through-channel facilitating the discharge of the first flux vapor released by the first thermal interface material during the reflow process; and (iii) the groove structure connected to the through-channel and aligned with the second integrated circuit die can guide the flow of the second thermal interface material to evenly distribute the second thermal interface material on the second integrated circuit die.

[0067] In some embodiments, a method for forming a semiconductor structure includes providing a substrate, wherein the substrate includes a first die and a second die on the substrate; dispensing a first thermal interface material onto the first die; forming a heat dissipation structure on the substrate, wherein the step of forming the heat dissipation structure includes aligning a porous metal of the heat dissipation structure with the first die; and forming a contact between the first thermal interface material and the heat dissipation structure. The method further includes performing a reflow soldering process on the first thermal interface material; injecting a second thermal interface material through a through-channel in the heat dissipation structure onto the second die; and curing the second thermal interface material.

[0068] In some embodiments, the step of forming the heat dissipation structure further includes aligning the through-channel and the second grain.

[0069] In some embodiments, the step of forming a heat dissipation structure further includes aligning the groove structure of the heat dissipation structure with the second grain, wherein the groove structure is connected to the through channel.

[0070] In some embodiments, the step of aligning the porous metal of the heat dissipation structure with the first grain includes sealing the first thermal interface material with the porous metal.

[0071] In some embodiments, the reflow process includes venting flux vapors released from the first thermal interface material via a through-channel.

[0072] In some embodiments, the reflow process includes using a porous metal to absorb a first thermal interface material overflowing from the first grain.

[0073] In some embodiments, the step of injecting a second thermal interface material includes injecting the second thermal interface material after performing a reflow process.

[0074] In some embodiments, the step of injecting the second thermal interface material includes distributing the second thermal interface material along the groove structure of the heat dissipation structure.

[0075] In some embodiments, the method of forming a semiconductor structure includes providing a first die and a second die on a substrate, wherein the first die and the second die are spaced apart; dispensing a first thermal interface material onto the first die; embedding a heat dissipation structure onto the first die and the second die, wherein the porous metal of the heat dissipation structure is located between the first die and the second die; forming a first thermal contact between the first die and the heat dissipation structure via the first thermal interface material; injecting a second thermal interface material through a through-channel in the heat dissipation structure onto the second die; and forming a second thermal contact between the second die and the heat dissipation structure via the second thermal interface material.

[0076] In some embodiments, the step of forming the first thermal contact includes performing a reflow process.

[0077] In some embodiments, the step of forming the first thermal junction includes maintaining the coverage of the first thermal interface material on the upper surface of the first grain.

[0078] In some embodiments, the step of forming the first thermal contact includes reducing the thickness of the first thermal interface material.

[0079] In some embodiments, the step of forming the first thermal junction includes maintaining the corner thermal resistance of the first thermal interface material at less than 0.25°C / W.

[0080] In some embodiments, the step of injecting the second thermal interface material delivers the second thermal interface material via a groove structure of a heat dissipation structure, wherein the groove structure is connected to the through-channel and located on the second grain.

[0081] In some embodiments, the step of forming the second thermal junction includes a curing process.

[0082] In some embodiments, the semiconductor structure includes a first die and a second die located on a substrate; and a heat dissipation structure located on the substrate. The heat dissipation structure includes porous metal surrounding the first die; and a through-channel located on the second die. The semiconductor structure also includes a first thermal interface material and a second thermal interface material. The first thermal interface material contacts the first die and the heat dissipation structure. The second thermal interface material contacts the second die and passes through the through-channel.

[0083] In some embodiments, the coverage of the first thermal interface material on the first grain is greater than about 90%.

[0084] In some embodiments, the corner thermal resistance of the first thermal interface material is less than about 0.25°C / W.

[0085] In some embodiments, the semiconductor structure further includes a groove structure located on the second die and connected to the through-channel.

[0086] In some embodiments, the groove structure includes a plurality of edges and a plurality of corners of eight grooved self-penetrating channels extending to a region aligned with the second grain.

[0087] In some embodiments, the groove structure includes four grooved self-penetrating channels extending around the periphery to multiple edges of the region aligned with the second grain.

[0088] In some embodiments, the groove structure includes four grooved self-penetrating channels extending around the periphery to multiple corners of the region aligned with the second grain.

[0089] In some embodiments, the groove structure includes a plurality of edges and a plurality of corners of sixteen grooved self-penetrating channels extending to a region aligned with the second grain.

[0090] In some embodiments, the groove structure includes four grooves extending from the periphery of the self-penetrating channel to multiple edges of the region aligned with the second grain, four grooves extending beyond the periphery of the self-penetrating channel to the edges of the region aligned with the second grain, and several other grooves located around the periphery of the region aligned with the second grain.

[0091] In some embodiments, the groove structure includes four grooves extending around the periphery of the self-penetrating channel to multiple corners of the region aligned with the second grain, and four grooves extending beyond the periphery of the self-penetrating channel to the corners of the region aligned with the second grain.

[0092] In some embodiments, the ratio of the depth of the groove structure to the thickness of the heat dissipation structure is between about 0.1 and about 0.5.

[0093] It should be understood that the embodiments (not the abstract) are used to illustrate the claims. The abstract may refer to one or more, but not all, possible embodiments of the present invention, and is therefore not intended to limit the appended claims.

[0094] The features of the above embodiments are beneficial for those skilled in the art to understand the present invention. Those skilled in the art should understand that the present invention can be used as a basis to design and vary other processes and structures to achieve the same purpose and / or the same advantages of the above embodiments. Those skilled in the art should also understand that these equivalent substitutions do not depart from the spirit and scope of the present invention, and changes, substitutions, or modifications can be made without departing from the spirit and scope of the present invention.

Claims

1. A semiconductor structure, characterized in that, include: A first grain and a second grain are located on a substrate; A heat dissipation structure is located on the substrate, wherein the heat dissipation structure includes: A porous metal surrounding the first grain; and A through-channel is located on this second grain; A first thermal interface material contacts the first grain and the heat dissipation structure; and A second thermal interface material contacts the second grain and passes through the penetration channel.

2. The semiconductor structure as described in claim 1, characterized in that, The coverage of the first thermal interface material on the first grain is greater than 90%.

3. The semiconductor structure as described in claim 1, characterized in that, It also includes a groove structure located on the second grain and connected to the through-channel.

4. The semiconductor structure as described in claim 3, characterized in that, The groove structure includes eight grooves extending from the periphery of the through-channel to multiple edges and corners aligned with a region on the second grain.

5. The semiconductor structure as described in claim 3, characterized in that, The groove structure includes four grooves extending from the periphery of the through-channel to multiple edges aligned with a region on the second grain.

6. The semiconductor structure as described in claim 3, characterized in that, The groove structure includes four grooves extending from the periphery of the through-channel to multiple corners aligned with a region on the second grain.

7. The semiconductor structure as described in claim 3, characterized in that, The groove structure includes sixteen grooves extending from the periphery of the through-channel to multiple edges and corners aligned with a region on the second grain.

8. The semiconductor structure as described in claim 3, characterized in that, The groove structure includes four grooves extending from the periphery of the through-channel to multiple edges of a region aligned with the second grain, some grooves extending beyond the four grooves extending from the periphery of the through-channel to the multiple edges of the region aligned with the second grain, and some other grooves located around the periphery of the region aligned with the second grain.

9. The semiconductor structure as described in claim 3, characterized in that, The groove structure includes four grooves extending from the periphery of the through-channel to multiple corners aligned with a region on the second grain, and some grooves extending beyond the four grooves extending from the periphery of the through-channel to multiple corners aligned with the region on the second grain.

10. The semiconductor structure as described in claim 3, characterized in that, The ratio of the depth of the groove structure to the thickness of the heat dissipation structure is between 0.1 and 0.5.

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