Method of manufacturing a semiconductor structure

Abstract

The embodiment of the present disclosure provides a manufacturing method of a semiconductor structure, comprising: providing a substrate, the substrate crossing an adjacent array region and a peripheral region; forming a first mask layer on the substrate in the array region and the peripheral region, wherein the first mask layer in the array region has a plurality of openings, and the openings pass through the first mask layer; forming a filling layer, the filling layer covers the top surface of the first mask layer and fills the openings; forming a second mask layer on the filling layer in the peripheral region; removing the filling layer higher than the top surface of the first mask layer in the array region under a first bias power condition by using a first etching process; removing the remaining filling layer in the array region under a second bias power condition by using a second etching process; and wherein the first bias power is greater than the second bias power. The embodiment of the present disclosure is at least beneficial to improve the performance and yield of the formed semiconductor structure.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor manufacturing technology, and in particular to a method for manufacturing a semiconductor structure. Background Technology

[0002] As semiconductor process nodes continue to advance, the critical dimension (CD) requirements in both front-end online (FEOL) and back-end online (BEOL) processes for semiconductor device fabrication are becoming increasingly stringent. To obtain semiconductor structures with smaller feature sizes, it is typically necessary to perform large-scale photolithography followed by processes such as dry etching, or plasma etching, to shrink the feature size and obtain semiconductor structures with even smaller feature sizes. However, while obtaining semiconductor structures with smaller feature sizes, problems may arise such as high line edge roughness of the etched structure and the etching of other structures adjacent to it.

[0003] Currently, the etching process in semiconductor structure fabrication still needs improvement. Summary of the Invention

[0004] This disclosure provides a method for manufacturing a semiconductor structure, which at least helps to improve the performance and yield of the semiconductor structure.

[0005] According to some embodiments of this disclosure, one aspect of this disclosure provides a method for manufacturing a semiconductor structure, comprising: providing a substrate spanning an adjacent array region and a peripheral region; forming a first mask layer on the substrate in the array region and the peripheral region, wherein the first mask layer located in the array region has a plurality of openings penetrating the first mask layer; forming a filling layer covering the top surface of the first mask layer and filling the openings; forming a second mask layer located on the filling layer in the peripheral region; using a first etching process under a first bias power condition, removing the filling layer in the array region above the top surface of the first mask layer; using a second etching process under a second bias power condition, removing the remaining filling layer in the array region; wherein the first bias power is greater than the second bias power.

[0006] In some embodiments, the first bias power is 3.5 to 10 times the second bias power.

[0007] In some embodiments, the second etching process has a preset etching duration, and the ratio of the actual etching duration of the second etching process to the preset etching duration is 1.2 to 1.5.

[0008] In some embodiments, the material of the first mask layer includes polycrystalline silicon; the etching gas used in both the first etching process and the second etching process includes oxygen, wherein the oxygen gas flow rate in the first etching process is greater than or equal to the oxygen gas flow rate in the second etching process.

[0009] In some embodiments, in the first etching process, the source power is further adjusted to a first source power; in the second etching process, the source power is further adjusted to a second source power; wherein the first source power is less than or equal to the second source power.

[0010] According to some embodiments of this disclosure, another aspect of this disclosure provides a method for manufacturing another semiconductor structure, comprising: providing a substrate spanning an adjacent array region and a peripheral region; forming a first mask layer on the substrate in the array region and the peripheral region, wherein the first mask layer in the array region has a plurality of openings penetrating the first mask layer; forming a filling layer covering the top surface of the first mask layer and filling the openings; forming a second mask layer on the filling layer in the peripheral region; and removing the filling layer in the array region under a preset source power condition; wherein the preset source power is 300W to 1000W.

[0011] In some embodiments, the fill layer in the array region is removed under no bias power conditions.

[0012] In some embodiments, the step of removing the fill layer of the array region has a preset etching duration, and the ratio of the actual etching duration of the step of removing the fill layer of the array region to the preset etching duration is 1.2 to 2.

[0013] In some embodiments, the step of removing the fill layer in the array region includes: using a third etching process to remove the fill layer in the array region above the top surface of the first mask layer under a first source power condition; and using a fourth etching process to remove the remaining fill layer in the array region under a second source power condition; wherein the first source power is less than or equal to the second source power.

[0014] In some embodiments, the filler layer contains carbon; in the step of removing the filler layer from the array region, an etching endpoint detection system is also used to monitor the carbon concentration on the top surface of the first mask layer of the array region and in the opening of the array region.

[0015] The technical solutions provided in this disclosure have at least the following advantages:

[0016] This disclosure provides a method for manufacturing a semiconductor structure. In the first etching process, a higher first bias power is used to increase the energy of the plasma, thereby accelerating the vertical physical bombardment of the fill layer by the plasma and shortening the first etching process time. This shortens the chemical etching time in the first etching process. Since chemical etching, with its strong isotropic properties, easily erodes the fill layer adjacent to the array region in the peripheral region, the likelihood of the fill layer in the peripheral region adjacent to the array region being etched in the first etching process is reduced. Then, in the second etching process, under a second bias power lower than the first bias power, the remaining fill layer in the array region is removed. This results in a relatively lower energy plasma used in the second etching process, slowing down the vertical physical bombardment of the plasma and reducing the likelihood of the exposed first mask layer in the first etching process being bombarded by the plasma. This is beneficial for improving the yield of the formed semiconductor structure.

[0017] Another embodiment of this disclosure provides a method for manufacturing a semiconductor structure. In the step of removing the filler layer in the array region, a preset source power of 300W to 1000W is used. Within this power range, the source power is relatively small, resulting in a lower concentration of plasma generated during the removal of the filler layer in the array region. This reduces the chemical etching rate and the influence of the isotropic nature of chemical etching on the etching morphology of the filler layer. Consequently, it reduces the etching rate of the filler layer adjacent to the array region in the peripheral region during the removal of the filler layer above the top surface of the first mask layer in the array region. This is to obtain a semiconductor structure with the desired morphology, which is beneficial to improving the performance and yield of the formed semiconductor structure. Furthermore, it allows for the removal of the filler layer in the array region in one step while reducing the etching of the filler layer in the peripheral region, which helps to reduce process complexity. Attached Figure Description

[0018] One or more embodiments are illustrated by way of example with corresponding pictures in the accompanying drawings. These illustrations do not constitute a limitation on the embodiments. Unless otherwise stated, the pictures in the accompanying drawings do not constitute a limitation on scale. In order to more clearly illustrate the technical solutions in the embodiments of this disclosure or the conventional technology, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0019] Figures 1 to 8 This is a schematic diagram of the steps of a semiconductor structure provided in an embodiment of the present disclosure;

[0020] Figures 9 to 15 This is a schematic diagram of the steps corresponding to another semiconductor structure provided in another embodiment of the present disclosure. Detailed Implementation

[0021] As can be seen from the background technology, the etching process in semiconductor structure fabrication still needs improvement.

[0022] One embodiment of this disclosure provides a method for manufacturing a semiconductor structure. First, in a first etching process, under a first bias power condition, a filler layer above the top surface of a first mask layer in an array region is removed to expose the top surface of the first mask layer in the array region. The first bias power is relatively high, which helps to increase the energy of the plasma used for etching, thereby accelerating the vertical physical bombardment of the filler layer by the plasma. This shortens the time of the first etching process, thus reducing the time of chemical etching in the first etching process and reducing the possibility of the filler layer in the peripheral region adjacent to the array region being etched during the first etching process. Then, in a second etching process, under a second bias power condition that is lower than the first bias power, the remaining filler layer in the array region is removed. This results in a relatively lower energy plasma used for etching in the second etching process, slowing down the vertical physical bombardment of the plasma and reducing the possibility of the exposed first mask layer being bombarded by plasma, which helps to improve the yield of the formed semiconductor structure.

[0023] Furthermore, another embodiment of the present disclosure provides a method for manufacturing a semiconductor structure, which uses a preset source power to remove the filling layer in the array region. The preset source power is 300W to 1000W. Within this power range, the source power is relatively small, resulting in a lower concentration of plasma generated during the removal of the filling layer in the array region. This reduces the chemical etching rate and the influence of the isotropic nature of chemical etching on the etching morphology of the filling layer. Consequently, it reduces the etching rate of the filling layer adjacent to the array region in the peripheral region during the removal of the filling layer above the top surface of the first mask layer in the array region. This is beneficial for obtaining a semiconductor structure with the desired morphology and can improve the performance and yield of the formed semiconductor structure. In addition, it can perform one-step etching of the filling layer in the array region while reducing the possibility of erosion of the filling layer in the peripheral region, which helps to reduce the process complexity.

[0024] The embodiments of this disclosure will now be described in detail with reference to the accompanying drawings. However, those skilled in the art will understand that many technical details have been provided in the embodiments of this disclosure to facilitate a better understanding of the disclosure. However, the technical solutions claimed in this disclosure can be implemented even without these technical details and various variations and modifications based on the following embodiments.

[0025] Figures 1 to 8 This is a schematic diagram of the steps of a semiconductor structure provided in an embodiment of the present disclosure.

[0026] refer to Figure 1A substrate 100 is provided, which spans the adjacent array region 10 and the peripheral region 20.

[0027] The substrate 100 can be made of elemental semiconductor materials or compound semiconductor materials. Elemental semiconductor materials can be germanium, silicon, selenium, boron, tellurium, or antimony; compound semiconductor materials can be gallium arsenide, indium phosphide, indium antimonide, silicon carbide, cadmium sulfide, or gallium arsenide silicon, etc.

[0028] The semiconductor structure to be formed can be a memory. The semiconductor structure to be formed includes an array region 11 and a peripheral region 12. The array region 11 is the core area of ​​the memory, used to store data; the peripheral region 12 is the control area of ​​the memory, used to control the writing and reading of data in the array region 11.

[0029] refer to Figure 2 A first mask layer 101 is formed on the substrate 100 of the array region 10 and the peripheral region 20. The first mask layer 101 located in the array region 10 has a plurality of openings 102 that penetrate the first mask layer 101.

[0030] The material of the first mask layer 101 can be polysilicon, silicon oxide, silicon nitride, or silicon oxynitride. The process for forming the first mask layer 101 can include chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), or a combination thereof. The process for forming the openings 102 can be photolithography. The multiple openings 102 are arranged at equal intervals in the first mask layer 101, or the spacing between different openings and adjacent openings 102 can be set differently. The spacing between adjacent openings 102 can be set according to actual conditions, and this embodiment does not limit the spacing of the multiple openings 102.

[0031] In some embodiments, an opening 102 is also provided in the first mask layer 101 adjacent to the array region in the peripheral region 20, so as to ensure that the opening 102 formed in the array region 10 after exposure, development and other steps is relatively consistent in size, so that the opening 102 that may be inconsistent with the size of the array region 10 due to machine limitations or other reasons is located in the peripheral region 20, and the opening 102 with inconsistent size is avoided from affecting the normal operation of subsequent processes of the array region 10.

[0032] Before forming the first mask layer 101, a sacrificial layer (not shown) may be formed on the substrate 100. The sacrificial layer protects the substrate 100 from erosion during the formation of the opening 102 of the first mask layer 101. The material of the sacrificial layer may be silicon oxide, silicon nitride, silicon oxynitride, or silicon carbide.

[0033] refer to Figure 3A filling layer 103 is formed, which covers the top surface of the first mask layer 101 and fills the opening 102.

[0034] The filler layer 103 can be made of SOC (Spin-on Carbon) or SOH (Spin-on Hard).

[0035] In some embodiments, the peripheral region 20 further has an opening 102 in the first mask layer 101 adjacent to the array region 10, and the filling layer 103 further fills the opening 102 in the peripheral region 20.

[0036] refer to Figure 4 A second mask layer 104 is formed, which is located on the filling layer 103 of the peripheral region 20. The second mask layer 104 is used to protect the filling layer 103 in the peripheral region 20 in subsequent steps and reduce the possibility of the filling layer 103 in the peripheral region 20 being etched.

[0037] In some embodiments, the second mask layer 104 may be a single film layer. For example, the material of the second mask layer 104 may be photoresist, silicon oxide, silicon nitride, or silicon oxynitride. In some embodiments, the second mask layer 104 may also be a stacked structure composed of multiple film layers. For example, the second mask layer 104 may include a bottom anti-reflective coating (BARC) and a photoresist layer. The bottom anti-reflective coating is located between the photoresist layer and the filler layer 103, and is used to absorb photoreflective materials during the photolithography process to form the photoresist layer, thereby protecting the filler layer 103 and the first mask layer 101 below the bottom anti-reflective coating.

[0038] The step of forming the second mask layer 104 may include: forming an initial second mask layer covering the entire first mask layer 101; removing the initial second mask layer in the array region 10, with the remaining initial second mask layer located in the peripheral region 20 constituting the second mask layer 104. In the step of removing the initial second mask layer in the array region 10, an etching endpoint detection system may be used to monitor the element content in the initial second mask layer to control the etching stop time and reduce the possibility of over-etching.

[0039] refer to Figure 5 Using a first etching process, under a first bias power condition, the filling layer 103 in the array region 10 that is higher than the top surface of the first mask layer 101 is removed.

[0040] The first etching process can be a plasma etching process. The plasma etching process can include physical etching and chemical etching of the filling layer 103 by plasma. Physical etching exhibits stronger anisotropy than isotropy, while chemical etching exhibits stronger isotropy than anisotropy. In the first etching process step, chemical etching can erode the filling layer 103 adjacent to the array region 10 in the peripheral region 20, causing the filling layer 103 in the peripheral region 20 to be partially exposed. This may result in the exposure of part of the first mask layer 101 in the peripheral region 20, affecting the normal progress of subsequent processes for etching the substrate 100 based on the first mask layer 101.

[0041] In the first etching process, the etching gas is ionized in the reaction chamber to generate a high-density plasma containing active free radicals, metastable particles, and atoms. A bias power is applied to the reaction chamber to generate a radio frequency electric field, causing the plasma generated in the etching process to perform directional physical sputtering bombardment of the filler layer 103 under the influence of the bias power, thereby etching the filler layer 103. The bias power can be provided by either an AC voltage source or a DC voltage source.

[0042] A larger first bias power can be set to increase the energy of the plasma used in the first etching process, thereby accelerating the vertical physical bombardment of the filling layer 103 by the plasma, shortening the time of the first etching process, thus shortening the chemical etching time in the first etching process, and reducing the possibility of the filling layer 103 in the peripheral region 20 being side-cut. In some embodiments, the first bias power can be 100W to 300W, for example, the first bias power can be 100W, 175W, 246W, 269W, 285W or 300W. Within this range, the first bias power is relatively large, which can provide higher energy for the plasma generated by the etching process, accelerate the plasma to physically etch the filling layer 103 vertically, shorten the time of the first etching process, thereby reducing the time of chemical etching, thereby reducing the possibility of the filling layer 103 of the adjacent array region 10 in the peripheral region 20 being side-exposed, thereby avoiding the exposure of part of the first mask layer 101 in the peripheral region 20, so as to protect the substrate 100 in the peripheral region 20 from being etched in the subsequent etching step of the substrate 100 in the array region 10, which is beneficial to improving the performance and yield of the formed semiconductor structure.

[0043] The etching gas can be selected from gases with relatively high etching selectivity for the filler layer 103 and the first mask layer 101, so as to reduce the possibility of the top surface of the first mask layer 101 being eroded after it is exposed in the first etching process. For example, the material of the first mask layer 101 can be polycrystalline silicon; the etching gas used in the first etching process can be oxygen. In some embodiments, the first etching process also provides a protective gas, which can protect the top surface of the first mask layer 101 exposed by etching and is beneficial to improving the verticality and uniformity of etching, thereby improving the contour morphology formed by etching. In some embodiments, the protective gas can be at least one of carbon sulfide, hydrogen, nitrogen, argon or helium.

[0044] The flow rate ratio of oxygen to protective gas can be in the range of 1.2 to 3, for example, the flow rate ratio can be 1.2, 1.7, 2.3, 2.8 or 3. Within this range, it can ensure that the effective etching gas oxygen concentration is relatively high, and that the protective gas can provide good protection for the first mask layer 101.

[0045] In some embodiments, the source power can be adjusted to a first source power, which ionizes the etching gas through inductive coupling to generate a high-density plasma containing active free radicals, metastable particles, and atoms. The first source power is typically provided by an AC voltage source and can range from 300W to 1000W. For example, the first source power can be 300W, 450W, 630W, 760W, 890W, 940W, or 1000W. Within this range, the first source power is relatively low, resulting in a lower plasma concentration in the reaction chamber, thus reducing the chemical etching rate. Physical etching is primarily used to etch the filling layer 103 on the top surface of the first mask layer 101 in the array region 20. This reduces the likelihood of the filling layer 103 in the peripheral region 20 being side-cut due to the isotropic nature of chemical etching, thereby improving the performance and yield of the formed semiconductor structure.

[0046] In some embodiments, an etching endpoint detection system is also used to monitor the etching status of the filler layer 103 on the top surface of the first mask layer 101. For example, the filler layer 103 contains carbon elements, and the material of the filler layer 103 can be a SOC material. By monitoring the concentration of carbon elements on the top surface of the first mask layer 101 through the etching endpoint detection system, it can be determined whether etching can be stopped, so as to precisely control the time of the first etching process.

[0047] refer to Figure 6 The second etching process is used to remove the remaining filling layer 103 in the array region 10 under the second bias power condition; wherein the first bias power can be greater than the second bias power.

[0048] The second etching process can be a plasma etching process. It is understandable that, since the top surface of the first mask layer 101 in the array region 10 is exposed in the first etching process, the plasma generated in the second etching process may still bombard the top surface of the first mask layer 101, which is detrimental to subsequent process steps. By setting the second bias power to be lower than the first bias power, the filling layer 103 is etched mainly by chemical etching to reduce the energy supplied to the plasma and thus mitigate the erosion of the first mask layer 101 by the plasma.

[0049] In some embodiments, the first bias power can be 3.5-10 times the second bias power. For example, the first bias power can be 3.5, 5.2, 6.7, 8.5, or 10 times the second bias power to control the time of the first and second etching processes. This avoids the first bias power being too high, resulting in a short first etching process time that is difficult to control precisely, and also avoids the second etching power being too low, resulting in a long second etching process time that affects efficiency. In some embodiments, the second bias power can be 30W to 80W. For example, the second source power can be 30W, 43W, 56W, 64W, 78W, or 80W. Within this range, a lower second bias power is beneficial for reducing the energy supplied to the plasma, thereby reducing the physical bombardment of the plasma on the first mask layer 101, reducing the erosion of the first mask layer 101, and primarily utilizing chemical etching to etch the filling layer 103.

[0050] The etching gas used in the second etching process can be selected from gases with high selectivity for etching the filler layer 103 and the first mask layer 101. For example, the etching gas used in the second etching process can be oxygen. A protective gas is also provided in the second etching process. The protective gas can protect the first mask layer 101 and improve the verticality and uniformity of the etching, thereby improving the contour morphology formed by the etching. The material of the protective gas can be at least one of carbon sulfide, hydrogen, nitrogen, argon, or helium.

[0051] In some embodiments, the flow rate ratio of oxygen to protective gas can be in the range of 1-2.5, for example, the flow rate ratio can be 1, 1.3, 1.7, 2.1 or 2.5. Within this flow rate range, it can be ensured that the effective etching gas oxygen concentration is relatively high, and that the protective gas can provide good protection for the first mask layer 101.

[0052] In some embodiments, the second etching process has a preset etching time, and the ratio of the actual etching time of the second etching process to the preset etching time is 1.2 to 1.5. For example, the ratio can be 1.2, 1.24, 1.36, 1.45 or 1.5. Within this ratio range, it can be ensured that the filling layer 103 in the array region 10 is completely removed, and the etching time is too long, so that the first mask layer 101 is eroded.

[0053] In some embodiments, an etching endpoint detection system is also used to monitor the etching status of the filling layer 103 in the opening 102. For example, the filling layer 103 contains carbon elements, and the material of the filling layer 103 can be a SOC material. By monitoring the concentration of carbon elements in the array region 10 through the etching endpoint detection system, it can be determined whether etching can be stopped, so as to precisely control the time of the first etching process.

[0054] In some embodiments, the source power can also be adjusted to a second source power in the second etching process. It is understood that since the etching of the first mask layer 102 is primarily physical etching, in the second etching process, the second source power can be set to be greater than the first source power to increase the plasma concentration, accelerate chemical etching, and shorten the time of the second etching process, thereby reducing the time of physical etching and lowering the likelihood of the first mask layer 101 being eroded. In some embodiments, the second source power can also be equal to the first source power.

[0055] The power of the second source can be between 300W and 1000W. For example, the power of the first source can be 300W and the power of the second source can be 500W; or, for another example, the power of the first source can be 420W and the power of the second source can be 630W.

[0056] refer to Figures 7 to 8 After removing the filling layer 103 in the array region 10, the process may further include: removing the second mask layer 104; using the first mask layer 101 and the filling layer 103 of the peripheral region 20 as a mask, etching to remove a portion of the substrate 100 of the array region; and removing the first mask layer and the filling layer 103.

[0057] The semiconductor structure manufacturing method provided in the above embodiments uses a larger first bias power to remove the filling layer 103 above the top surface of the first mask layer 101 in the array region 10, thereby increasing the energy of the plasma used in the first etching process, thus accelerating the vertical physical bombardment of the filling layer 103 by the plasma, shortening the time of the first etching process, thereby shortening the time of chemical etching in the first etching process, reducing the possibility of the filling layer 103 in the peripheral region 20 being side-cut, thereby reducing the possibility of the substrate 100 in the peripheral region 20 being etched in the subsequent etching step of the substrate 100 in the array region 10; and uses a second bias power that is smaller than the first bias power to remove the remaining filling layer 103 in the array region 10, so that the energy of the plasma used in the second etching process is relatively low, thereby slowing down the vertical physical bombardment of the plasma, reducing the possibility of the exposed first mask layer being bombarded by plasma, which is beneficial to improving the yield of the formed semiconductor structure.

[0058] Accordingly, another embodiment of this disclosure also provides a method for manufacturing another semiconductor structure. The method for manufacturing a semiconductor structure according to another embodiment of this disclosure will be described in detail below with reference to the accompanying drawings. For parts that are the same as or corresponding to the previous embodiment, please refer to the corresponding descriptions of the foregoing embodiments; detailed descriptions will not be repeated below. Figures 9 to 15 This is a schematic diagram of the structure corresponding to each step of a method for manufacturing another semiconductor structure according to another embodiment of this disclosure.

[0059] refer to Figure 9 A substrate 100 is provided, which spans the adjacent array region 10 and the peripheral region 20.

[0060] The substrate 100 can be made of elemental semiconductor materials or compound semiconductor materials. Elemental semiconductor materials can be germanium, silicon, selenium, boron, tellurium, or antimony; compound semiconductor materials can be gallium arsenide, indium phosphide, indium antimonide, silicon carbide, cadmium sulfide, or gallium arsenide silicon, etc.

[0061] The semiconductor structure to be formed can be a memory. The semiconductor structure to be formed includes an array region 11 and a peripheral region 12. The array region 11 is the core area of ​​the memory, used to store data; the peripheral region 12 is the control area of ​​the memory, used to control the writing and reading of data in the array region 11.

[0062] refer to Figure 10 A first mask layer 101 is formed on the substrate 100 of the array region 10 and the peripheral region 20. The first mask layer 101 located in the array region 10 has a plurality of openings 102 that penetrate the first mask layer 101.

[0063] The material of the first mask layer 101 can be polysilicon, silicon oxide, silicon nitride, or silicon oxynitride. The process for forming the first mask layer 101 can include chemical deposition, plasma-enhanced chemical vapor deposition, atomic layer deposition, or a combination thereof. The process for forming the opening 102 can be photolithography.

[0064] In some embodiments, an opening 102 is also provided in the first mask layer 101 adjacent to the array region in the peripheral region 20, so as to ensure that the opening 102 formed in the array region 10 after exposure, development and other steps is relatively consistent in size, so that the opening 102 that may be inconsistent with the size of the array region 10 due to machine limitations or other reasons is located in the peripheral region 20, and the opening 102 with inconsistent size is avoided from affecting the normal operation of subsequent processes of the array region 10.

[0065] Before forming the first mask layer 101, a sacrificial layer (not shown) may be formed on the substrate 100. The sacrificial layer protects the substrate 100 from erosion during the formation of the opening 102 of the first mask layer 101. The material of the sacrificial layer may be silicon oxide, silicon nitride, silicon oxynitride, or silicon carbide.

[0066] refer to Figure 11 A filling layer 103 is formed, which covers the top surface of the first mask layer 101 and fills the opening 102.

[0067] The filler layer 103 can be made of SOC material or SOH material.

[0068] In some embodiments, the peripheral region 20 further has an opening 102 in the first mask layer 101 adjacent to the array region 10, and the filling layer 103 further fills the opening 102 in the peripheral region 20.

[0069] refer to Figure 12 A second mask layer 104 is formed, which is located on the filling layer 103 of the peripheral region 20. The second mask layer 104 is used to protect the filling layer 103 in the peripheral region 20 in subsequent steps and reduce the possibility of the filling layer 103 in the peripheral region 20 being etched.

[0070] In some embodiments, the second mask layer 104 may be a single layer. For example, the material of the second mask layer 104 may be photoresist, silicon oxide, silicon nitride, or silicon oxynitride. In some embodiments, the second mask layer 104 may also be a stacked structure composed of multiple layers. For example, the second mask layer 104 may include a bottom anti-reflective coating and a photoresist layer, wherein the bottom anti-reflective coating is located between the photoresist layer and the filler layer 103, and is used to absorb photoreflective materials during the photolithography process to form the photoresist layer, thereby protecting the filler layer 103 and the first mask layer 101 below the bottom anti-reflective coating.

[0071] The step of forming the second mask layer 104 may include: forming an initial second mask layer covering the entire first mask layer 101; removing the initial second mask layer in the array region 10, with the remaining initial second mask layer located in the peripheral region 20 constituting the second mask layer 104. In the step of removing the initial second mask layer in the array region 10, an etching endpoint detection system may be used to monitor the element content in the initial second mask layer to control the etching stop time and reduce the possibility of over-etching.

[0072] refer to Figure 13 Under a preset source power condition, the fill layer 103 in the array region 10 is removed; wherein, the preset source power can be 300W to 1000W. For example, the preset source power can be 300W, 370W, 550W, 660W, 780W, 920W or 1000W.

[0073] The process for removing the filling layer 103 in the array region 10 can be plasma etching. Plasma etching can include physical etching and chemical etching of the filling layer 103 by plasma. Physical etching exhibits stronger anisotropy than isotropy, while chemical etching exhibits stronger isotropy than anisotropy. The process of removing the filling layer 103 in the array region 10 includes: removing the filling layer 103 on the top surface of the first mask layer 101 in the array region 10 under a preset source power condition. During this process, chemical etching may erode the filling layer 103 adjacent to the array region 10 in the peripheral region 20, causing the filling layer 103 in the peripheral region 20 to be side-penetrated. This may expose part of the first mask layer 101 in the peripheral region 20, affecting the normal progress of subsequent processes for etching the substrate 100 based on the first mask layer 101. By setting the preset source power within the range of 300W to 1000W, the preset source power is relatively low, resulting in a lower plasma concentration generated in the reaction chamber, thereby reducing the chemical etching rate and weakening the isotropic nature of the chemical etching. Furthermore, the first mask layer 101 also protects the top surface of the filling layer in the peripheral region 20 from erosion, thereby reducing the possibility of the filling layer 103 in the peripheral region 20 being side-cut, which is beneficial to improving the performance and yield of the formed semiconductor structure.

[0074] Because the preset source power is relatively low, in some embodiments, the fill layer 103 in the array region 10 can be removed under conditions of no bias power.

[0075] The etching gas can be selected from gases with relatively high etching selectivity for the filler layer 103 and the first mask layer 101, thereby reducing the possibility of the first mask layer 101 being eroded. For example, the material of the first mask layer 101 can be polycrystalline silicon; the etching gas used in the first etching process can be oxygen. In some embodiments, the first etching process also provides a protective gas, which can protect the top surface of the first mask layer 101 exposed by etching and is beneficial to improving the verticality and uniformity of etching, thereby improving the contour morphology formed by etching. In some embodiments, the protective gas can be at least one of carbon sulfide, hydrogen, nitrogen, argon, or helium.

[0076] The flow rate ratio of oxygen to protective gas can be in the range of 1 to 3, for example, the flow rate ratio can be 1, 1.7, 2.3, 2.8 or 3. Within this range, it can be ensured that the effective etching gas oxygen concentration is relatively high, and that the protective gas can provide good protection for the first mask layer 101.

[0077] In some embodiments, the step of removing the filling layer 103 of the array region 10 has a preset etching time. The ratio of the actual etching time of the step of removing the filling layer of the array region to the preset etching time can be 1.2 to 2. For example, the ratio can be 1.2, 1.24, 1.36, 1.65 or 2. Within this ratio range, it can be ensured that the filling layer 103 in the array region 10 is completely removed, and the etching time is avoided from being too long and causing the first mask layer 101 to be eroded.

[0078] In some embodiments, an etching endpoint detection system is also used to monitor the etching status of the filler layer 103 in the array region 10. For example, the filler layer 103 contains carbon elements, and the material of the filler layer 103 can be a SOC material. In the step of removing the filler layer 103 in the array region 10, the concentration of carbon elements on the top surface of the first mask layer 101 of the array region 10 and in the opening 102 of the array region 10 is monitored by the etching endpoint detection system to determine whether etching can be stopped, so as to precisely control the time of the first etching process.

[0079] Because the preset source power is relatively low, the filling layer in the array region 10 can be removed in one step when the possibility of the filling layer 103 in the peripheral region 20 being side-punched is low. In some embodiments, the filling layer 103 in the array region 10 can be removed in two steps. The step of removing the filling layer in the array region may include: using a third etching process to remove the filling layer in the array region above the top surface of the first mask layer under a first source power condition; and using a fourth etching process to remove the remaining filling layer in the array region under a second source power condition. The first source power is set to be less than or equal to the second source power so that the plasma concentration in the third etching process is relatively low, thereby reducing the chemical etching rate of the third etching process and reducing the possibility of the filling layer 103 in the peripheral region 20 being etched in the third etching process. Since the etching that erodes the first mask layer 103 is mainly physical etching, the second source power is set to be relatively high to increase the plasma concentration, thereby accelerating the chemical etching rate in the fourth etching process, balancing the time of the third etching process, shortening the time to remove the filling layer 103 in the array region 10, and avoiding the possibility of the first mask layer 103 and the filling layer 103 in the peripheral region 20 being eroded due to excessive etching time.

[0080] The power of the first source can be in the range of 300W to 1000W, and the power of the second source can also be in the range of 300W to 1000W. For example, the power of the first source can be 350W and the power of the second source can be 500W; or, for another example, the power of the first source can be 400W and the power of the second source can be 700W.

[0081] refer to Figures 14 to 15 After removing the filling layer 103 in the array region 10, the process may further include: removing the second mask layer 104; using the first mask layer 101 and the filling layer 103 of the peripheral region 20 as a mask, etching to remove a portion of the substrate 100 of the array region; and removing the first mask layer and the filling layer 103.

[0082] The semiconductor structure manufacturing method disclosed in the above embodiments provides a preset source power for removing the filling layer 103 in the array region 10. The preset source power is 300W to 1000W. Within this power range, the source power is relatively small, resulting in a lower concentration of plasma generated during the removal of the filling layer in the array region. This reduces the chemical etching rate and the influence of the isotropic nature of chemical etching on the etching morphology of the filling layer. Consequently, it reduces the etching rate of the filling layer 103 adjacent to the array region 10 in the peripheral region 20 during the removal of the filling layer 103 above the top surface of the first mask layer 101 in the array region 10. This is beneficial for obtaining a semiconductor structure with the desired morphology and can improve the performance and yield of the formed semiconductor structure. Furthermore, since the preset source power is relatively small, it is possible to perform one-step etching of the filling layer in the array region while reducing the possibility of erosion of the filling layer in the peripheral region, which helps to reduce the process complexity.

[0083] Those skilled in the art will understand that the above embodiments are specific examples of implementing this disclosure, and in practical applications, various changes in form and detail may be made without departing from the spirit and scope of this disclosure. Any person skilled in the art can make various alterations and modifications without departing from the spirit and scope of this disclosure; therefore, the scope of protection of this disclosure should be determined by the scope defined in the claims.

Claims

1. A method for manufacturing a semiconductor structure, characterized in that, include: A substrate is provided that spans an adjacent array region and a peripheral region; A first mask layer is formed on the substrate of the array region and the peripheral region, wherein the first mask layer located in the array region has a plurality of openings that penetrate the first mask layer; A filling layer is formed, which covers the top surface of the first mask layer and fills the opening; A second mask layer is formed, which is located on the fill layer of the peripheral region; Using a first etching process, under a first bias power condition, the filling layer above the top surface of the first mask layer in the array region is removed; A second etching process is used to remove the remaining filler layer in the array region under a second bias power condition; wherein the first bias power is greater than the second bias power. The first bias power is 3.5-10 times the second bias power.

2. The method for manufacturing a semiconductor structure according to claim 1, characterized in that, The second etching process has a preset etching time, and the ratio of the actual etching time of the second etching process to the preset etching time is 1.2 to 1.

5.

3. The method for manufacturing a semiconductor structure according to claim 1, characterized in that, The material of the first mask layer includes polycrystalline silicon; the etching gas used in both the first etching process and the second etching process includes oxygen, wherein the oxygen flow rate in the first etching process is greater than or equal to the oxygen flow rate in the second etching process.

4. The method for manufacturing a semiconductor structure according to claim 1, characterized in that, In the first etching process, the source power is further adjusted to a first source power; in the second etching process, the source power is further adjusted to a second source power; wherein the first source power is less than or equal to the second source power.

5. A method for manufacturing a semiconductor structure, characterized in that, include: A substrate is provided that spans an adjacent array region and a peripheral region; A first mask layer is formed on the substrate of the array region and the peripheral region, wherein the first mask layer located in the array region has a plurality of openings that penetrate the first mask layer; A filling layer is formed, which covers the top surface of the first mask layer and fills the opening; A second mask layer is formed, which is located on the fill layer of the peripheral region; Under a preset source power condition, the filler layer in the array region is removed; wherein, the preset source power is 300W~1000W; The step of removing the fill layer in the array region includes: A third etching process is used to remove the filling layer above the top surface of the first mask layer in the array region under the first source power condition; The remaining filling layer in the array region is removed using a fourth etching process under a second source power condition; wherein the first source power is less than or equal to the second source power.

6. The method for manufacturing a semiconductor structure according to claim 5, characterized in that, Remove the fill layer in the array region under no bias power conditions.

7. The method for manufacturing a semiconductor structure according to claim 5, characterized in that, The step of removing the fill layer of the array region has a preset etching time, and the ratio of the actual etching time of the step of removing the fill layer of the array region to the preset etching time is 1.2~2.

8. The method for manufacturing a semiconductor structure according to claim 5, characterized in that, The filling layer contains carbon elements; in the step of removing the filling layer in the array region, an etching endpoint detection system is also used to monitor the carbon element concentration on the top surface of the first mask layer of the array region and in the opening of the array region.

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