A semiconductor chip
By employing a stacked structure of aluminum oxide passivation layer and other passivation layers in semiconductor chips, the problem of micro-cracks caused by etching processes is solved, improving chip reliability and production yield, and adapting to process compatibility with complex device structures.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2025-06-25
- Publication Date
- 2026-06-23
Smart Images
Figure CN224402112U_ABST
Abstract
Description
Technical Field
[0001] This utility model belongs to the technical field of semiconductors, and specifically relates to a semiconductor chip. Background Technology
[0002] In semiconductor chip manufacturing, passivation reliability directly impacts chip performance. Typically, after the device fabrication process, a metal interconnect layer needs to be constructed. Electroplating is preferred due to its low cost. The metal electroplating process first uses processes such as sputtering to form a conductive layer across the entire surface. Then, an electroplated layer is formed on a specific area of the conductive layer. After electroplating, excess conductive layer needs to be etched away to disconnect the interconnects between the electroplated metals. Next, a passivation layer is deposited on the chip surface to protect the device and isolate it from moisture. The passivation effect of this layer is crucial for the chip's high-temperature and humidity resistance and its reliability testing tolerance.
[0003] Existing etching processes result in the conductive layer penetrating deep beneath the electroplated layer, creating a concave morphology at the bottom of the electroplated metal. This morphology can form microcracks during the subsequent deposition of the passivation layer. These microcracks become channels for the penetration of corrosive environmental media (water vapor / ions), which is one of the reasons for product failure in subsequent reliability tests, affecting the product's production yield and performance. Utility Model Content
[0004] This invention addresses the shortcomings of existing technologies by providing a semiconductor chip.
[0005] To achieve the above objectives, the technical solution of this utility model is as follows:
[0006] A semiconductor chip includes a device structure, an insulating layer, a metal interconnect layer, a first passivation layer, and an aluminum oxide passivation layer; the insulating layer is disposed on the device structure, and the metal interconnect layer is disposed on the insulating layer and electrically connected to the device structure; the bottom sidewall of the metal interconnect layer is recessed and forms a recessed region between it and the surface of the insulating layer; the first passivation layer is disposed on the metal interconnect layer and the insulating layer; the aluminum oxide passivation layer and the first passivation layer form a stacked structure, covering the metal interconnect layer and extending to cover the surface of the surrounding insulating layer.
[0007] Optionally, the indentation length of the recessed region is 0.1–0.6 μm, and the height is 40–100 nm.
[0008] Optionally, the alumina passivation layer extends 0.3 to 1 μm on the insulating layer surrounding the metal interconnect layer.
[0009] Optionally, in the stacked structure, the alumina passivation layer fills the recessed area, and the first passivation layer is disposed outside the alumina passivation layer.
[0010] Optionally, in the stacked structure, the first passivation layer fills the recessed area, and the alumina passivation layer is disposed outside the first passivation layer.
[0011] Optionally, it further includes a second passivation layer, which is disposed outside the alumina passivation layer and the first passivation layer, and the second passivation layer is silicon nitride, silicon oxide, or silicon oxynitride.
[0012] Optionally, the first passivation layer is silicon nitride, silicon oxide, or silicon oxynitride, with a thickness of 200–800 nm; the thickness of the aluminum oxide passivation layer is 20–50 nm.
[0013] Optionally, the metal interconnect layer sequentially includes an adhesion layer, a seed layer, and an electroplated metal layer, wherein the adhesion layer is a titanium-tungsten alloy, and the seed layer and the electroplated metal layer are gold, and at least the edge of the adhesion layer is recessed relative to the edge of the electroplated metal layer to form the recessed area.
[0014] Optionally, the device structure has electrodes, and the metal interconnect layer is electrically connected to the electrodes through conductive vias penetrating the insulating layer.
[0015] Optionally, the device structure includes an HBT device or a pHEMT device, and the insulating layer is a polymer insulating material.
[0016] The beneficial effects of this utility model are as follows:
[0017] By employing a stacked structure of alumina passivation layer and other passivation layers, the high density and excellent step coverage of the alumina passivation layer, along with the high mechanical strength of the other passivation layers, form a synergistic protective barrier. This barrier can block the path of water vapor / ions to penetrate the metal interconnect through the micro-cracks in the passivation layer caused by the bottom depression area of the metal interconnect layer, thus solving the corrosion failure problem caused by morphological defects in traditional single-layer passivation. It has strong process compatibility, is suitable for conventional processes, and can be flexibly adapted to complex device structures, significantly improving the yield and stability of various types of chips.
[0018] Other features and beneficial effects of this invention will be set forth in the following description, and will be apparent in part from the description, or may be learned by practicing this invention. Attached Figure Description
[0019] Figure 1 This is a schematic diagram of the semiconductor chip structure in Example 1;
[0020] Figure 2 This is a schematic diagram of the semiconductor chip structure in Example 2;
[0021] Figure 3 This is a schematic diagram of the semiconductor chip structure in Example 3;
[0022] Figure 4 This is a schematic diagram of the structure of the semiconductor chip based on the pHEMT device in Example 4;
[0023] Figure 5 This is a schematic diagram of the structure of a semiconductor chip based on an HBT device in Example 4. Detailed Implementation
[0024] The present invention will be further explained below with reference to the accompanying drawings and specific embodiments. The accompanying drawings are merely illustrative to facilitate understanding of the present invention, and their specific proportions can be adjusted according to design requirements. The vertical relationships of relative elements and the definitions of front / back in the graphics described herein should be understood by those skilled in the art to refer to the relative positions of the components; therefore, they can all be flipped to present the same component, and all of this should fall within the scope disclosed in this specification.
[0025] Example 1
[0026] The semiconductor chip of Example 1, referenced Figure 1 The device includes a device structure 1, an insulating layer 2, a metal interconnect layer 3, a first passivation layer 4, and an aluminum oxide passivation layer 5. The device structure 1 includes a semiconductor substrate 11 and electrodes 12 disposed on the semiconductor substrate 11. For ease of explanation, the figure uses one electrode as an example. The insulating layer 2 is disposed on the device structure 1 to provide insulation and high fill effect. The metal interconnect layer 3 is disposed on the insulating layer 2 and electrically connected to the device structure 1. The bottom sidewall of the metal interconnect layer 3 is recessed and forms a recessed region 3a between it and the surface of the insulating layer 2. The first passivation layer 4 covers the surfaces of the metal interconnect layer 3 and the insulating layer 2 and fills the recessed region 3a. The aluminum oxide passivation layer 5 is disposed outside the first passivation layer 4, covering the metal interconnect layer 3 and extending to cover the surrounding surface of the insulating layer 2. The dense aluminum oxide passivation layer 5 fills the gaps in the first passivation layer 4 near the recessed region 3a and forms a stacked structure with the first passivation layer 4, preventing moisture from directly penetrating the metal through the passivation layer cracks, thereby improving product reliability.
[0027] The insulating layer 2 is a polymer insulating material, such as polyimide (PI); the metal interconnect layer 3 includes an adhesion layer 31, a seed layer and an electroplated metal layer in sequence. The adhesion layer 31 is a titanium-tungsten alloy (TiW) to improve the bonding force between the electroplated metal material and the insulating layer material. The seed layer and the electroplated metal layer are both gold (Au). A through-hole 2a is formed in the insulating layer 2 to expose the electrode 12. An adhesion layer 31 and a seed layer are sequentially deposited on the surface of the insulating layer 2 using processes such as sputtering to form a conductive layer. The adhesion layer 31 and the seed layer are simultaneously deposited on the inner wall of the through-hole 2a and contact the electrode 12. Then, an electroplated metal layer is formed in a predetermined area using an electroplating process. The electroplated metal layer fills the through-hole 2a to form a conductive through-hole and covers the surface of the insulating layer 2 surrounding the through-hole 2a. Afterwards, the conductive layer is etched using a conventional etching process. At least the edge of the adhesion layer 31 will be recessed relative to the edge of the electroplated metal layer, forming a recessed area. The figure shows the adhesion layer 31 forming a recessed area 3a as an example. In some processes, the bottom areas of the seed layer and the electroplated metal layer may also be over-etched due to thickness issues, expanding the recessed area. Ultimately, both result in a recessed morphology on the bottom sidewall of the metal interconnect layer 3. In this embodiment, refer to... Figure 1 The width L0 of the metal interconnect layer 3 is 4 to 5 μm, and the thickness H0 (i.e., the deposition thickness on the surface of the insulating layer) is 4 to 5 μm; the inward length L1 of the single-sided recessed region 3a is 0.1 to 0.3 μm, and the height H1 (i.e., the pore height between the recessed region and the surface of the insulating layer) is 40 to 100 nm, for example, H1 is 60 nm.
[0028] The first passivation layer 4 is made of silicon nitride, silicon oxide, or silicon oxynitride, and is deposited over the entire surface using, for example, MOCVD (metal-organic chemical vapor deposition), with a thickness of 200–800 nm; alternatively, silicon nitride (SiN) with a thickness of 600 nm can be used. The aluminum oxide passivation layer 5 is formed using ALD (atomic layer deposition) and has a thickness of 20–50 nm, for example, 25 nm. Excess aluminum oxide is then etched away. The etching window can be set at a distance of 0.3–1 μm from the edge of the first passivation layer 4 on the metal interconnect layer 3. The final extension length L2 of the remaining aluminum oxide passivation layer 5 on the insulating layer 2 surrounding the metal interconnect layer is correspondingly 0.3–1 μm, for example, approximately 0.5 μm. This ensures a dense stack of aluminum oxide near the stress concentration depression region 3a, improving reliability. Etching away excess aluminum oxide prevents abnormal interconnect short circuits between metal lines.
[0029] Example 2
[0030] The difference between Example 2 and Example 1 is that, referring to Figure 2It also includes a second passivation layer 6 disposed on the alumina passivation layer 5 and the first passivation layer 4. The material of the second passivation layer 6 is silicon nitride, silicon oxide, or silicon oxynitride, preferably the same as the material of the first passivation layer 4; for example, it can be silicon nitride (SiN) with a thickness of 200 nm. Alumina and silicon nitride have good adhesion, and the stacked structure formed by the re-deposition of silicon nitride can fill weak points and further improve reliability.
[0031] Example 3
[0032] The semiconductor chip of Example 3, referenced Figure 3 The device includes a device structure 1, an insulating layer 2, a metal interconnect layer 3, a first passivation layer 4, and an aluminum oxide passivation layer 5. The device structure 1 includes a semiconductor substrate 11 and electrodes 12 disposed on the semiconductor substrate 11. For ease of explanation, the figure uses one electrode as an example. The insulating layer 2 is disposed on the device structure 1 to provide insulation and high fill effect. The metal interconnect layer 3 is disposed on the insulating layer 2 and electrically connected to the device structure 1. The bottom sidewall of the metal interconnect layer 3 is recessed, forming a recessed region 3a between it and the surface of the insulating layer 2. The aluminum oxide passivation layer 5 covers the metal interconnect layer 3 and fills the recessed region 3a, extending to cover the surrounding surface of the insulating layer 2. The first passivation layer 4 is disposed outside the aluminum oxide passivation layer 5, completely covering the aluminum oxide passivation layer 5 and the exposed surface of the insulating layer 2. The aluminum oxide passivation layer 5 fills the recessed region 3a, preventing a concave morphology at the bottom of the metal interconnect layer 3, thus preventing microcracks after the deposition of the first passivation layer 4. The alumina passivation layer 5 and the first passivation layer 4 form a stacked structure, which prevents water vapor from directly penetrating the metal through the cracks in the passivation layer, thereby improving product reliability.
[0033] The insulating layer 2 is a polymer insulating material, such as polyimide (PI). The arrangement of the metal interconnect layer 3 and the electrode connection through the through-hole 2a are described in Example 1. In this example, [reference is provided]. Figure 3 The width L0 of the metal interconnect layer 3 is 4.5 to 5.5 μm, and the thickness H0 (i.e., the deposition thickness on the surface of the insulating layer) is 4 to 5 μm; the inward length L1 of the single-sided recessed region 3a is 0.2 to 0.6 μm, and the height H1 (i.e., the pore height between the recessed region and the surface of the insulating layer) is 40 to 100 nm, for example, H1 is 60 nm.
[0034] After electroplating the metal, a deposition window for alumina is defined using photoresist, with the edge of the deposition window 0.3–1 μm from the sidewall of the metal interconnect layer 3. A dense alumina layer with a thickness of 20–50 nm, for example, 30 nm, is grown using ALD (Atomic Layer Deposition). After stripping the photoresist, the alumina is visible covering the surface of the metal interconnect layer 3 and the insulating layer 2 near its bottom, filling the recessed region 3a. The final alumina passivation layer 5 extends 0.3–1 μm, for example, about 0.5 μm, on the insulating layer 2 surrounding the metal interconnect layer. Subsequently, a first passivation layer 4 is deposited over the entire surface using, for example, MOCVD (Metal-Organic Chemical Vapor Deposition). The material of the first passivation layer 4 is silicon nitride, silicon oxide, or silicon oxynitride, with a deposition thickness of 200–800 nm; for example, silicon nitride (SiN) with a thickness of 600 nm can be selected. Because the bottom of the metal interconnect layer 3 is filled, no gaps are generated along the morphology of the aluminum oxide passivation layer 5 during silicon nitride deposition, which can improve chip reliability under the current process.
[0035] Example 4
[0036] Examples 1-3 use the connection of a single electrode as an example. Based on different device structures, there are multiple metal electrodes and their external structures that are simultaneously fabricated on different functional layers of a semiconductor substrate. When fabricating the metal interconnect layer, the electrodes are set through the through-holes of the insulating layer, and the entire surface of the insulating layer is sputtered with an attachment layer and a seed layer. After the electroplated metal is fabricated, the connection between the attachment layer and the seed layer is etched to realize the metal interconnect layer for each electrode to be led out.
[0037] refer to Figure 4 Device structure 1A is a high electron mobility transistor (pHEMT) device. Its semiconductor layer may include a buffer layer, a channel layer, a resistive layer, a barrier layer (e.g., a Schottky barrier layer), an isolation layer, a capping layer, any suitable layer, or a combination thereof, but is not limited thereto. Device structure 1A has a source S, a drain D, and a gate G. The source S and drain D may respectively include Ti, Al, W, Au, Pd, Au, Ge, Ni, Mo, Pt, other suitable metals, alloys thereof, or combinations thereof. An ohmic contact may be formed between the source S and the semiconductor layer, and an ohmic contact may be formed between the electrode D and the semiconductor layer. Conventionally, the surface of device structure 1A will have other arrangements such as a passivation layer, but this is not limited. An insulating layer 2 covers device structure 1A. The arrangement of the metal interconnect layer 3, the first passivation layer 4, and the aluminum oxide passivation layer 5 is as described in Examples 1 to 3, with the structure of Example 1 being illustrated as an example. The metal interconnect layer 3 is electrically connected to the source electrode S and the drain electrode D through conductive vias. The first passivation layer 4 and the aluminum oxide passivation layer 5 form a stacked structure on and near the surface of each metal interconnect layer 3, which can improve the passivation reliability.
[0038] refer to Figure 5Device structure 1B is a heterojunction bipolar transistor (HBT) device. Its semiconductor layer may include a secondary collector layer, a collector layer, a base layer, an emitter layer, an emitter contact layer, any suitable layer, or a combination thereof. Device structure 1B has a collector contact metal 12a, a base contact metal 12b, and an emitter contact metal 12c. Conventionally, the surface of device structure 1B will have other features such as a passivation layer, which is not limited. An insulating layer 2 covers device structure 1B. The configuration of the metal interconnect layer 3, the first passivation layer 4, and the aluminum oxide passivation layer 5 is as described in Examples 1-3, with the structure of Example 3 shown as an example. The metal interconnect layer 3 is connected to the collector contact metal 12a, the base contact metal 12b, and the emitter contact metal 12c through conductive vias. The first passivation layer 4 and the aluminum oxide passivation layer 5 form a stacked structure on and near the surface of each metal interconnect layer 3, which can improve passivation reliability.
[0039] The above embodiments are only used to further illustrate a semiconductor chip of the present invention, but the present invention is not limited to the embodiments. Any simple modifications, equivalent changes and alterations made to the above embodiments based on the technical essence of the present invention shall fall within the protection scope of the technical solution of the present invention.
Claims
1. A semiconductor chip, characterized by: It includes a device structure, an insulating layer, a metal interconnect layer, a first passivation layer, and an aluminum oxide passivation layer; the insulating layer is disposed on the device structure, and the metal interconnect layer is disposed on the insulating layer and electrically connected to the device structure; the bottom sidewall of the metal interconnect layer is recessed and forms a recessed area between it and the surface of the insulating layer; The first passivation layer is disposed on the metal interconnect layer and the insulating layer; The alumina passivation layer and the first passivation layer form a stacked structure, covering the metal interconnect layer and extending to cover the surface of the surrounding insulating layer.
2. The semiconductor chip of claim 1, wherein: The indentation length of the recessed area is 0.1–0.6 μm, and the height is 40–100 nm.
3. The semiconductor chip of claim 1, wherein: The alumina passivation layer extends 0.3 to 1 μm in length on the insulating layer surrounding the metal interconnect layer.
4. The semiconductor chip of claim 1, wherein: In the stacked structure, the alumina passivation layer fills the recessed area, and the first passivation layer is disposed on the outside of the alumina passivation layer.
5. The semiconductor chip according to claim 1, characterized in that: In the stacked structure, the first passivation layer fills the recessed area, and the alumina passivation layer is disposed outside the first passivation layer.
6. The semiconductor chip according to claim 5, characterized in that: It also includes a second passivation layer, which is disposed outside the alumina passivation layer and the first passivation layer. The second passivation layer is silicon nitride, silicon oxide, or silicon oxynitride.
7. The semiconductor chip according to claim 1, characterized in that: The first passivation layer is silicon nitride, silicon oxide, or silicon oxynitride, with a thickness of 200–800 nm; the thickness of the aluminum oxide passivation layer is 20–50 nm.
8. The semiconductor chip according to claim 1, characterized in that: The metal interconnect layer sequentially includes an adhesion layer, a seed layer, and an electroplated metal layer. The adhesion layer is a titanium-tungsten alloy, and the seed layer and the electroplated metal layer are gold. At least the edge of the adhesion layer is recessed relative to the edge of the electroplated metal layer to form the recessed area.
9. The semiconductor chip according to claim 1, characterized in that: The device structure has electrodes, and the metal interconnect layer is electrically connected to the electrodes through conductive vias penetrating the insulating layer.
10. The semiconductor chip according to claim 1, characterized in that: The device structure includes an HBT device or a pHEMT device, and the insulating layer is a polymer insulating material.