A chip package structure of a photodiode stack connection
By using a photodiode stacked connection structure and a conductive copper layer heat dissipation design, combined with a focusing lens and encapsulating colloid, the problem of insufficient light utilization in photodiode packaging is solved, achieving efficient photoelectric conversion and improved heat dissipation.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- HEYUAN FUYU OPTOELECTRONICS TECH CO LTD
- Filing Date
- 2025-08-28
- Publication Date
- 2026-06-26
AI Technical Summary
In existing photodiode packaging structures, the planar arrangement of multiple chips results in different incident angles of light, and some light cannot be effectively utilized, affecting photoelectric conversion efficiency.
A photodiode stacked connection structure is adopted, the first chip and the second chip are connected by conductive adhesive, and a conductive copper layer with an arc groove is set at the corner of the substrate to improve the heat dissipation effect. A condenser lens is used to focus the light onto the chip surface, and thermally conductive encapsulant is filled between the package shell and the substrate.
It improves light utilization and photoelectric conversion efficiency, enhances heat dissipation and packaging stability, has a compact overall structure, and improves the performance of photodiodes.
Smart Images
Figure CN224419202U_ABST
Abstract
Description
Technical Field
[0001] This utility model relates to the field of chip packaging structure, and more particularly to a chip packaging structure with photodiode stacked connection. Background Technology
[0002] A photodiode is a semiconductor device that converts light signals into electrical signals. It is widely used in photoelectric detection, imaging systems, and optical communication. A photodiode generates current by irradiation with light, and its performance is affected by photoelectric conversion efficiency, response speed, and packaging structure.
[0003] In the existing technology, the traditional photodiode packaging structure generally adopts single-layer chip packaging or multiple chips are arranged in a plane on a substrate. However, the method of directly arranging multiple chips in a plane results in each chip receiving light at a different incident angle. Some light cannot pass through the condenser lens to illuminate the photosensitive area of the chip, resulting in insufficient light utilization and thus affecting the photoelectric conversion efficiency of the photodiode.
[0004] Therefore, existing technologies have shortcomings and need to be improved. Utility Model Content
[0005] The technical problem to be solved by this utility model is to provide a chip packaging structure with a compact structure and effective improvement in photodiode stacking efficiency.
[0006] The technical solution of this utility model is as follows: a chip packaging structure for stacked photodiodes, including a substrate, a first chip, a second chip, a packaging shell, a focusing lens, a conductive copper layer, and surface mount pins;
[0007] The substrate has a conductive pad in the middle, the first chip is disposed on the conductive pad, the second chip is stacked on the surface of the first chip, and the second chip and the first chip are connected by conductive adhesive. The surface area of the first chip is larger than the surface area of the second chip.
[0008] The substrate has arc-shaped grooves at its four corners. The conductive copper layer has an arc-shaped section and a flat section. The arc-shaped section is located on the wall of the arc-shaped groove, and the flat section is located on the top surface of the substrate. The top of the arc-shaped section is connected to the conductive pad through the flat section.
[0009] The surface mount pin is located at the bottom of the substrate, and the bottom of the arc segment is connected to the surface mount pin. The surface mount pin is used for electrical connection with external circuitry.
[0010] The encapsulation housing is disposed on the top of the substrate, the encapsulation housing is used to cover the first chip and the second chip, and the encapsulation colloid is filled between the encapsulation housing and the substrate;
[0011] The focusing lens is disposed on the top surface of the package housing, and the focusing lens is used to focus external light onto the first chip and the second chip.
[0012] Using the above technical solution, in the chip packaging structure of the photodiode stacked connection, the surface mount pins include a first pin, a second pin, and a third pin;
[0013] The first pin and the second pin are respectively located on one side of the bottom of the substrate, and the first pin and the second pin are respectively connected to the bottom of the arc end of the conductive copper layer;
[0014] The third pin is located on the other side of the bottom of the substrate, and the two ends of the third pin are respectively connected to the bottom of the arc end of the conductive copper layer.
[0015] In the above technical solution, the condensing lens in the chip packaging structure with stacked photodiodes is a Fresnel lens.
[0016] Using the above technical solution, in the chip packaging structure with stacked photodiodes, the corners of the packaging shell are respectively provided with transition arc structures.
[0017] In the above technical solution, the chip packaging structure with stacked photodiodes is made of polycarbonate.
[0018] In the above technical solution, in the chip packaging structure with stacked photodiodes, the substrate and the packaging shell are fixedly connected by a hot melt adhesive layer.
[0019] In the above technical solution, the encapsulating colloid in the chip packaging structure of the photodiode stacked connection is silicone or epoxy resin.
[0020] In the above technical solution, the substrate in the chip packaging structure with stacked photodiodes is made of BT flexible resin glass fiber board.
[0021] Compared with the prior art, the present invention has the following beneficial effects:
[0022] This invention, by stacking the first and second chips, avoids the second chip blocking the photosensitive area of the first chip, thereby improving the utilization rate of incident light. The conductive copper layer, while providing electrical connection, also features an arc-shaped groove at the corner of the substrate, allowing the arc-shaped section of the conductive copper layer to tightly adhere to the substrate surface along the groove wall. This conducts heat generated by the first chip to the outside of the substrate, improving heat dissipation. The encapsulating colloid fills the space between the encapsulation shell and the substrate, enhancing sealing while also providing thermal conductivity, thus improving heat dissipation and encapsulation durability. A focusing lens located on the top surface of the encapsulation shell focuses external light onto the surfaces of the first and second chips, preventing light loss and improving photoelectric conversion efficiency. The overall structure is compact, effectively improving the performance, heat dissipation, and encapsulation stability of the photodiode. Attached Figure Description
[0023] To more clearly illustrate the technical solutions in the embodiments of this utility model or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this utility model. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0024] The structures, proportions, sizes, etc., shown in the accompanying drawings of this specification are only for the purpose of assisting those skilled in the art in understanding and reading the content disclosed in the specification, and are not intended to limit the implementation conditions of this utility model. Therefore, they have no substantial technical significance. Any modifications to the structure, changes in the proportions, or adjustments to the size, without affecting the effects and purposes that this utility model can produce, should still fall within the scope of the technical content disclosed in this utility model.
[0025] Figure 1 This is a schematic diagram of the overall structure of this utility model;
[0026] Figure 2 This is a schematic diagram of the exploded structure of this utility model;
[0027] Figure 3 This is a schematic diagram of the bottom structure of this utility model. Detailed Implementation
[0028] To make the utility model's objectives, features, and advantages more apparent and understandable, the technical solutions in the embodiments of the present utility model will be clearly and completely described below with reference to the accompanying drawings. Obviously, the embodiments described below are only some embodiments of the present utility model, and not all embodiments. Based on the embodiments of the present utility model, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present utility model.
[0029] In the description of this utility model, it should be understood that the terms "upper," "lower," "top," "bottom," "inner," and "outer," etc., indicating the orientation or positional relationship are based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing this utility model and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this utility model. It should be noted that when a component is considered to be "connected" to another component, it can be directly connected to the other component or there may be a component centrally located at the same time.
[0030] The technical solution of this utility model will be further described below with reference to the accompanying drawings and specific embodiments.
[0031] like Figures 1 to 3 As shown, this embodiment provides a chip packaging structure for stacked photodiodes, including a substrate 1, a first chip 21, a second chip 22, a package housing 3, a focusing lens 4, a conductive copper layer 5, and surface mount leads 6. The substrate 1 has a conductive pad 11 in the middle, the first chip 21 is disposed on the conductive pad 11, and the second chip 22 is stacked on the surface of the first chip 21, with the second chip 22 and the first chip 21 connected by conductive adhesive. The surface area of the first chip 21 is larger than the surface area of the second chip 22. During the packaging process, the first chip 21 is fixed to the conductive pad 11 in the middle of the substrate 1 using a die-bonding process, thereby achieving electrical connection. Subsequently, the smaller second chip 22 is attached to the central area of the first chip 21 and electrically connected by conductive adhesive. This avoids the second chip 22 blocking the photosensitive surface of the underlying first chip 21, thereby improving the utilization rate of incident light.
[0032] The substrate 1 has arc-shaped grooves 10 at its four corners. The conductive copper layer 5 has an arc-shaped segment 51 and a flat segment 52. The arc-shaped segment 51 is located on the wall of the arc-shaped groove 10, and the flat segment 52 is located on the top surface of the substrate 1. The top of the arc-shaped segment 51 is connected to the conductive pad 11 through the flat segment 52. The surface mount pin 6 is located at the bottom of the substrate 1, and the bottom of the arc-shaped segment 51 is connected to the surface mount pin 6. The surface mount pin 6 is used for electrical connection with external circuits. During the packaging process, the conductive copper layer 5 provides electrical connection while also allowing the arc-shaped grooves 10 at the corners of the substrate 1 to tightly adhere to the surface of the substrate 1 along the wall of the arc-shaped grooves 10. Furthermore, the arc-shaped segment 51 can conduct heat from the first chip 21 to the outside of the substrate 1, improving heat dissipation.
[0033] The encapsulation housing 3 is disposed on the top of the substrate 1. The encapsulation housing 3 is used to cover the first chip 21 and the second chip 22, and the space between the encapsulation housing 3 and the substrate 1 is filled with encapsulating colloid. The encapsulation housing 3 can protect the first chip 21 and the second chip 22 from the influence of the external environment. In addition, the encapsulating colloid filled between the encapsulation housing 3 and the substrate 1 can not only provide good sealing performance and prevent external contaminants from entering, but also play a buffering role, reducing the impact of external stress on the chip and enhancing the reliability and durability of the encapsulation. In addition, the encapsulating colloid also has a certain thermal conductivity, which can dissipate the heat generated by the first chip 21 and the second chip 22 more quickly, avoiding excessive temperature rise that would affect the performance of the photodiode.
[0034] The condensing lens 4 is disposed on the top surface of the packaging housing 3, and is used to focus external light onto the first chip 21 and the second chip 22. The condensing lens 4 allows more light to directly illuminate the surfaces of the first chip 21 and the second chip 22, making the light more concentrated on the photosensitive area of the chip, effectively improving the photoelectric conversion efficiency of the photodiode.
[0035] like Figure 1 and Figure 3 As shown, the patch pin 6 further includes a first pin 61, a second pin 62, and a third pin 63. The first pin 61 and the second pin 62 are respectively located on one side of the bottom of the substrate 1, and the first pin 61 and the second pin 62 are respectively connected to the bottom of the arc segment 51 of the conductive copper layer 5. The third pin 63 is located on the other side of the bottom of the substrate 1, and the two ends of the third pin 63 are respectively connected to the bottom of the arc segment 51 of the conductive copper layer 5.
[0036] Furthermore, the focusing lens 4 is a Fresnel lens, which has a concentric ring-shaped stepped structure on its surface. This allows infrared beams from the target direction to converge along the optical axis onto the surfaces of the stacked first chip 21 and second chip 22, thereby effectively increasing the energy density of the received light and enhancing the photoelectric conversion efficiency.
[0037] like Figure 1 and Figure 2 As shown, the corners of the encapsulation housing 3 are further provided with transition arc structures 30.
[0038] Furthermore, the encapsulation housing 3 is made of polycarbonate.
[0039] Furthermore, the substrate 1 and the packaging shell 3 are fixedly connected by a hot melt adhesive layer, which can improve the connection tightness between the substrate 1 and the packaging shell 3 and enhance the stability of the entire packaging structure.
[0040] Furthermore, the encapsulating colloid is silicone or epoxy resin. In this embodiment, the encapsulating colloid is silicone. Silicone has good light transmittance and flexibility, which can protect the first chip 21 and the second chip 22 from the influence of the external environment. At the same time, the temperature resistance and UV resistance of silicone can improve the stability of the photodiode in long-term operation. In addition, the flexibility of silicone allows it to adapt to temperature changes and mechanical stress, enhancing the encapsulation durability and mechanical strength of the photodiode.
[0041] Furthermore, the substrate 1 is made of BT flexible resin glass fiber board, which has good thermal stability. Compared with ordinary epoxy board 1, its coefficient of thermal expansion is lower and it is not easy to deform due to temperature rise or thermal stress, thereby improving the overall structural stability.
[0042] The above-described embodiments are only used to illustrate the technical solutions of this utility model, and are not intended to limit it. Although this utility model has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this utility model.
Claims
1. A chip packaging structure for stacked interconnection of photodiodes, characterized in that: It includes a substrate, a first chip, a second chip, a package housing, a focusing lens, a conductive copper layer, and surface mount pins; The substrate has a conductive pad in the middle, the first chip is disposed on the conductive pad, the second chip is stacked on the surface of the first chip, and the second chip and the first chip are connected by conductive adhesive. The surface area of the first chip is larger than the surface area of the second chip. The substrate has arc-shaped grooves at its four corners. The conductive copper layer has an arc-shaped section and a flat section. The arc-shaped section is located on the wall of the arc-shaped groove, and the flat section is located on the top surface of the substrate. The top of the arc-shaped section is connected to the conductive pad through the flat section. The surface mount pin is located at the bottom of the substrate, and the bottom of the arc segment is connected to the surface mount pin. The surface mount pin is used for electrical connection with external circuitry. The encapsulation housing is disposed on the top of the substrate, the encapsulation housing is used to cover the first chip and the second chip, and the encapsulation colloid is filled between the encapsulation housing and the substrate; The focusing lens is disposed on the top surface of the package housing, and the focusing lens is used to focus external light onto the first chip and the second chip.
2. The chip packaging structure with stacked photodiodes according to claim 1, characterized in that: The surface mount pins include a first pin, a second pin, and a third pin; The first pin and the second pin are respectively located on one side of the bottom of the substrate, and the first pin and the second pin are respectively connected to the bottom of the arc end of the conductive copper layer; The third pin is located on the other side of the bottom of the substrate, and the two ends of the third pin are respectively connected to the bottom of the arc end of the conductive copper layer.
3. The chip packaging structure with stacked photodiodes according to claim 1, characterized in that: The focusing lens is a Fresnel lens.
4. The chip packaging structure with stacked photodiodes according to claim 1, characterized in that: The corners of the encapsulation shell are provided with transition arc structures.
5. The chip packaging structure with stacked photodiodes according to claim 1, characterized in that: The encapsulation housing is made of polycarbonate.
6. The chip packaging structure with stacked photodiodes according to claim 1, characterized in that: The substrate and the packaging shell are fixedly connected by a hot melt adhesive layer.
7. The chip packaging structure with stacked photodiodes according to claim 1, characterized in that: The encapsulating colloid is silicone or epoxy resin.
8. The chip packaging structure with stacked photodiodes according to claim 1, characterized in that: The substrate is made of BT flexible resin glass fiber board.