A display panel and display device

Abstract

The application discloses a display panel and a display device. The display panel comprises a driving substrate, a pixel definition layer, a partition structure and a plurality of sub-pixels. The pixel definition layer is arranged on the driving substrate and forms a pixel containing area. The partition structure is arranged on the pixel definition layer and comprises a padding layer, a partition layer, a conductive part and a partition part arranged in layers. The plurality of sub-pixels are arranged at least partially in the pixel containing area. Each sub-pixel comprises an anode electrode, a hole injection layer, a light-emitting layer group and a cathode electrode arranged in layers. Two adjacent sub-pixels are separated by the partition structure. In the separation direction of the two adjacent sub-pixels, the length of the orthographic projection of the partition layer on the driving substrate is greater than the length of the orthographic projection of the conductive part and the padding layer on the driving substrate, so that the hole injection layer is separated from the conductive part by the partition layer. In this way, the conductive part and the hole injection layer are separated by the partition layer and the padding layer, and the risk of crosstalk between the two adjacent sub-pixels is alleviated.

Description

Technical Field

[0001] This application relates to the field of display technology, and in particular to a display panel and display device. Background Technology

[0002] OLED (Organic Light Emitting Display) is currently the mainstream display technology. OLED display panels include active-matrix OLED (AMOLED) and passive-matrix OLED (PMOLED). Currently, AMOLED is increasingly being manufactured using maskless deposition technology.

[0003] Currently, adjacent sub-pixels are often separated by a partition structure. However, there is a risk that the hole injection layers of two adjacent sub-pixels are electrically connected through the partition structure, which leads to a high risk of crosstalk between the two adjacent sub-pixels. Utility Model Content

[0004] The main objective of this application is to provide a display panel and display device that address the aforementioned technical problems existing in the prior art.

[0005] To address the aforementioned issues, this application provides a display panel comprising a driving substrate, a pixel definition layer, a partition structure, and a plurality of sub-pixels. The pixel definition layer is disposed on the driving substrate, protruding from the driving substrate and forming a pixel receiving area. The partition structure protrudes from the pixel definition layer on the side away from the driving substrate, and includes a padding layer, a partition layer, a conductive portion, and a partition portion stacked in a direction away from the driving substrate. The plurality of sub-pixels are at least partially disposed in the pixel receiving area, and each sub-pixel includes an anode electrode, a hole injection layer, a light-emitting layer group, and a cathode electrode stacked in a direction away from the driving substrate. Adjacent sub-pixels are separated by the partition structure, and the cathode electrodes of adjacent sub-pixels are electrically connected through the conductive portion. In the direction of separation between adjacent sub-pixels, the length of the orthographic projection of the partition layer on the driving substrate is greater than the length of the orthographic projection of the conductive portion and the padding layer on the driving substrate, so that the hole injection layer and the conductive portion are separated by the partition layer.

[0006] In some embodiments, the thickness of the underlay layer is greater than the thickness of the hole injection layer.

[0007] In some embodiments, the thickness of the underlay layer is greater than or equal to 0.01 μm and less than or equal to 0.2 μm.

[0008] In some embodiments, the sum of the thicknesses of the hole injection layer and the light-emitting layer group is greater than the sum of the thicknesses of the padding layer and the barrier layer.

[0009] In some embodiments, the thickness of the partition layer is greater than or equal to 0.1 μm and less than or equal to 0.4 μm.

[0010] In some embodiments, in the spacing direction, the length of the orthogonal projection of the partition layer on the driving substrate is greater than the length of the orthogonal projection of the partition portion on the driving substrate.

[0011] In some embodiments, in the spacing direction, the distance between the first boundary of the partition layer on the side of the orthogonal projection on the driving substrate and the second boundary of the partition portion on the orthogonal projection on the driving substrate that is close to the first boundary is greater than or equal to 0.1 μm and less than or equal to 3 μm.

[0012] In some embodiments, in the spacing direction, the length of the orthographic projection of the partition portion on the driving substrate is greater than the length of the orthographic projection of the conductive portion on the driving substrate.

[0013] In some embodiments, the size of the sidewall of the conductive portion gradually decreases in the direction parallel to the driving substrate from the pixel definition layer to the partition.

[0014] To address the aforementioned problems, this application provides a display device, which includes the aforementioned display panel.

[0015] The beneficial effects of this utility model are as follows: Unlike existing technologies, this application provides a display panel comprising a driving substrate, a pixel definition layer, a partition structure, and multiple sub-pixels. The pixel definition layer is disposed on the driving substrate, protruding from the driving substrate and forming a pixel receiving area. The partition structure protrudes from the pixel definition layer on the side away from the driving substrate, and includes a padding layer, a partition layer, a conductive portion, and a partition portion stacked in a direction away from the driving substrate. Multiple sub-pixels are at least partially disposed in the pixel receiving area. Each sub-pixel includes a stacked anode electrode, a hole injection layer, a light-emitting layer group, and a cathode electrode. Adjacent sub-pixels are separated by the partition structure, and the cathode electrodes of adjacent sub-pixels are electrically connected through the conductive portion. In the direction of separation between adjacent sub-pixels, the length of the orthographic projection of the partition layer onto the driving substrate is greater than the length of the orthographic projection of the conductive portion and the padding layer onto the driving substrate, so that the hole injection layer and the conductive portion are separated by the partition layer. Through the above implementation method, the conductive part and the hole injection layer can be isolated by the isolation layer and the padding layer, thereby mitigating the risk of crosstalk between two adjacent sub-pixels caused by the hole injection layer of the sub-pixel directly overlapping with the conductive part, and improving the reliability of the display panel. Attached Figure Description

[0016] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0017] Figure 1 This is a schematic diagram of the structure of a display device according to one or more embodiments of this application;

[0018] Figure 2 This is a first structural schematic diagram of a display panel according to one or more embodiments of this application;

[0019] Figure 3 This is a second structural schematic diagram of a display panel according to one or more embodiments of this application;

[0020] Figure 4 This is a third structural schematic diagram of a display panel according to one or more embodiments of this application.

[0021] Reference numerals: Display device 1; Display panel 2; Driving substrate 10; Substrate 11; Driving circuit layer 12; Pixel definition layer 20; Pixel receiving area 21; Partition structure 30; Padding layer 31; Partition layer 32; First boundary 321; Conductive part 33; Partition part 34; Second boundary 341; Spacing space 35; Sub-pixel 40; Anode electrode 41; Hole injection layer 42; Light emitting layer group 43; Cathode electrode 44; Spacing direction x1. Detailed Implementation

[0022] The embodiments of the technical solution of this application will now be described in detail with reference to the accompanying drawings. These embodiments are only used to more clearly illustrate the technical solution of this application and are therefore merely examples, and should not be used to limit the scope of protection of this application.

[0023] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains; the terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the application; the terms “comprising” and “having”, and any variations thereof, in the specification, claims, and foregoing description of the drawings are intended to cover non-exclusive inclusion.

[0024] In the description of the embodiments of this application, technical terms such as "first" and "second" are used only to distinguish different objects and should not be construed as indicating or implying relative importance or implicitly specifying the number, specific order, or primary and secondary relationship of the indicated technical features. In the description of the embodiments of this application, "multiple" means two or more, unless otherwise explicitly defined.

[0025] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0026] In the description of the embodiments in this application, the term "and / or" is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, and B existing alone. Additionally, the character " / " in this document generally indicates that the preceding and following related objects have an "or" relationship.

[0027] In the description of the embodiments of this application, the term "multiple" refers to two or more (including two), similarly, "multiple sets" refers to two or more (including two sets), and "multiple pieces" refers to two or more (including two pieces).

[0028] In the description of the embodiments of this application, the technical terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," "axial," "radial," and "circumferential" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing the embodiments of this application and simplifying the description, and are not intended to indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on the embodiments of this application.

[0029] In the description of the embodiments of this application, unless otherwise expressly specified and limited, technical terms such as "installation," "connection," "joining," and "fixing" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. For those skilled in the art, the specific meaning of the above terms in the embodiments of this application can be understood according to the specific circumstances.

[0030] OLED (Organic Light Emitting Display) is currently the mainstream display technology. OLED display panels include active-matrix OLED (AMOLED) and passive-matrix OLED (PMOLED). Currently, AMOLED is increasingly being manufactured using maskless deposition technology.

[0031] Currently, adjacent sub-pixels are often separated by a partition structure. However, there is a risk that the hole injection layers of two adjacent sub-pixels are electrically connected through the partition structure, which leads to a high risk of crosstalk between the two adjacent sub-pixels.

[0032] This application provides a display device, which may include, but is not limited to, mobile phones, tablets, laptops, desktop computers, terminals, interactive displays, digital audio-visual equipment, IoT devices, etc. Interactive displays may include interactive whiteboards, digital advertising interactive screens, and interactive gaming displays, etc. IoT devices may include smart home devices and smart wearable devices, etc. The display device may include a display panel, which can provide a display interface and touch input to achieve corresponding functions.

[0033] Please refer to Figure 1 , Figure 1 This is a schematic diagram of the structure of a display device according to one or more embodiments of this application.

[0034] Display device 1 can be a regular mobile phone, feature phone, or smartphone. A smartphone can be a flat-screen phone, a curved-screen phone, or a foldable phone, etc. Display device 1 has a display panel 2, which can be located at the top, middle, or bottom of display device 1. Display panel 2 can be used to display information on display device 1; for example, it can serve as the visual information display section of display device 1. Display panel 2 can also serve as a touch information input section, allowing users to operate display device 1 by touching display panel 2, for example, to meet the display and input needs during interface navigation and function switching of display device 1.

[0035] See Figures 2-3 , Figure 2 This is a first structural schematic diagram of a display panel according to one or more embodiments of this application; Figure 3 This is a second structural schematic diagram of a display panel according to one or more embodiments of this application.

[0036] To address the aforementioned problems, this application provides a display panel 2, which includes a driving substrate 10, a pixel definition layer 20, a partition structure 30, and a plurality of sub-pixels 40. The pixel definition layer 20 is disposed on the driving substrate 10, protruding from the driving substrate 10 and forming a pixel receiving area 21. The partition structure 30 protrudes from the side of the pixel definition layer 20 away from the driving substrate 10, and includes a padding layer 31, a partition layer 32, a conductive portion 33, and a partition portion 34 stacked in a direction away from the driving substrate 10. The plurality of sub-pixels 40 are at least partially disposed In the pixel accommodating region 21, each sub-pixel 40 includes a stacked anode electrode 41, a hole injection layer 42, a light-emitting layer group 43, and a cathode electrode 44. Two adjacent sub-pixels 40 are separated by a partition structure 30, and the cathode electrodes 44 of two adjacent sub-pixels 40 are electrically connected through a conductive part 33. In the spacing direction x1 between two adjacent sub-pixels 40, the length of the orthographic projection of the partition layer 32 on the driving substrate 10 is greater than the length of the orthographic projection of the conductive part 33 and the padding layer 31 on the driving substrate 10, so that the hole injection layer 42 and the conductive part 33 are separated by the partition layer 32.

[0037] The driving substrate 10 may include a substrate 11 and a driving circuit layer 12. The substrate 11 may be a glass substrate or a flexible substrate, wherein the flexible substrate is made of polyimide (PI). The driving circuit layer 12 may be a TFT circuit layer, which is used to drive the light-emitting layer group 43 of the sub-pixel 40. Specifically, the TFT circuit layer includes multiple arrayed driving circuit units, each driving circuit unit may include a thin-film transistor (TFT) device and a capacitor. Each driving circuit unit corresponds to an anode electrode 41 and a light-emitting layer group 43. The TFT device is of the low-temperature polysilicon (LTPS) type or the metal-oxide semiconductor (MOS) type, such as indium gallium zinc oxide (IGZO) MOS type.

[0038] A pixel definition layer 20 is disposed on the driving substrate 10, protruding from the driving substrate 10 and forming a pixel receiving region 21. The pixel definition layer 20 can define the position of the sub-pixel 40 through the pixel receiving region 21, so that the sub-pixel 40 is positioned appropriately. The material of the pixel definition layer 20 can be an organic material, an organic material with an inorganic coating disposed thereon, or an inorganic material. The organic material of the pixel definition layer 20 includes, but is not limited to, polyimide. The inorganic material of the pixel definition layer 20 includes, but is not limited to, silicon oxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (Si2N2O), magnesium fluoride (MgF2), or combinations thereof.

[0039] Multiple sub-pixels 40 are at least partially disposed in the pixel receiving region 21. Each sub-pixel 40 includes a stacked anode electrode 41, a hole injection layer 42, a light-emitting layer group 43, and a cathode electrode 44. The cathode electrodes 44 of two adjacent sub-pixels 40 are electrically connected through a conductive portion 33. The anode electrode 41 is disposed between the pixel defining layer 20 and the driving substrate 10. Specifically, the anode electrode 41 may be disposed on the surface of the driving circuit layer 12 away from the substrate 11. For example, multiple anode electrodes 41 are arranged in an array, and each anode electrode 41 corresponds one-to-one with and is electrically connected to a driving circuit unit in the driving circuit layer 12. The materials of the anode electrode 41 include, but are not limited to, chromium, titanium, gold, silver, copper, aluminum, ITO, combinations thereof, or other suitable conductive materials.

[0040] The hole injection layer 42 is a key functional layer located between the anode and the light-emitting layer group 43 in optoelectronic devices (such as OLEDs), and is typically made of conductive polymer or metal oxide materials. The light-emitting layer group 43 includes a light-emitting layer, which can be used to emit at least one of red, blue, or green light when energized.

[0041] The partition structure 30 protrudes from the pixel definition layer 20 on the side facing away from the driving substrate 10, and two adjacent sub-pixels 40 are separated by the partition structure 30. The partition structure 30 includes a padding layer 31, a partition layer 32, a conductive portion 33, and a partition portion 34 stacked in the direction away from the driving substrate 10. It can be understood that the padding layer 31 is closest to the pixel definition layer 20, and the partition portion 34 is furthest away from the pixel definition layer 20.

[0042] It should be noted that the partition 34 can be used to separate the hole injection layer material, the light-emitting layer material, and the cathode electrode material during the deposition and formation of the sub-pixel 40, thereby forming two spaced-apart sub-pixels 40 on both sides of the partition structure 30. The partition 34 can be made of organic or inorganic materials. Organic materials can include, but are not limited to, soluble polytetrafluoroethylene (PFA) and polyimide (PI), etc., while inorganic materials can include, but are not limited to, metals, metal oxides, or combinations thereof. The conductive part 33 is conductive and can be made of, but is not limited to, metals or metal oxides, or combinations thereof. Specifically, metals can include, but are not limited to, copper, iron, aluminum, molybdenum, nickel, silver, magnesium, calcium, or combinations thereof, etc., while metal oxides can include, but are not limited to, indium oxide, tin oxide, indium tin oxide, or combinations thereof, etc. The conductive part 33 is used to electrically connect the cathode electrodes 44 of two adjacent sub-pixels 40. The material of the padding layer 31 can include, but is not limited to, molybdenum, copper, inorganic silicides, etc. It should be noted that the material of the partition layer 32 is different from that of the padding layer 31. For example, when the material of the partition layer 32 is an inorganic silicon compound, the material of the padding layer 31 can be metal, thereby reducing the molding difficulty of the partition layer 32 and the padding layer 31.

[0043] The partition layer 32 is located between the padding layer 31 and the conductive portion 33. In the spacing direction x1 between two adjacent sub-pixels 40, the length of the orthographic projection of the partition layer 32 on the driving substrate 10 is greater than the length of the orthographic projection of the conductive portion 33 and the padding layer 31 on the driving substrate 10. It should be noted that the length of the orthographic projection of the partition layer 32 on the driving substrate 10 is greater than the length of the orthographic projection of the conductive portion 33 and the padding layer 31 on the driving substrate 10. An interval space 35 is formed between the partition layer 32 and the pixel definition layer 20. During the deposition of the hole injection layer material, due to the presence of the interval space 35, the sidewall of the partition layer 32 is difficult to provide stable support for the hole injection layer material. As a result, some hole injection layer material will fall into the interval space 35 instead of continuing to accumulate thickness towards the conductive portion 33 along the sidewall of the partition layer 32. This causes the hole injection layer 42 of the sub-pixel 40 to be disconnected from the conductive portion 33, thus mitigating the risk of crosstalk between two adjacent sub-pixels 40 caused by the overlap of the hole injection layer 42 and the conductive portion 33. Understandably, in some application scenarios, the partition layer 32 can also block some hole injection layer material on the side of the partition layer 32 away from the padding layer 31. However, due to the existence of the space 35, some hole injection layer material will fall into the space 35 instead of continuing to accumulate thickness towards the conductive part 33. This causes the hole injection layer 42 of the sub-pixel 40 to break away from the part of hole injection layer material blocked by the partition layer 32, thereby causing the hole injection layer 42 to break away from the conductive part 33.

[0044] Through the above embodiments, the conductive part 33 can be isolated from the hole injection layer 42 by the isolation layer 32 and the padding layer 31, thereby mitigating the risk of crosstalk between two adjacent sub-pixels 40 caused by the hole injection layer 42 of the sub-pixel 40 directly overlapping with the conductive part 33, and improving the reliability of the display panel 2.

[0045] In some embodiments, the thickness of the padding layer 31 is greater than the thickness of the hole injection layer 42. It is understood that by setting the thickness of the padding layer 31 to be greater than the thickness of the hole injection layer 42, the difficulty of accumulating the material of the hole injection layer 42 along the sidewall of the partition layer 32 towards the conductive portion 33 is further increased, reducing the risk of electrical connection between the hole injection layer 42 and the conductive portion 33, and further improving the reliability of the display panel 2. In some applications, the size of the padding layer 31 in the spacing direction x1 can gradually increase or decrease in the direction away from the pixel definition layer 20.

[0046] In some embodiments, the thickness of the padding layer 31 is greater than or equal to 0.01 μm and less than or equal to 0.2 μm. Optionally, the thickness of the padding layer 31 can be, but is not limited to, 0.01 μm, 0.11 μm, 0.12 μm, 0.15 μm, 0.18 μm, 0.2 μm, etc. Therefore, by setting a larger thickness for the padding layer 31, the difficulty of accumulating the material of the hole injection layer 42 along the sidewall of the barrier layer 32 towards the conductive portion 33 is increased, mitigating the risk of crosstalk between adjacent sub-pixels 40 caused by the hole injection layer 42 of the sub-pixel 40 directly overlapping with the conductive portion 33.

[0047] In some embodiments, in the spacing direction x1, the difference between half the length of the orthographic projection of the partition layer 32 on the driving substrate 10 and half the length of the orthographic projection of the padding layer 31 on the driving substrate 10 is greater than or equal to 0.01 μm and less than or equal to 0.2 μm.

[0048] In some embodiments, the sum of the thicknesses of the hole injection layer 42 and the light-emitting layer group 43 is greater than the sum of the thicknesses of the padding layer 31 and the barrier layer 32. It is understood that by setting the sum of the thicknesses of the hole injection layer 42 and the light-emitting layer group 43 to be greater than the sum of the thicknesses of the padding layer 31 and the barrier layer 32, it is beneficial for the material of the light-emitting layer group 43 to be continuously deposited on the side of the hole injection layer 42 away from the driving substrate 10 and on the side of the barrier layer 32 away from the pixel definition layer 20. This facilitates the continuous deposition of the cathode electrode 44 on the side of the light-emitting layer group 43 away from the driving substrate 10, reduces the molding difficulty of the cathode electrode 44, and improves the reliability of the display panel 2. In some applications, the light-emitting layer group 43 includes a light-emitting layer and a functional layer group, wherein the functional layer group includes one or more of a hole transport layer, an electron blocking layer, an electron transport layer, an electron injection layer, and a protective layer.

[0049] In some embodiments, the thickness of the partition layer 32 is greater than or equal to 0.1 μm and less than or equal to 0.4 μm. Optionally, the thickness of the partition layer 32 can be between 0.1 μm and 0.2 μm, or between 0.3 μm and 0.4 μm, etc. Specifically, the thickness of the partition layer 32 can be, but is not limited to, 0.1 μm, 0.2 μm, 0.25 μm, 0.3 μm, 0.4 μm, etc. Therefore, by reasonably setting the thickness of the partition layer 32, it is beneficial to increase the difficulty of accumulating the thickness of the hole injection layer 42 material along the sidewall of the partition layer 32 towards the conductive portion 33, while facilitating the continuous deposition of the material of the light-emitting layer group 43 on the side of the hole injection layer 42 away from the driving substrate 10 and on the side of the partition layer 32 away from the pixel definition layer 20, thereby reducing the molding difficulty of the cathode electrode 44.

[0050] In some embodiments, the length of the orthographic projection of the partition layer 32 onto the driving substrate 10 in the spacing direction x1 is greater than the length of the orthographic projection of the partition portion 34 onto the driving substrate 10. This facilitates the blocking of a portion of the hole injection layer material exceeding the length range of the partition portion 34 in the spacing direction x1 during the deposition of the hole injection layer material. This further increases the difficulty of overlapping between the hole injection layer 42 and the conductive portion 33. Simultaneously, increasing the length of the partition layer 32 in the spacing direction x1 helps to continuously deposit the material of the light-emitting layer group 43 on the side of the partition layer 32 away from the pixel definition layer 20, thereby reducing the molding difficulty of the cathode electrode 44.

[0051] In some embodiments, in the spacing direction x1, the distance between the first boundary 321 of the partition layer 32 on the driving substrate 10 (where its orthogonal projection is on the driving substrate 10) and the second boundary 341 of the partition portion 34 on the driving substrate 10 (where its orthogonal projection is on the driving substrate 10) near the first boundary 321 is greater than or equal to 0.1 μm and less than or equal to 3 μm is less than or equal to 3 μm. For example, the sub-pixels 40 on both sides of the partition structure 30 are defined as a first pixel and a second pixel, respectively. Taking the first pixel as an example, the boundary of the partition layer 32 on the driving substrate 10 near the first pixel is the first boundary 321, and correspondingly, the boundary of the partition portion 34 on the driving substrate 10 near the first pixel is the second boundary 341. The distance between the first boundary 321 and the second boundary 341 is greater than or equal to 0.1 μm and less than or equal to 3 μm. The same applies to the second pixel. Therefore, by reasonably setting the spacing between the first boundary 321 and the second boundary 341, it is beneficial to better ensure that the material of the light-emitting layer group 43 is continuously deposited on the side of the partition layer 32 away from the pixel definition layer 20, thereby reducing the molding difficulty of the cathode electrode 44. Optionally, the spacing between the first boundary 321 and the second boundary 341 can be between 0.1μm and 2μm, or between 1.5μm and 3μm, or between 2μm and 3μm. Specifically, the spacing between the first boundary 321 and the second boundary 341 can be 0.1μm, 0.8μm, 1.5μm, 2μm, 3μm, etc.

[0052] In some embodiments, in the spacing direction x1, the length of the orthographic projection of the partition portion 34 on the driving substrate 10 is greater than the length of the orthographic projection of the conductive portion 33 on the driving substrate 10. Therefore, by setting the length of the orthographic projection of the partition portion 34 on the driving substrate 10 to be greater than the length of the orthographic projection of the conductive portion 33 on the driving substrate 10 in the spacing direction x1, the partition portion 34 can better shield and isolate the hole injection layer material during deposition, reducing the risk of electrical connection between the hole injection layer 42 and the conductive portion 33. In some applications, the difference between half the length of the orthographic projection of the partition portion 34 on the driving substrate 10 and half the length of the orthographic projection of the conductive portion 33 on the driving substrate 10 in the spacing direction x1 is greater than or equal to 0.4 μm and less than or equal to 1 μm. The thickness of the conductive portion can be greater than or equal to 0.5 μm and less than or equal to 1.2 μm. The thickness of the partition structure 30 can be greater than or equal to 0.05 μm and less than or equal to 3 μm.

[0053] In some embodiments, the size of the sidewall of the conductive portion 33 gradually decreases in the direction parallel to the driving substrate 10 from the pixel definition layer 20 to the partition portion 34. As a result, the conductive portion 33 is wider at the end near the cathode electrode 44 and narrower at the end near the partition portion 34, which facilitates the cathode electrodes 44 of the multiple sub-pixels 40 to overlap with the conductive portion 33 and conduct electricity.

[0054] Combination Figure 4 , Figure 4 This is a third structural schematic diagram of a display panel according to one or more embodiments of this application.

[0055] In some other embodiments, in the spacing direction x1, the length of the orthographic projection of the partition layer 32 on the driving substrate 10 is less than the length of the orthographic projection of the partition portion 34 on the driving substrate 10, but greater than the length of the orthographic projection of the conductive portion 33 on the driving substrate 10. In the spacing direction x1, the distance between the first boundary 321 on the side of the orthographic projection of the partition layer 32 on the driving substrate 10 and the second boundary 341 on the side of the orthographic projection of the partition portion 34 on the driving substrate 10 that is close to the first boundary 321 is greater than or equal to 0.1 μm and less than or equal to 0.3 μm.

[0056] In summary, this application provides a display panel 2, which includes a driving substrate 10, a pixel definition layer 20, a partition structure 30, and a plurality of sub-pixels 40. The pixel definition layer 20 is disposed on the driving substrate 10, protruding from the driving substrate 10 and forming a pixel receiving area 21. The partition structure 30 protrudes from the side of the pixel definition layer 20 away from the driving substrate 10, and includes a padding layer 31, a partition layer 32, a conductive portion 33, and a partition portion 34 stacked in a direction away from the driving substrate 10. The plurality of sub-pixels 40 are at least partially disposed on the driving substrate 10. In the pixel accommodating area 21, each sub-pixel 40 includes a stacked anode electrode 41, a hole injection layer 42, a light-emitting layer group 43, and a cathode electrode 44. Adjacent sub-pixels 40 are separated by a partition structure 30, and the cathode electrodes 44 of adjacent sub-pixels 40 are electrically connected through a conductive portion 33. Specifically, in the spacing direction x1 between adjacent sub-pixels 40, the length of the orthographic projection of the partition layer 32 onto the driving substrate 10 is greater than the length of the orthographic projection of the conductive portion 33 and the padding layer 31 onto the driving substrate 10, so that the hole injection layer 42 and the conductive portion 33 are separated by the partition layer 32. Through this embodiment, the conductive portion 33 and the hole injection layer 42 can be separated by the partition layer 32 and the padding layer 31, thereby mitigating the risk of crosstalk between adjacent sub-pixels 40 caused by the hole injection layer 42 directly contacting the conductive portion 33, and improving the reliability of the display panel 2.

[0057] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and not to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. These modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application, and they should all be covered within the scope of the claims and specification of this application. In particular, as long as there is no structural conflict, the various technical features mentioned in the embodiments can be combined in any way. This application is not limited to the specific embodiments disclosed herein, but includes all technical solutions falling within the scope of the claims.

Claims

1. A display panel, characterized by, The display panel includes: Drive substrate; A pixel definition layer is disposed on the driving substrate, the pixel definition layer protrudes from the driving substrate and forms a pixel accommodating area; A partition structure protrudes from the pixel definition layer on the side opposite to the driving substrate. The partition structure includes a padding layer, a partition layer, a conductive portion, and a partition portion stacked in a direction away from the driving substrate. Multiple sub-pixels are at least partially disposed in the pixel accommodating area. Each sub-pixel includes a stacked anode electrode, a hole injection layer, a light-emitting layer group, and a cathode electrode. Adjacent sub-pixels are separated by the partition structure, and the cathode electrodes of adjacent sub-pixels are electrically connected through the conductive part. In the direction of the interval between two adjacent sub-pixels, the length of the orthographic projection of the isolation layer on the driving substrate is greater than the length of the orthographic projection of the conductive portion and the padding layer on the driving substrate, so that the hole injection layer and the conductive portion are isolated by the isolation layer.

2. The display panel according to claim 1, characterized in that, The thickness of the underlayment layer is greater than the thickness of the cavitation injection layer.

3. The display panel according to claim 2, characterized in that, The thickness of the underlayment layer is greater than or equal to 0.01 μm and less than or equal to 0.2 μm.

4. The display panel according to claim 2, characterized in that, The sum of the thicknesses of the hole injection layer and the light-emitting layer group is greater than the sum of the thicknesses of the padding layer and the partition layer.

5. The display panel according to claim 4, characterized in that, The thickness of the partition layer is greater than or equal to 0.1 μm and less than or equal to 0.4 μm.

6. The display panel according to claim 1, characterized in that, In the spacing direction, the length of the orthogonal projection of the partition layer on the driving substrate is greater than the length of the orthogonal projection of the partition portion on the driving substrate.

7. The display panel according to claim 6, characterized in that, In the spacing direction, the distance between the first boundary of the partition layer on the side of its orthogonal projection on the driving substrate and the second boundary of the partition portion on the driving substrate near the first boundary is greater than or equal to 0.1 μm and less than or equal to 3 μm.

8. The display panel according to claim 1, characterized in that, In the spacing direction, the length of the orthogonal projection of the partition portion on the driving substrate is greater than the length of the orthogonal projection of the conductive portion on the driving substrate.

9. The display panel according to claim 8, characterized in that, From the pixel definition layer to the partition, the size of the sidewall of the conductive portion gradually decreases in the direction parallel to the driving substrate.

10. A display device, characterized in that, The display device includes a display panel as described in any one of claims 1-9.

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