Display substrate and display device

Abstract

The display substrate and the display device are provided. The display substrate comprises a display area and a first frame area located on at least one side. A circuit structure layer and a protection structure layer are sequentially arranged on one side of a substrate. The protection structure layer is provided with a protection structure. The first frame area comprises a bending area. In the bending area, an inorganic insulating layer in the circuit structure layer is removed to form a first bending opening. A normal projection of at least one boundary of the first bending opening on the substrate is covered by a normal projection of the protection structure on the substrate. In a direction from the display area to the first frame area, the protection structure and the at least one boundary of the first bending opening are located on at least one side of the bending area. The technical scheme provided by the embodiments of the present disclosure can solve the technical problem of film layer falling off or crack near the bending area to a certain extent.

Description

Technical Field

[0001] This disclosure relates to, but is not limited to, the field of display technology, and in particular to a display substrate and a display device. Background Technology

[0002] Organic light-emitting diodes (OLEDs) and quantum dot light-emitting diodes (QLEDs) are active-matrix display devices with advantages such as self-illumination, wide viewing angle, high contrast, low power consumption, extremely high response speed, thinness, flexibility, and low cost. With the continuous development of display technology, flexible displays using OLEDs or QLEDs as light-emitting devices and controlled by thin-film transistors (TFTs) have become the mainstream products in the display field.

[0003] Currently, display substrates have a technical problem where the film layer near the bending area is prone to peeling off or cracking. Utility Model Content

[0004] The problem to be solved by the embodiments of this disclosure is to provide a display substrate and a display device to solve the technical problem that the film layer near the bending area of ​​the existing display substrate is prone to peeling off or cracking.

[0005] To address the aforementioned technical problems, in a first aspect, embodiments of this disclosure provide a display substrate, comprising:

[0006] A substrate, the substrate including a display area and a first border area located on at least one side of the display area;

[0007] A circuit structure layer is located on one side of the substrate.

[0008] A protective structure layer is located on the side of the circuit structure layer away from the substrate, and the protective structure layer is provided with a protective structure;

[0009] A bending area is located in the first frame area, in which the inorganic insulating layer in the circuit structure layer is removed to form a first bending opening;

[0010] Wherein, at least one boundary of the first bending opening is orthographically projected onto the substrate by the orthographically projected onto the substrate by the protective structure, and along the direction from the display area to the first border area, the protective structure and at least one boundary of the first bending opening are located on at least one side of the bending area.

[0011] In an exemplary embodiment, the protective structure includes a first protective structure and a second protective structure, and at least one boundary of the first bent opening includes a first boundary and a second boundary;

[0012] Along the direction from the display area to the first border area, the first protective structure and the first boundary are located on the side of the bending area closer to the display area, and the second protective structure and the second boundary are located on the side of the bending area away from the display area.

[0013] The orthographic projection of the first boundary on the substrate is covered by the orthographic projection of the first protective structure on the substrate; the orthographic projection of the second boundary on the substrate is covered by the orthographic projection of the second protective structure on the substrate.

[0014] In an exemplary embodiment, the protective structure layer includes at least a touch structure layer, the touch structure layer including a touch planarization layer, and in a direction perpendicular to the plane of the substrate, the touch planarization layer is located as the film layer farthest from the circuit structure layer in the touch structure layer; at least a portion of the structure of the protective structure is located in the touch planarization layer.

[0015] In an exemplary embodiment, the protective structure layer further includes a first protective layer, which is located on the side of the touch planarization layer away from the substrate in a direction perpendicular to the plane of the substrate.

[0016] The touch planarization layer includes a first region, a second region, and at least one blocking structure. The blocking structure is located in the first border region. The first region of the touch planarization layer and the first protective layer form a cover layer. The cover layer is located in the display region and extends to the first border region in a direction from the display region to the first border region. The cover layer is located on the side of the at least one blocking structure away from the bending area. The second region of the touch planarization layer is located on the side of the bending area away from the display region. The second protective structure includes at least the second region of the touch planarization layer.

[0017] In an exemplary embodiment, the at least one blocking structure includes a first blocking structure and a second blocking structure, which are located along the direction from the display area to the first border area, with the first blocking structure located on the side of the second blocking structure away from the display area.

[0018] The first blocking structure's orthogonal projection on the substrate covers the orthogonal projection of the first boundary on the substrate, and the first protective structure includes the first blocking structure; or, the second blocking structure's orthogonal projection on the substrate covers the orthogonal projection of the first boundary on the substrate, and the first protective structure includes the second blocking structure.

[0019] In an exemplary embodiment, along the direction from the display area to the first border area: in a structure where the orthogonal projection of the first blocking structure on the substrate covers the orthogonal projection of the first boundary on the substrate, the size of the first blocking structure is larger than the size of the second blocking structure; in a structure where the orthogonal projection of the second blocking structure on the substrate covers the orthogonal projection of the first boundary on the substrate, the size of the first blocking structure is smaller than the size of the second blocking structure.

[0020] In an exemplary embodiment, the at least one blocking structure includes a first blocking structure in the direction from the display area to the first border area, the edge of the cover layer near the bending area is located between the first boundary and the first blocking structure, the orthographic projection of the first boundary on the substrate is within the range of the orthographic projection of the cover layer on the substrate, and the first protective structure includes the cover layer.

[0021] In an exemplary embodiment, in the first border region, along the direction from the display region to the first border region, the boundary of the first protective layer on the side away from the display region is located between the boundary of the first region of the touch flat layer on the side away from the display region and the at least one blocking structure.

[0022] In an exemplary embodiment, along the direction from the display area to the first border area, the second boundary is located between the second region of the touch planarization layer and the bending area, and the orthographic projection of the second boundary on the substrate is within the range of the orthographic projection of the second region of the touch planarization layer on the substrate.

[0023] In an exemplary embodiment, the protective structure layer includes at least a touch structure layer, which includes at least one first signal connection line and a touch inorganic insulating layer. In a direction perpendicular to the plane of the substrate, the touch inorganic insulating layer is located on the side of the first signal connection line closer to the substrate.

[0024] The protective structure includes at least one of the first signal connection line and the touch inorganic insulating layer.

[0025] In an exemplary embodiment, the touch structure layer further includes a touch planarization layer, which is located on the side of the first signal connection line away from the substrate in a direction perpendicular to the plane of the substrate, and at least a portion of the protective structure is located in the touch planarization layer.

[0026] Along the direction from the display area to the first border area, in the protective structure on the same side of the bending area: the orthographic projection of the structure located on the touch planarization layer on the substrate covers the orthographic projection of the structure located on the touch inorganic insulating layer on the substrate; the orthographic projection of the structure located on the touch planarization layer on the substrate covers the orthographic projection of the first signal connection line on the substrate.

[0027] In an exemplary embodiment, in the structure in which the first protective structure includes the first signal connection line, along the direction from the display area to the first border area: the first signal connection line in the first protective structure is located on the side of the bending area close to the display area, and both ends are located on both sides of the first boundary, and the first signal connection line in the first protective structure at least partially overlaps with the orthographic projection of the first boundary on the substrate.

[0028] In an exemplary embodiment, in the structure in which the second protection structure includes the first signal connection line, along the direction from the display area to the first border area: the first signal connection line in the second protection structure is located on the side of the bending area away from the display area, and both ends are located on both sides of the second boundary, and the first signal connection line in the second protection structure at least partially overlaps with the orthographic projection of the second boundary on the substrate.

[0029] In an exemplary embodiment, the circuit structure layer further includes at least one second signal connection line, at least a portion of the structure of the second signal connection line is located in the bending area, the same second signal connection line corresponds to two first signal connection lines, along the direction from the display area to the first border area, of the two first signal connection lines corresponding to the same second signal connection line, one first signal connection line is located on the side of the bending area closer to the display area, and the other first signal connection line is located on the side of the bending area away from the display area;

[0030] In the first border region, the touch-sensitive inorganic insulating layer includes a first opening that exposes at least a portion of the structure of the second signal connection line, through which the first signal connection line is electrically connected to the corresponding second signal connection line.

[0031] In an exemplary embodiment, along the direction from the display area to the first border area, on the side of the bending area near the display area, the first opening is located on the side of the first boundary near the display area. In the structure in which the first protective structure includes the touch inorganic insulating layer, the first protective structure includes a touch inorganic insulating layer located between the first opening and the bending area. The orthographic projection of the touch inorganic insulating layer in the first protective structure on the substrate covers the orthographic projection of the first boundary on the substrate.

[0032] In an exemplary embodiment, along the direction from the display area to the first border area, on the side of the bending area away from the display area, the first opening is located on the side of the second boundary away from the display area. In the structure where the second protective structure includes the touch inorganic insulating layer, the second protective structure includes a touch inorganic insulating layer located between the first opening and the bending area. The orthographic projection of the touch inorganic insulating layer in the second protective structure on the substrate covers the orthographic projection of the second boundary on the substrate.

[0033] In an exemplary embodiment, in the bending area, the touch inorganic insulating layer in the touch structure layer is removed to form a second bending opening. The second bending opening includes a third boundary and a fourth boundary. In the structure of the protective structure including the touch inorganic insulating layer, along the direction from the display area to the first border area: the third boundary is located between the first boundary and the bending area, and the fourth boundary is located between the second boundary and the bending area.

[0034] In an exemplary embodiment, the circuit structure layer further includes a first planarization layer and a second planarization layer. In a direction perpendicular to the plane of the substrate, the first planarization layer is located between the inorganic insulating layer and the at least one second signal connection line in the circuit structure layer, and the second planarization layer is located on the side of the at least one second signal connection line away from the substrate. The first bend opening is filled by the first planarization layer, and the orthographic projection of the first bend opening on the substrate is within the range of the orthographic projection of the second planarization layer on the substrate.

[0035] In the first border region, the second planarization layer includes a second opening that exposes at least a portion of the structure of the second signal connection line, through which the first signal connection line is electrically connected to a corresponding second signal connection line.

[0036] In an exemplary embodiment, in the first opening and the second opening corresponding to the same second signal connection line, the orthographic projection of the first opening on the substrate is within the range of the orthographic projection of the second opening on the substrate.

[0037] In an exemplary embodiment, the display substrate further includes:

[0038] Multiple first signal lines are located in the display area;

[0039] Multiple pads are located in the first frame area and on the side of the bending area away from the display area;

[0040] The end of the at least one second signal connection line away from the display area is electrically connected to at least one pad via a corresponding first signal connection line, and the end closer to the display area is electrically connected to at least one first signal line via a corresponding first signal connection line.

[0041] In an exemplary embodiment, in the direction from the circuit structure layer to the protective structure layer, the touch structure layer includes a touch buffer layer, a first touch conductive layer, an interlayer insulation layer, a second touch conductive layer, and a touch planarization layer arranged sequentially; the first signal connection line is located in the second touch conductive layer; the touch inorganic insulation layer includes the touch buffer layer and the interlayer insulation layer; and at least a portion of the protective structure is located in the touch planarization layer.

[0042] The first touch conductive layer includes at least one third signal connection line in the direction from the display area to the first frame area. The at least one third signal connection line corresponds one-to-one with at least one first signal connection line located on the side of the bending area near the display area. In the first frame area, the touch layer insulating layer includes a third opening that exposes at least a portion of the structure of the third signal connection line. The first signal connection line is electrically connected to the corresponding third signal connection line through the third opening.

[0043] In an exemplary embodiment, along the direction from the display area to the first border area, on the same side of the bending area, the center position of the third signal connection line is located on the side of the center position of the first signal connection line away from the bending area, and the first opening is located between the third opening and the bending area; the end of the second signal connection line near the display area is electrically connected to at least one first signal line through a corresponding first signal connection line and a corresponding third signal connection line.

[0044] In an exemplary embodiment, the display area includes a plurality of sub-pixels, at least one sub-pixel includes a pixel driving circuit and a light-emitting element, the pixel driving circuit is located in the circuit structure layer, and at least one pixel driving circuit includes a transfer electrode, a plurality of transistors and at least one capacitor; in the same sub-pixel, the pixel driving circuit is electrically connected to the light-emitting element through the transfer electrode;

[0045] In a direction perpendicular to the plane of the substrate, the light-emitting element is located between the circuit structure layer and the protective structure layer. The capacitor includes a first electrode plate and a second electrode plate sequentially disposed on one side of the substrate. The transistor includes an active layer, a control electrode, a first electrode, and a second electrode. The active layer is located on the side of the first electrode plate closer to the substrate. The control electrode is disposed on the same layer as the first electrode plate. The first electrode and the second electrode are located on the side of the second electrode plate away from the substrate. The transition electrode is located on the side of the first electrode and the second electrode away from the substrate. The second signal connection line is disposed on the same layer as the transition electrode.

[0046] In an exemplary embodiment, in a direction perpendicular to the plane of the substrate, the inorganic insulating layer in the circuit structure layer includes at least: a first gate insulating layer located between the active layer and the control electrode, a second gate insulating layer located between the control electrode and the second electrode plate, an interlayer insulating layer located between the first electrode and the second electrode and the second electrode plate, and a passivation layer located between the first electrode and the second electrode and the transition electrode.

[0047] In an exemplary embodiment, the display substrate further includes a light-emitting structure layer, which is located between the circuit structure layer and the protective structure layer in a direction perpendicular to the plane of the substrate. The light-emitting structure layer includes a pixel definition layer.

[0048] The pixel definition layer includes a first structural portion, at least a portion of which is located in the bending region. The orthographic projection of the first structural portion of the pixel definition layer on the substrate covers the orthographic projection of the first bending opening on the substrate.

[0049] In an exemplary embodiment, in the first border region, along the direction pointing from the display region to the first border region: on the side of the bending region near the display region, the first structural portion is located on the side of the first opening away from the display region, and the orthographic projection of the first structural portion of the pixel definition layer on the substrate at least partially overlaps with the orthographic projection of the first protective structure and the first boundary of the pixel definition layer on the substrate; on the side of the bending region away from the display region, the first structural portion of the pixel definition layer is located on the side of the first opening near the display region, and the orthographic projection of the first structural portion of the pixel definition layer on the substrate at least partially overlaps with the orthographic projection of the second protective structure and the second boundary on the substrate.

[0050] In an exemplary embodiment, along the direction from the display area to the first border area: a first buffer zone is provided between the first boundary and the bending area, and the orthographic projection of the boundary of the first protective structure on the side near the bending area on the substrate is located within the range of the orthographic projection of the first buffer zone on the substrate; a second buffer zone is provided between the second boundary and the bending area, and the orthographic projection of the boundary of the second protective structure on the side near the bending area on the substrate is located within the range of the orthographic projection of the second buffer zone on the substrate.

[0051] In an exemplary embodiment, along the direction from the display area to the first border area: the distance between the boundary of the first protective structure near the bend area and the first boundary is less than the size of the first buffer; the distance between the boundary of the second protective structure near the bend area and the second boundary is less than the size of the second buffer.

[0052] In an exemplary embodiment, the size of the first buffer is 20 micrometers to 100 micrometers along the direction from the display area to the first border area, and the size of the second buffer is 20 micrometers to 100 micrometers.

[0053] Secondly, this disclosure also provides a display device, including the display substrate described in any of the above embodiments.

[0054] The display substrate and display device provided in this embodiment include a display area and a first border area located on at least one side. A circuit structure layer and a protective structure layer are sequentially provided on one side of the substrate. The protective structure layer contains a protective structure. The first border area includes a bending area. In the bending area, an inorganic insulating layer in the circuit structure layer is removed to form a first bending opening. The orthographic projection of at least one boundary of the first bending opening on the substrate is covered by the orthographic projection of the protective structure on the substrate. Along the direction from the display area to the first border area, the protective structure and at least one boundary of the first bending opening are located on at least one side of the bending area. In the technical solution provided in this embodiment, the removal of the inorganic insulating layer in the circuit structure layer to form the first bending opening, and the orthographic projection of at least one boundary of the first bending opening on the substrate being covered by the orthographic projection of the protective structure on the substrate, can disperse the stress of the inorganic insulating layer in the circuit structure layer, and can solve the technical problem of film peeling or cracking near the bending area to a certain extent.

[0055] After reading and understanding the accompanying diagrams and detailed descriptions, the other aspects can be understood. Attached Figure Description

[0056] The accompanying drawings are provided to further illustrate the technical solutions of this disclosure and form part of the specification. They are used together with the embodiments of this disclosure to explain the technical solutions of this disclosure and do not constitute a limitation on the technical solutions of this disclosure. The shapes and sizes of the components in the drawings do not reflect actual proportions and are only intended to illustrate the content of this disclosure.

[0057] Figure 1 The diagram shown is a structural schematic of a display device;

[0058] Figure 2a The diagram shown is a schematic diagram of the structure of a display substrate;

[0059] Figure 2b The diagram shown is a schematic diagram of the structure of a display substrate;

[0060] Figure 3 The diagram shown is a schematic diagram of the first border area of ​​a display substrate;

[0061] Figure 4 The above is a schematic diagram of the structure of a display substrate;

[0062] Figure 5a The above is Figure 2a and Figure 2b A schematic diagram of a cross-sectional structure along the a0-a0 position in the middle;

[0063] Figure 5b The above is Figure 2a and Figure 2b A schematic diagram of a cross-sectional structure along the a0-a0 position in the middle;

[0064] Figure 6a This is an exemplary embodiment of the present disclosure. Figure 2a A schematic diagram of a cross-sectional structure along the midline at position u1-u1;

[0065] Figure 6b This is an exemplary embodiment of the present disclosure. Figure 2a A schematic diagram of a cross-sectional structure along the midline at position u1-u1;

[0066] Figure 6c This is an exemplary embodiment of the present disclosure. Figure 2a A schematic diagram of a cross-sectional structure along the midline at position u1-u1;

[0067] Figure 6d This is an exemplary embodiment of the present disclosure. Figure 2a A schematic diagram of a cross-sectional structure along the midline at position u1-u1;

[0068] Figure 6e This is an exemplary embodiment of the present disclosure. Figure 2a A schematic diagram of a cross-sectional structure along the midline at position u1-u1;

[0069] Figure 6f This is an exemplary embodiment of the present disclosure. Figure 2a A schematic diagram of a cross-sectional structure along the midline at position u1-u1;

[0070] Figure 6g This is an exemplary embodiment of the present disclosure. Figure 2a A schematic diagram of a cross-sectional structure along the midline at position u1-u1;

[0071] Figure 6h This is an exemplary embodiment of the present disclosure. Figure 2a A schematic diagram of a cross-sectional structure along the midline at position u1-u1;

[0072] Figure 6i This is an exemplary embodiment of the present disclosure. Figure 2a A schematic diagram of a cross-sectional structure along the midline at position u1-u1;

[0073] Figure 6j This is an exemplary embodiment of the present disclosure. Figure 2a A schematic diagram of a cross-sectional structure along the a1-a1 position in the middle;

[0074] Figure 7 for Figure 2a A schematic diagram of a cross-sectional structure along the midline at position u1-u1;

[0075] Figure 8 for Figure 2a A schematic diagram of a cross-sectional structure along the a1-a1 position in the middle;

[0076] Figure 9The diagram shown is a schematic diagram of a display device provided in an embodiment of this disclosure. Detailed Implementation

[0077] The technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this disclosure, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.

[0078] It is understood that the various figures in the embodiments of this disclosure are only used to schematically show the connection relationship between the various components. The dimensions of the various components in the figures are not drawn to scale, and their relative positional relationship may not completely correspond to the actual position.

[0079] In this disclosure, unless otherwise expressly specified and limited, the terms "installation," "connection," "joining," and "fixing," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this disclosure according to the specific circumstances.

[0080] In this disclosure, "electrical connection" includes the situation where components are connected together by a component having a certain electrical function. There are no particular limitations on the term "component having a certain electrical function," as long as it enables the transmission and reception of electrical signals between the connected components. Examples of "components having a certain electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other components with various functions.

[0081] In this disclosure, the terms "film" and "layer" can be interchanged. For example, sometimes "conductive layer" can be replaced with "conductive film". Similarly, sometimes "insulating film" can be replaced with "insulating layer".

[0082] The "patterning process" as described in this disclosure includes processes such as depositing a film layer, coating photoresist, mask exposure, development, etching, and photoresist stripping. Deposition can be performed using any one or more methods selected from sputtering, evaporation, and chemical vapor deposition; coating can be performed using any one or more methods selected from spraying and spin coating; and etching can be performed using any one or more methods selected from dry etching and wet etching. A "thin film" refers to a thin film of a certain material fabricated on a substrate (which may be called a substrate) using a deposition or coating process. If the "thin film" does not require a patterning process during the entire fabrication process, it can also be called a "layer". If the "thin film" requires a patterning process during the entire fabrication process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern".

[0083] Figure 1The diagram shows a schematic of a display device. The display substrate may include a timing controller, a data signal driving circuit, a scan signal driving circuit, a light emission signal driving circuit, and a pixel array. The timing controller is connected to the data signal driving circuit, the scan signal driving circuit, and the light emission signal driving circuit. The data signal driving circuit is connected to multiple data signal lines (D1 to Dn), the scan signal driving circuit is connected to multiple scan signal lines (G1 to Gm), and the light emission signal driving circuit is connected to multiple light emission signal lines (E1 to Eo). The pixel array may include multiple sub-pixels Pxij, where i and j can be natural numbers. At least one sub-pixel Pxij may include a circuit unit and a light emission device connected to the circuit unit. The circuit unit may include a pixel driving circuit, which may be connected to the scan signal lines, the light emission signal lines, and the data signal lines (which may be referred to as data lines). In an exemplary embodiment, the timing controller can provide grayscale values ​​and control signals of specifications suitable for the data signal driving circuit to the data signal driving circuit, clock signals, scan start signals, etc. of specifications suitable for the scan signal driving circuit to the scan signal driving circuit, and clock signals, transmit stop signals, etc. of specifications suitable for the light emission signal driving circuit to the light emission signal driving circuit. The data signal driving circuit can use the grayscale values ​​and control signals received from the timing controller to generate data voltages to be provided to data signal lines D1, D2, D3, ..., Dn. For example, the data signal driving circuit can sample the grayscale values ​​using a clock signal and apply the data voltage corresponding to the grayscale value to data signal lines D1 to Dn on a pixel-by-pixel basis, where n can be a natural number. The scan signal driving circuit can generate scan signals to be provided to scan signal lines G1, G2, G3, ..., Gm by receiving clock signals, scan start signals, etc., from the timing controller. For example, the scan signal driving circuit can sequentially provide scan signals with conduction level pulses to scan signal lines G1 to Gm. For example, the scan signal driving circuit can be configured as a shift register and can generate scan signals by sequentially transmitting scan start signals, provided in the form of on-level pulses, to the next stage circuit under the control of a clock signal, where m can be a natural number. The light emission signal driving circuit can generate transmit signals to be provided to the light emission signal lines E1, E2, E3, ..., Eo by receiving clock signals, transmit stop signals, etc., from a timing controller. For example, the light emission signal driving circuit can sequentially provide transmit signals with cutoff level pulses to the light emission signal lines E1 to Eo. For example, the light emission driver can be configured as a shift register and can generate transmit signals by sequentially transmitting transmit stop signals, provided in the form of cutoff level pulses, to the next stage circuit under the control of a clock signal, where o can be a natural number.

[0084] Figure 2aThe diagram shows a schematic representation of a display substrate. Figure 2a As shown, the display substrate may include a display area AA and a border area BB surrounding the display area AA. In some examples, the border area BB may include: a first border area (lower border) B1 and a second border area (upper border) B2 disposed opposite each other in the second direction Y, and a third border area (left border) B3 and a fourth border area (right border) B4 disposed opposite each other in the first direction X. The first border area B1 is connected to the third border area B3 and the fourth border area B4, and the second border area B2 is connected to the third border area B3 and the fourth border area B4. In some examples, the display area AA may include a plurality of regularly arranged sub-pixels Pxij, a plurality of gate control signal lines SL, and a plurality of data lines DL. The plurality of gate control signal lines SL may extend along the first direction X, and the plurality of data lines DL may extend along the second direction Y. The orthogonal projections of the plurality of gate control signal lines SL and the plurality of data lines DL on the substrate may intersect to form a plurality of sub-pixel areas, and a sub-pixel Pxij may be disposed in each sub-pixel area. Multiple data lines DL can be electrically connected to multiple sub-pixels Pxij, and the multiple data lines DL can be configured to provide data signals to the multiple sub-pixels Pxij. Multiple gate control signal lines SL can be electrically connected to multiple sub-pixels Pxij, and the multiple gate control signal lines SL can be configured to provide gate control signals to the multiple sub-pixels Pxij. In some examples, the gate control signals may include scan signals and emission control signals, or may include scan signals, reset control signals, and emission control signals. Sub-pixels Pxij may include pixel driving circuitry and light-emitting devices. The first frame region B1 may include bonding circuitry connecting the signal lines to an external driving device. The third frame region B3 and the fourth frame region B4 may include gate driving circuitry and a second power supply line VSS for transmitting voltage signals to the multiple sub-pixels.

[0085] Figure 3The diagram shows a planar structure of the first bezel region B1. In a plane parallel to the display substrate, the first bezel region B1 may include a first fan-out area 11, a bending area 12, a second fan-out area 13, an anti-static area 15, a third fan-out area 16, and a bonding area 14, arranged sequentially along a direction away from the display area AA. The bonding area 14 may include a driver chip area 141 and a bonding electrode area 142, arranged sequentially along a direction away from the bending area 12 from the second fan-out area 13. The first fan-out area 11 may include a data fan-out line, a first power line, and a second power line VSS. The data fan-out line is located in the middle of the first fan-out area 11 and includes multiple data connection lines configured to connect to the display area AA in a fan-out routing manner. The first power line is configured to connect to the display area AA as a high-voltage power line (VDD), and the second power line is a low-voltage power line (VSS) located in the third bezel region B3 and the fourth bezel region B4. The bending area 12 may include a composite insulating layer with grooves, configured to bend the bonding area 14 to the back of the display area AA (e.g., Figure 4As shown, the bending area 12 is equipped with data connection lines. One end of the data connection lines in the bending area 12 is connected to the data connection lines in the first fan-out area 11, and the other end is connected to the data connection lines in the second fan-out area 13. The second fan-out area 13 includes multiple data connection lines led out in a fan-out routing manner. The anti-static area 15 is equipped with multiple anti-static circuits 40, which are connected to the multiple data connection lines in the second fan-out area 13. The third fan-out area 16 includes multiple data output lines led out in a fan-out routing manner, which are connected to the multiple anti-static circuits 40 in the anti-static area 15. The driver chip area 141 can house an integrated circuit (IC) 20, configured to connect to multiple data output lines in the third fan-out area 16. The driver chip area 141 can also house multiple driver pads PA1 and multiple input pads PA2. Multiple input ports of the IC 20 can be electrically connected to multiple input pads PA2, and multiple output ports of the IC can be connected to multiple driver pads PA1. Input pads PA2 are used to input signals, which are converted by the IC 20 and output to the driver pads PA1. The driver pads PA1 transmit signals (such as data signals) to the corresponding data lines DL through corresponding data output lines and corresponding data connection lines. The bonding electrode area 142 includes multiple bonding pads configured to bond to a flexible printed circuit (FPC) 30. The bonding pads can also be electrically connected to corresponding input pads through multiple signal leads. Signals from the FPC can be transmitted to the integrated circuit 20 through the input pads. In an exemplary embodiment, an integrated circuit (IC) 20 can be bonded to the driver chip area 141, and a flexible printed circuit (FPC) 30 can be bonded to the bonding electrode area 142. In an exemplary embodiment, the integrated circuit 20 (which may be referred to as a data driving circuit) can generate driving signals required to drive sub-pixels and can provide these driving signals to the sub-pixel Pxij located in the display area AA. For example, the driving signal can be a data signal controlling the brightness of the sub-pixel. In an exemplary embodiment, the bonding electrode area 142 can be provided with bonding pads (PADs) PA3 including multiple pins, and the flexible printed circuit board 30 can be bonded to the pads.

[0086] In an exemplary implementation, such as Figure 4As shown, the bending region 12 can reverse the surface of the bonding region 14, that is, the upward-facing surface of the bonding region 14 can be transformed to face downward by bending the bending region 12. In an exemplary embodiment, when the bending region 12 is bent, the bonding region 14 can overlap with the display region AA in the thickness direction of the display substrate.

[0087] In an exemplary implementation, such as Figure 2b The diagram shown is a structural schematic of another type of display substrate. Figure 2b and Figure 2a The difference is that, Figure 2b The bending area 12 is not provided, so the binding area 14 cannot be bent to the back of the display area AA. Other structures are the same as... Figure 2b The same. In an exemplary embodiment, Figure 2a and Figure 2b The integrated circuit 20 is bonded to the first frame area B1. This structure can be called a COP (Chip on Panel) structure. The integrated circuit 20 can also be bonded to the flexible circuit board 30, which can reduce the size of the first frame area B1. This structure can be called a chip-on-flex film (COF).

[0088] In exemplary embodiments, for large-size display substrates, multiple data driver ICs (also known as driver ICs or driver integrated circuits) and multiple FPCs can be provided. The multiple FPCs are respectively bound to and connected to the multiple data driver ICs. For example, four data driver ICs can be provided, each bound to one of the four FPCs. This disclosure is not limited to four ICs and four FPCs; for example, two data driver ICs and two FPCs can be provided. For small-size display substrates, one or two data driver ICs can be provided. In this disclosure, the number of data driver ICs and FPCs can be set according to the size and functional requirements of the display substrate, and this disclosure does not limit this number.

[0089] Figure 5a for Figure 2a and Figure 2b The diagram shows a cross-sectional view of a sub-pixel Pxij taken along the a0-a0 position in the display area AA of the display substrate. Figure 5a The diagram illustrates the structure of a sub-pixel within the display area. This example uses multiple transistors of the same type in the pixel circuit; for instance, these transistors could all be low-temperature polysilicon thin-film transistors (LTPS) or oxide thin-film transistors (OPS). Figure 5a As shown. In other examples, the multiple transistors in the pixel circuit can be low-temperature polycrystalline silicon thin-film transistors and oxide thin-film transistors, such as... Figure 5bAs shown. Furthermore, this example illustrates a display substrate integrating a mutual capacitance touch structure to form an FMLOC structure.

[0090] In some examples, such as Figure 5a As shown, in the direction Z perpendicular to the plane of the display substrate, the display area of ​​the display substrate may include: a substrate 100 and a circuit structure layer 200, a light-emitting structure layer 300, an encapsulation structure layer 400, a touch structure layer 500, and a color filter layer 600 sequentially disposed on the substrate 100. The display structure layer may include at least the circuit structure layer 200 and the light-emitting structure layer 300. The circuit structure layer 200 may include at least pixel circuits for multiple sub-pixels, and each sub-pixel's pixel circuit may include multiple transistors and at least one capacitor. The light-emitting structure layer 300 may include at least light-emitting elements for multiple sub-pixels.

[0091] In some examples, Figure 5aThe illustration uses an example where each sub-pixel includes a thin-film transistor 21 and a capacitor 22. In some examples, the circuit structure layer 200 of the display area may include: a semiconductor layer, a first gate metal layer, a second gate metal layer, a first source-drain metal layer, a second source-drain metal layer, and a third source-drain metal layer disposed on the substrate 100. The multiple display area metal layers of the display structure layer in this example may include: a first gate metal layer, a second gate metal layer, a first source-drain metal layer, a second source-drain metal layer, and a third source-drain metal layer. A first gate insulating layer 201 may be disposed between the semiconductor layer and the first gate metal layer; a second gate insulating layer 202 may be disposed between the first gate metal layer and the second gate metal layer; an interlayer insulating layer 203 may be disposed between the second gate metal layer and the first source-drain metal layer; a passivation layer 204 and a first planarization layer 205 may be disposed between the first source-drain metal layer and the second source-drain metal layer; a second planarization layer 206 may be disposed between the second source-drain metal layer and the third source-drain metal layer; and a third planarization layer 207 may be disposed on the side of the third source-drain metal layer away from the substrate 100. The first gate insulating layer 201, the second gate insulating layer 202, the interlayer insulating layer 203, and the passivation layer 204 may be inorganic insulating layers, while the first planarization layer 205, the second planarization layer 206, and the third planarization layer 207 may be organic insulating layers. However, this embodiment is not limited to these limitations. In some examples, a buffer layer 1501 may be disposed on the side of the semiconductor layer near the substrate. The buffer layer 1501 can prevent harmful substances in the substrate from penetrating the interior of the display substrate and can also increase the adhesion of the film layers in the display substrate to the substrate. In some examples, a bottom shielding metal layer (BSM) may be disposed on the side of the buffer layer 1501 near the substrate. The bottom shielding metal layer BSM can be configured to at least partially cover the active layer of the thin-film transistor of the pixel circuit to prevent external light from affecting the performance of the thin-film transistor. In some examples, a passivation layer may be omitted between the first source-drain metal layer and the second source-drain metal layer, and only a first planarization layer may be disposed between the first source-drain metal layer and the second source-drain metal layer.

[0092] In some examples, such as Figure 5aAs shown, the semiconductor layer of the display area may include at least the active layer 210 of the thin-film transistor 21. The active layer 210 of the thin-film transistor 21 may include a first region 2101, a second region 2102, and a channel region 2100 located between the first region 2101 and the second region 2102. The first gate metal layer may include at least the gate 213 of the thin-film transistor 21 and the first electrode 221 of the capacitor 22. The orthographic projection of the gate 213 of the thin-film transistor 21 onto the substrate 100 may cover the orthographic projection of the channel region 2100 of the active layer 210 onto the substrate 100. The second gate metal layer may include at least the second electrode 222 of the capacitor 22. The orthographic projections of the second electrode 222 and the first electrode 221 of the capacitor 22 onto the substrate 100 may at least partially overlap, for example, they may coincide. The first source-drain metal layer may include at least the source 211 and the drain 212 of the thin-film transistor 21. The interlayer insulating layer 203 may have multiple vias (e.g., including a first pixel via and a second pixel via) in the display area. The interlayer insulating layer 203, the second gate insulating layer 202, and the first gate insulating layer 201 within the first pixel via can be removed, exposing at least a portion of the surface of the first region 2101 of the active layer 210. The interlayer insulating layer 203, the second gate insulating layer 202, and the first gate insulating layer 201 within the second pixel via can be removed, exposing at least a portion of the surface of the second region 2102 of the active layer 210. The source 211 of the thin-film transistor 21 can be electrically connected to the first region 2101 of the active layer 210 through the first pixel via, and the drain 212 can be electrically connected to the second region 2102 of the active layer 210 through the second pixel via. The second source-drain metal layer may include at least a first transition electrode 231. The first transition electrode 231 can be electrically connected to the drain 212 of the thin-film transistor 21 of the pixel circuit through a third pixel via formed by the passivation layer 204 and the first planarization layer 205. The third source-drain metal layer may include at least a second transition electrode 232. The second transition electrode 232 can be electrically connected to the first transition electrode 231 located in the second source-drain metal layer through a fourth pixel via formed by the second planarization layer 206. The second transition electrode 232 can be electrically connected to the first electrode 301 (e.g., anode) of the light-emitting element through a fifth pixel via formed by the third planarization layer 207. In this example, the electrical connection between the pixel circuit and the light-emitting element can be achieved through the first transition electrode 231 and the second transition electrode 232.

[0093] In some examples, the gate lines of the display area may be located, for example, in the first gate metal layer or the second gate metal layer; the data lines of the display area may be located, for example, in the second source-drain metal layer or the third source-drain metal layer; and the high-potential power lines (first power lines) of the display area may be located, for example, in at least one of the second and third source-drain metal layers. This embodiment is not limited in this respect. The circuit structure layer of this example may include three source-drain metal layers, which can avoid arranging too many traces in a single source-drain metal layer, thereby facilitating the realization of a narrow bezel structure.

[0094] In some examples, such as Figure 5a As shown, the light-emitting structure layer 300 may include a pixel definition layer 304 and multiple light-emitting elements. For example, each light-emitting element may include a stacked first electrode 301, an organic light-emitting layer 302, and a second electrode 303. The first electrode 301 of the light-emitting element can be an anode, and the first electrode 301 can be disposed on a third planarization layer 207 and electrically connected to a second transition electrode 232 through a fifth pixel via formed in the third planarization layer 207. The pixel definition layer 304 is disposed on the first electrode 301 and the third planarization layer 207, and the pixel definition layer 304 may have multiple pixel openings, one pixel opening exposing at least a portion of the surface of a corresponding first electrode 301. At least a portion of the organic light-emitting layer 302 can be disposed within a pixel opening and connected to the corresponding first electrode 301. The second electrode 303 can be disposed on the organic light-emitting layer 302 and connected to the organic light-emitting layer 302. The organic light-emitting layer 302 can emit light of a corresponding color under the drive of the first electrode 301 and the second electrode 303. An isolation pillar layer may also be provided on the side of the pixel definition layer 304 away from the substrate 100, and the isolation pillar layer may include multiple isolation pillars (PS).

[0095] In some examples, the organic light-emitting layer 302 of the light-emitting element may include an emitting layer (EML) and one or more films selected from the following: a hole injection layer (HIL), a hole transport layer (HTL), a hole block layer (HBL), an electron block layer (EBL), an electron injection layer (EIL), and an electron transport layer (ETL). Under the voltage drive of the first electrode 301 and the second electrode 303, the light-emitting properties of the organic material can be utilized to emit light at the required grayscale.

[0096] In some examples, the light-emitting layers of different colored light-emitting elements can be different. For example, a red light-emitting element includes a red light-emitting layer, a green light-emitting element includes a green light-emitting layer, and a blue light-emitting element includes a blue light-emitting layer. To reduce process complexity and improve yield, the hole injection layer and hole transport layer on one side of the light-emitting layer can be common layers, as can the electron injection layer and electron transport layer on the other side. In some examples, any one or more of the hole injection layer, hole transport layer, electron injection layer, and electron transport layer can be fabricated in a single process (single vapor deposition process or single inkjet printing process), and isolation can be achieved through surface steps of the formed film layers or through surface treatment. For example, any one or more of the hole injection layer, hole transport layer, electron injection layer, and electron transport layer corresponding to adjacent sub-pixels can be isolated. In some examples, the organic light-emitting layer can be formed by vapor deposition using a fine metal mask (FMM) or an open mask, or by inkjet printing.

[0097] In some examples, such as Figure 5a As shown, in a direction perpendicular to the plane of the substrate, the encapsulation structure layer 400 may include a first encapsulation layer 401, a second encapsulation layer 402, and a third encapsulation layer 403 stacked together. The first encapsulation layer 401 and the third encapsulation layer 403 may be made of inorganic materials such as silicon nitride, silicon oxide, or silicon oxynitride. Inorganic materials have high density and can prevent the intrusion of water, oxygen, etc. The second encapsulation layer 402 may be disposed between the first encapsulation layer 401 and the third encapsulation layer 403 to ensure that external moisture cannot enter the light-emitting element. The second encapsulation layer 402 may be made of organic materials, for example, it may be a polymer material containing a desiccant or a polymer material that can block moisture, or it may be a polymer resin to planarize the surface of the display substrate and relieve stress on the first encapsulation layer 401 and the third encapsulation layer 403. It may also include a desiccant or other water-absorbing material to absorb water, oxygen, and other substances that have penetrated the interior. However, this embodiment is not limited to this. For example, the encapsulation structure layer may adopt a five-layer stacked structure of inorganic / organic / inorganic / organic / inorganic.

[0098] In some examples, the touch structure layer of the display area may include: a plurality of first touch electrodes, a plurality of first connecting portions, a plurality of second touch electrodes, and a plurality of second connecting portions. The plurality of first touch electrodes may be arranged in the same layer, and adjacent first touch electrodes may be connected through the first connecting portions. The plurality of second touch electrodes may be arranged in the same layer, and adjacent second touch electrodes may be connected through the second connecting portions.

[0099] In some examples, such as Figure 5aAs shown, in a direction perpendicular to the plane of the substrate, the touch structure layer 500 of the display area may include: a touch buffer layer (TBL) 501, a first touch conductive layer 511, a touch interlayer insulating layer (TLD) 502, and a second touch conductive layer 512, arranged sequentially. The touch buffer layer 501 and the touch interlayer insulating layer 502 can be inorganic insulating layers, such as SiNx layers. The first touch conductive layer 511 may include multiple first touch electrodes, multiple second touch electrodes, and multiple first connecting portions. The first touch electrodes and the first connecting portions can be an integral structure interconnected. The second touch conductive layer 512 may include multiple second connecting portions. The second connecting portions can be interconnected with adjacent second touch electrodes through vias formed in the touch interlayer insulating layer. However, this embodiment is not limited to this. In other examples, the first touch conductive layer may include: a plurality of first touch electrodes, a plurality of second touch electrodes, and a plurality of second connecting portions, wherein the second touch electrodes and the second connecting portions may be an integral structure interconnected with each other; the second touch conductive layer may include a plurality of first connecting portions, which may be interconnected with adjacent first touch electrodes through vias formed in the interlayer insulating layer. In some examples, the first touch electrodes may be driving (Tx) electrodes, and the second touch electrodes may be sensing (Rx) electrodes. Alternatively, the first touch electrodes may be sensing (Rx) electrodes, and the second touch electrodes may be driving (Tx) electrodes. This embodiment is not limited in this respect.

[0100] In some examples, the first and second touch electrodes may be rhomboid in shape, such as a regular rhombus, a horizontally elongated rhombus, or a vertically elongated rhombus. In other examples, the first and second touch electrodes may be any one or more of triangles, squares, trapezoids, parallelograms, pentagons, hexagons, and other polygons, which are not limited to the embodiments disclosed herein.

[0101] In some examples, the first and second touch electrodes can be in the form of transparent conductive electrodes. In other examples, the first and second touch electrodes can be in the form of a metal mesh, which can be formed by multiple interwoven metal wires. The metal mesh can include multiple mesh patterns, and the mesh pattern can be a polygon composed of multiple metal wires. The metal mesh-type first and second touch electrodes have advantages such as low resistance, small thickness, and fast response speed.

[0102] In some examples, such as Figure 5aAs shown, in a direction perpendicular to the plane of the substrate, the color filter on encapsulation (COE) 600 may include an insulating layer 601, a color filter layer, and an overcoat 602 disposed sequentially. The color filter layer includes a black matrix 610 and color filter units 611 disposed between the black matrix 610. The color filter units 611 may be, for example, red filter units, green filter units, or blue filter units.

[0103] In some examples, such as Figure 5b As shown, Figure 2a and Figure 2b The diagram shows a cross-sectional view of a sub-pixel Pxij taken along position a0-a0 in the display area AA of the display substrate. In the direction Z perpendicular to the display substrate, the display area may include: a substrate 100 and a circuit structure layer 200, a light-emitting structure layer 300, an encapsulation structure layer 400, and a touch structure layer 500 sequentially disposed on the substrate 100. The display structure layer may include at least the circuit structure layer 200 and the light-emitting structure layer 300. The circuit structure layer 200 may include at least pixel circuits for multiple sub-pixels, each sub-pixel's pixel circuit including multiple transistors and at least one capacitor. The light-emitting structure layer 300 may include at least light-emitting elements for multiple sub-pixels.

[0104] In some examples, Figure 5b The illustration uses an example where each sub-pixel includes a first transistor 21, a second transistor 23, and a capacitor 22. The transistor types of the first transistor 21 and the second transistor 23 can be different. Specifically, the first transistor 21 can be a low-temperature polycrystalline silicon thin-film transistor, and the second transistor 23 can be an oxide thin-film transistor.

[0105] In some examples, the circuit structure layer 200 of the display area may include: a first semiconductor layer, a first gate metal layer, a second gate metal layer, a second semiconductor layer, a third gate metal layer, a first source / drain metal layer, and a second source / drain metal layer disposed on the substrate 100. In this example, the multiple display area metal layers of the display structure layer may include: a first gate metal layer, a second gate metal layer, a third gate metal layer, a first source / drain metal layer, and a second source / drain metal layer. A first gate insulating (GI) layer 201 may be disposed between the first semiconductor layer and the first gate metal layer, and a second gate insulating layer 202 may be disposed between the first gate metal layer and the second gate metal layer; a first interlayer insulating (ILD) layer 103 and a first buffer layer 104 may be disposed between the second gate metal layer and the second semiconductor layer, and the first buffer layer 104 may be located on the side of the first interlayer insulating layer 103 away from the substrate 100; a third gate insulating layer 105 may be disposed between the second semiconductor layer and the third gate metal layer; a second interlayer insulating layer 106 may be disposed between the third gate metal layer and the first source / drain metal layer; a passivation (PVX) layer 204 and a first planarization (PLN) layer 205 may be disposed between the first source / drain metal layer and the second source / drain metal layer, and the first planarization layer 205 may be located on the side of the passivation layer 204 away from the substrate 100; a second planarization layer 206 may be disposed on the side of the second source / drain metal layer away from the substrate 100. In this embodiment, the first gate insulating layer 201, the second gate insulating layer 202, the first interlayer insulating layer 103, the first buffer layer 104, the third gate insulating layer 105, the second interlayer insulating layer 106, and the passivation layer 204 can be inorganic insulating layers, while the first planarization layer 205 and the second planarization layer 206 can be organic insulating layers. However, this embodiment is not limited in this respect. In some other examples, a buffer layer 1501 can also be provided on the side of the first semiconductor layer near the substrate. The buffer layer 1501 can prevent harmful substances in the substrate from penetrating into the interior of the display substrate and can also increase the adhesion of the film layers in the display substrate to the substrate. In some other examples, a bottom Shielding Metal (BSM) can also be provided on the side of the buffer layer 1501 near the substrate. The bottom Shielding Metal (BSM) can be configured to at least partially cover the active layer of the transistors in the pixel circuit to avoid external light affecting the performance of the transistors. In other examples, the passivation layer between the first source / drain metal layer and the second source / drain metal layer may be omitted, and only a first planarization layer may be provided between the first source / drain metal layer and the second source / drain metal layer. In still other examples, the first buffer layer between the second gate metal layer and the second semiconductor layer may be omitted, and only a first interlayer insulating layer 103 may be provided.

[0106] In some examples, such as Figure 5bAs shown, the first semiconductor layer of the display area may include at least: a first active layer 210 of the first transistor 21. The first active layer 210 of the first transistor 21 may include: a first region 2101, a second region 2102, and a channel region 2100 located between the first region 2101 and the second region 2102. The first gate metal layer may include at least: a first gate 213 of the first transistor 21 and a first electrode 221 of the capacitor 22. The orthographic projection of the first gate 213 of the first transistor 21 onto the substrate 100 may cover the orthographic projection of the channel region 2100 of the first active layer 210 onto the substrate 100. The second gate metal layer may include at least: a second electrode 222 of the capacitor 22 and a third gate 234 of the second transistor 23. The orthographic projections of the second electrode 222 and the first electrode 221 of the capacitor 22 onto the substrate 100 may at least partially overlap, for example, they may coincide. The second semiconductor layer may include at least: a second active layer 230 of the second transistor 23. The third gate metal layer may include at least: the second gate 233 of the second transistor 23. The orthographic projection of the second gate 233 of the second transistor 23 onto the substrate 100 may partially overlap with the orthographic projection of the second active layer 230 onto the substrate 100. The orthographic projection of the third gate 234 of the second transistor 23 onto the substrate 100 may partially overlap with the orthographic projection of the second active layer 230 onto the substrate 100. The third gate 234 may be the bottom gate of the second transistor 23, and the second gate 233 may be the top gate of the second transistor 23.

[0107] In some examples, such as Figure 5bAs shown, the first source-drain metal layer may include at least: a first source 211 and a first drain 212 of the first transistor 21, and a second source 235 and a second drain 236 of the second transistor 23. The second interlayer insulating layer 106 may have multiple pixel vias (e.g., including a first pixel via, a second pixel via, a third pixel via, and a fourth pixel via) in the display area. The second interlayer insulating layer 106, the third gate insulating layer 105, the first buffer layer 104, the first interlayer insulating layer 103, the second gate insulating layer 202, and the first gate insulating layer 201 within the first pixel via can be removed, exposing at least a portion of the surface of the first region 2101 of the first active layer 210; the second interlayer insulating layer 106, the third gate insulating layer 105, the first buffer layer 104, the first interlayer insulating layer 103, the second gate insulating layer 202, and the first gate insulating layer 201 within the second pixel via can be removed, exposing at least a portion of the surface of the second region 2102 of the first active layer 210. The second interlayer insulating layer 106 and the third gate insulating layer 105 within the third and fourth pixel vias can be removed, exposing at least a portion of the surface at both ends of the second active layer 230. The first source 211 of the first transistor 21 can be electrically connected to the first region 2101 of the first active layer 210 through the first pixel via, and the first drain 212 can be electrically connected to the second region 2102 of the first active layer 210 through the second pixel via. The second source 235 of the second transistor 23 can be electrically connected to one end of the second active layer 230 through the third pixel via, and the second drain 236 of the second transistor 23 can be electrically connected to the other end of the second active layer 230 through the fourth pixel via. The second source-drain metal layer may include at least a first transition electrode 231. The first transition electrode 231 can be electrically connected to the first drain 212 of the first transistor 21 of the pixel circuit through a fifth pixel via formed by the passivation layer 204 and the first planarization layer 205. In this example, the first transition electrode 231 can be used to achieve the electrical connection between the pixel circuit and the light-emitting element.

[0108] In some examples, the gate lines of the display area may be located, for example, on the first gate metal layer and the third gate metal layer; the data lines of the display area may be located, for example, on the second source-drain metal layer; and the high-potential power lines (first power lines) of the display area may be located, for example, on the second source-drain metal layer. This embodiment is not limited in this respect.

[0109] In some examples, such as Figure 5bAs shown, the light-emitting structure layer 300 may include a pixel definition layer 134 and multiple light-emitting elements. For example, each light-emitting element may include a stacked first electrode 301, an organic light-emitting layer 302, and a second electrode 303. The first electrode 301 of the light-emitting element can be an anode, and the first electrode 301 can be disposed on the second planarization layer 206 and electrically connected to the first transition electrode 231 through a sixth pixel via formed in the second planarization layer 206. The pixel definition layer 304 is disposed on the first electrode 301 and the second planarization layer 206, and the pixel definition layer 304 may have multiple pixel openings, one pixel opening exposing at least a portion of the surface of a corresponding first electrode 301. At least a portion of the organic light-emitting layer 302 can be disposed within a pixel opening and connected to the corresponding first electrode 301. The second electrode 303 can be disposed on the organic light-emitting layer 302 and connected to the organic light-emitting layer 302. The organic light-emitting layer 302 can emit light of a corresponding color under the drive of the first electrode 301 and the second electrode 303.

[0110] In some examples, the organic light-emitting layer 302 of the light-emitting element may include an emitting layer (EML) and one or more films selected from the following: a hole injection layer (HIL), a hole transport layer (HTL), a hole block layer (HBL), an electron block layer (EBL), an electron injection layer (EIL), and an electron transport layer (ETL). Under the voltage drive of the first electrode 301 and the second electrode 303, the light-emitting properties of the organic material can be utilized to emit light at the required grayscale.

[0111] In some examples, the light-emitting layers of different colored light-emitting elements can be different. For example, a red light-emitting element includes a red light-emitting layer, a green light-emitting element includes a green light-emitting layer, and a blue light-emitting element includes a blue light-emitting layer. To reduce process complexity and improve yield, the hole injection layer and hole transport layer on one side of the light-emitting layer can be common layers, as can the electron injection layer and electron transport layer on the other side. In some examples, any one or more of the hole injection layer, hole transport layer, electron injection layer, and electron transport layer can be fabricated in a single process (single vapor deposition process or single inkjet printing process), and isolation can be achieved through surface steps of the formed film layers or through surface treatment. For example, any one or more of the hole injection layer, hole transport layer, electron injection layer, and electron transport layer corresponding to adjacent sub-pixels can be isolated. In some examples, the organic light-emitting layer can be formed by vapor deposition using a fine metal mask (FMM) or an open mask, or by inkjet printing.

[0112] In some examples, such as Figure 5b As shown, the encapsulation structure layer 400 may include a first encapsulation layer 401, a second encapsulation layer 402, and a third encapsulation layer 403 stacked together. The first encapsulation layer 401 and the third encapsulation layer 403 may be made of inorganic materials, such as silicon nitride, silicon oxide, or silicon oxynitride. Inorganic materials have high density and can prevent the intrusion of water, oxygen, etc. The second encapsulation layer 402 may be disposed between the first encapsulation layer 401 and the third encapsulation layer 403 to ensure that external moisture cannot enter the light-emitting element. The second encapsulation layer 402 may be made of organic materials, for example, it may be a polymer material containing a desiccant or a polymer material that can block moisture, or it may be a polymer resin to planarize the surface of the display substrate and relieve stress on the first encapsulation layer 401 and the third encapsulation layer 403. It may also include a desiccant or other water-absorbing material to absorb water, oxygen, and other substances that have penetrated the interior. However, this embodiment is not limited to this. For example, the encapsulation structure layer may adopt a five-layer stacked structure of inorganic / organic / inorganic / organic / inorganic.

[0113] In some examples, the touch structure layer of the display area may include: a plurality of first touch electrodes, a plurality of first connecting portions, a plurality of second touch electrodes, and a plurality of second connecting portions. The plurality of first touch electrodes may be arranged in the same layer, and adjacent first touch electrodes may be connected through the first connecting portions. The plurality of second touch electrodes may be arranged in the same layer, and adjacent second touch electrodes may be connected through the second connecting portions.

[0114] In some examples, such as Figure 5bAs shown, in a direction perpendicular to the plane of the display substrate, the touch structure layer 500 of the display area may include: a touch buffer layer (TBL) 501, a first touch conductive layer (TMA) 511, a touch interlayer insulating layer (TLD) 502, a second touch conductive layer (TMB) 512, and a protective layer 503, arranged sequentially. The touch buffer layer 501 and the touch interlayer insulating layer 502 may be inorganic insulating layers, and the protective layer 503 may be an organic insulating layer. The first touch conductive layer 511 may include a plurality of first touch electrodes, a plurality of second touch electrodes, and a plurality of first connecting portions. The first touch electrodes and the first connecting portions may be an integral structure interconnected. The second touch conductive layer 512 may include a plurality of second connecting portions. The second connecting portions may be interconnected with adjacent second touch electrodes through vias formed in the touch interlayer insulating layer. However, this embodiment is not limited in this respect. In other examples, the first touch conductive layer may include: a plurality of first touch electrodes, a plurality of second touch electrodes, and a plurality of second connecting portions, wherein the second touch electrodes and the second connecting portions may be an integral structure interconnected with each other; the second touch conductive layer may include a plurality of first connecting portions, which may be interconnected with adjacent first touch electrodes through vias formed in the interlayer insulating layer. In some examples, the first touch electrodes may be driving (Tx) electrodes, and the second touch electrodes may be sensing (Rx) electrodes. Alternatively, the first touch electrodes may be sensing (Rx) electrodes, and the second touch electrodes may be driving (Tx) electrodes. This embodiment is not limited in this respect.

[0115] In some examples, the first and second touch electrodes may be rhomboid in shape, such as a regular rhombus, a horizontally elongated rhombus, or a vertically elongated rhombus. In other examples, the first and second touch electrodes may be any one or more of triangles, squares, trapezoids, parallelograms, pentagons, hexagons, and other polygons, which are not limited to the embodiments disclosed herein.

[0116] In some examples, the first and second touch electrodes can be in the form of transparent conductive electrodes. In other examples, the first and second touch electrodes can be in the form of a metal mesh, which can be formed by multiple interwoven metal wires. The metal mesh can include multiple mesh patterns, and the mesh pattern can be a polygon composed of multiple metal wires. The metal mesh-type first and second touch electrodes have advantages such as low resistance, small thickness, and fast response speed.

[0117] In an exemplary embodiment, at least one sub-pixel Pxij may include a pixel circuit (which may be referred to as a pixel driving circuit) and a light-emitting element. In the same sub-pixel Pxij, the light-emitting element is electrically connected to the pixel circuit and is configured to emit light under the drive of the pixel circuit.

[0118] exist Figure 2a The structure shown includes a bending region 12. The inorganic layer experiences significant stress, and part of the inorganic insulating layer within the bending region 12 needs to be removed. However, the boundary of the inorganic insulating layer is located near the bending region 12. In the direction from the display area AA to the first frame area B1, the boundary of the inorganic insulating layer lies on both sides of the bending region 12. The bending process of the bending region 12 still affects the boundary of the inorganic insulating layer. During bending, the inorganic insulating layer near the bending region 12 remains under stress and is prone to peeling. This also causes the metal film layer on the side of the inorganic insulating layer furthest from the substrate to easily peel off. (e.g., during bending, the inorganic insulating layer in the circuit structure layer 200 is easily detached due to stress, causing the metal signal lines on the side of the inorganic insulating layer away from the substrate to detach or crack. As the detachment and cracks extend, the metal film layer on the side of the inorganic insulating layer away from the substrate cannot transmit signals normally. In some cases, the encapsulation layer may fail due to damage to the metal film layer. Moisture will enter the organic layer along the metal traces in the damaged metal film layer and continue to extend to the display area, causing abnormal display in the display area.)

[0119] This disclosure provides a display substrate, which may include:

[0120] A substrate, the substrate including a display area and a first border area located on at least one side of the display area;

[0121] A circuit structure layer is located on one side of the substrate.

[0122] A protective structure layer is located on the side of the circuit structure layer away from the substrate, and the protective structure layer is provided with a first protective structure;

[0123] A bending area is located in the first frame area, in which the inorganic insulating layer in the circuit structure layer is removed to form a first bending opening;

[0124] Wherein, at least one boundary of the first bending opening is orthographically projected onto the substrate by the orthographically projected onto the substrate by the protective structure, and along the direction from the display area to the first border area, the protective structure and at least one boundary of the first bending opening are located on at least one side of the bending area.

[0125] The display substrate provided in this embodiment includes a display area and a first border area located on at least one side. A circuit structure layer and a protective structure layer are sequentially provided on one side of the substrate. The protective structure layer contains a protective structure. The first border area includes a bending area. In the bending area, an inorganic insulating layer in the circuit structure layer is removed to form a first bending opening. The orthographic projection of at least one boundary of the first bending opening onto the substrate is covered by the orthographic projection of the protective structure onto the substrate. Along the direction from the display area to the first border area, the protective structure and at least one boundary of the first bending opening are located on at least one side of the bending area. In the technical solution provided in this embodiment, the removal of the inorganic insulating layer in the circuit structure layer to form a first bending opening, and the orthographic projection of at least one boundary of the first bending opening onto the substrate being covered by the orthographic projection of the protective structure onto the substrate, can disperse the stress of the inorganic insulating layer in the circuit structure layer, and can solve the technical problem of film peeling or cracking near the bending area to a certain extent.

[0126] like Figure 2a , 6a to Figure 6i As shown, Figures 6a to 6i for Figure 2a Several cross-sectional structural diagrams at position u1-u1 are shown. The display substrate provided in this embodiment may include:

[0127] The substrate 100 includes a display area AA and a first border area B1 located on at least one side of the display area AA.

[0128] The circuit structure layer 200 is located on one side of the substrate 100;

[0129] The protective structure layer 700 is located on the side of the circuit structure layer 200 away from the substrate 100, and the protective structure layer 700 is provided with a protective structure 07.

[0130] The bending area 12 is located in the first border area B1. In the bending area 12, the inorganic insulating layer 20 in the circuit structure layer 200 is removed to form the first bending opening V1.

[0131] Wherein, the orthographic projection of at least one boundary BL of the first bending opening V1 on the substrate 100 is covered by the orthographic projection of the protective structure 07 on the substrate 100. Along the direction Y from the display area AA to the first border area B1, the protective structure 07 and at least one boundary BL of the first bending opening V1 are located on at least one side of the bending area 12.

[0132] In an exemplary embodiment, the orthographic projection of the protective structure 07 in the protective structure layer 700 onto the substrate 100 covers the orthographic projection of at least one boundary BL of the first bending opening V1 onto the substrate 100. This can disperse the stress of the inorganic insulating layer 20 in the circuit structure layer 200 and can solve the technical problem of film peeling or cracking near the bending area to a certain extent.

[0133] In an exemplary implementation, such as Figures 6a to 6i As shown, the protective structure 07 may include a first protective structure 71 and a second protective structure 72, and at least one boundary of the first bent opening V1 may include a first boundary BL1 and a second boundary BL2.

[0134] Along the direction Y from the display area AA to the first border area B1, the first protective structure 71 and the first boundary BL1 can be located on the side of the bending area 12 closer to the display area AA, and the second protective structure 72 and the second boundary BL2 can be located on the side of the bending area 12 away from the display area AA.

[0135] The orthographic projection of the first boundary BL1 onto the substrate 100 is covered by the orthographic projection of the first protective structure 71 onto the substrate 100; the orthographic projection of the second boundary BL2 onto the substrate is covered by the orthographic projection of the second protective structure 72 onto the substrate 100.

[0136] In an exemplary implementation, such as Figures 6a to 6i As shown, the protective structure layer 700 includes at least a touch structure layer 500, which may include a touch planarization layer 503. In the direction Z perpendicular to the plane of the substrate 100, the touch planarization layer 503 is located in the touch structure layer 500 that is furthest from the circuit structure layer 200. At least a portion of the structure of the protective structure 07 may be located in the touch planarization layer 503.

[0137] In an exemplary implementation, such as Figures 6a to 6i As shown, the protective structure layer 700 may further include a first protective layer 701, which may be located on the side of the touch planarization layer 503 away from the substrate 100 in the direction Z perpendicular to the plane of the substrate 100.

[0138] The touch planarization layer 503 may include a first region 5031, a second region 5032, and at least one blocking structure Dam. The blocking structure Dam may be located in the first border region B1. The first region 5031 of the touch planarization layer 503 and the first protective layer 701 form a cover layer 70. The cover layer 70 is located in the display region AA and extends to the first border region B1 in the direction Y from the display region AA to the first border region B1. The cover layer 70 may be located on the side of at least one blocking structure Dam away from the bending region 12. The second region 5032 of the touch planarization layer 503 may be located on the side of the bending region 12 away from the display region AA. The second protective structure 72 includes at least the second region 5032 of the touch planarization layer 503.

[0139] In an exemplary implementation, such as Figures 6a to 6e As shown, at least one blocking structure Dam may include a first blocking structure Dam1 and a second blocking structure Dam2, along the direction Y from the display area AA to the first border area B1. The first blocking structure Dam1 may be located on the side of the second blocking structure Dam2 away from the display area AA.

[0140] like Figure 6a As shown, the orthographic projection of the first blocking structure Dam1 on the substrate 100 can cover the orthographic projection of the first boundary BL1 on the substrate 100, and the first protective structure 71 may include the first blocking structure Dam1; or, as Figures 6b to 6e As shown, the orthographic projection of the second blocking structure Dam2 on the substrate 100 can cover the orthographic projection of the first boundary BL1 on the substrate 100, and the first protection structure 71 may include the second blocking structure Dam2.

[0141] In an exemplary embodiment, the direction Y along the display area AA pointing to the first border area B1 is as follows: Figure 6a As shown, in a structure where the orthographic projection of the first blocking structure Dam1 on the substrate 100 covers the orthographic projection of the first boundary BL1 on the substrate 100, the size of the first blocking structure Dam1 is larger than the size of the second blocking structure Dam2; as Figures 6b to 6e As shown, in a structure in which the orthographic projection of the second blocking structure Dam2 on the substrate 100 covers the orthographic projection of the first boundary BL1 on the substrate 100, the size of the first blocking structure Dam1 is smaller than the size of the second blocking structure Dam2.

[0142] In an exemplary implementation, such as Figures 6f to 6iAs shown, at least one blocking structure Dam may include a first blocking structure Dam1, along the direction Y from the display area AA to the first border area B1. The edge of the cover layer 70 near the bending area 12 is located between the first boundary BL1 and the first blocking structure Dam1. The orthographic projection of the first boundary BL1 on the substrate 100 is within the range of the orthographic projection of the cover layer 70 on the substrate 100. The first protective structure 71 may include the cover layer 70. Figures 6f to 6i In the structure shown, the cover layer 70 serves two purposes: firstly, it disperses the stress at the first boundary BL1, preventing the film layer near the bending area 12 from peeling off or cracking during bending; secondly, it provides encapsulation and protection for the display substrate. Figures 6f to 6i In the structure shown, the first boundary BL1 is protected by the first protective layer 701 in the cover layer 70 and the first region 5031 of the touch flat layer 503, which can better disperse the stress near the first boundary BL1.

[0143] In an exemplary implementation, such as Figures 6a to 6i As shown, in the first border area B1, along the direction Y from the display area AA to the first border area B1, the boundary of the first protective layer 701 on the side away from the display area AA is located between the boundary of the first area 5031 of the touch flat layer 503 on the side away from the display area AA and at least one blocking structure Dam.

[0144] In an exemplary embodiment, the first protective layer 701 can be fabricated using inkjet printing (IJP). During the fabrication of the first protective layer 701, at least one barrier structure, Dam, can block the flow of the first protective layer 701. Figure 5a and Figure 5b The encapsulation structure layer 400 mainly encapsulates the display area AA, while the first protective layer 701 can encapsulate the entire display substrate.

[0145] In an exemplary implementation, such as Figures 6a to 6i As shown, along the direction Y from the display area AA to the first border area B1, the second boundary BL2 can be located between the second area 5032 of the touch planarization layer 503 and the bending area 12. The orthographic projection of the second boundary BL2 on the substrate 100 can be located within the range of the orthographic projection of the second area 5032 of the touch planarization layer 503 on the substrate 100. The second boundary BL2 of the first bending opening V1 is covered by the second area 5032 of the touch planarization layer 503, which can disperse the stress of the second boundary BL2 and reduce the risk of film peeling or cracking near the bending area 12.

[0146] In an exemplary implementation, such as Figures 6a to 6iAs shown, the protective structure layer 700 includes at least a touch structure layer 500. The touch structure layer 500 may include at least one first signal connection line L1 and a touch inorganic insulating layer 50. In the direction Z perpendicular to the plane of the substrate 100, the touch inorganic insulating layer 50 may be located on the side of the first signal connection line L1 close to the substrate 100.

[0147] like Figures 6c to 6e , Figures 6g to 6i As shown, the protective structure 07 may include at least one of the first signal connection line L1 and the touch inorganic insulating layer 50. Based on the touch planarization layer 503, the protective structure 07 adds at least one of the first signal connection line L1 and the touch inorganic insulating layer 50, enabling the protective structure 07 to better disperse the stress generated in the bending area 12 during bending, and to better prevent the film layer near the bending area 12 from peeling off or cracking.

[0148] In an exemplary implementation, such as Figures 6a to 6i As shown, the touch structure layer 500 may also include a touch planarization layer 503. In the direction Z perpendicular to the plane of the substrate 100, the touch planarization layer 503 may be located on the side of the first signal connection line L1 away from the substrate 100, and at least a part of the structure of the protection structure 71 may be located in the touch planarization layer 503.

[0149] Along the direction Y from the display area AA to the first border area B1, in the protective structure 07 on the same side of the bending area 12: the orthographic projection of the structure of the touch planarization layer 503 on the substrate 100 covers the orthographic projection of the structure of the touch inorganic insulating layer 50 on the substrate 100, and covers the orthographic projection of the first signal connection line L1 on the substrate 100.

[0150] In an exemplary embodiment, the orthographic projection of the protective structure 07 on the touch planarization layer 503 onto the substrate 100 covers the orthographic projection of the protective structure 07 on the touch inorganic insulating layer 50 onto the substrate 100, which can alleviate the stress at the boundary of the touch inorganic insulating layer 50 near the bending region 12. The orthographic projection of the protective structure 07 on the touch planarization layer 503 onto the substrate 100 also covers the orthographic projection of the first signal connection line L1 onto the substrate 100, thus protecting the first signal connection line L1 and preventing it from being corroded in subsequent fabrication processes.

[0151] In an exemplary implementation, such as Figures 6d to 6e , Figures 6h to 6iAs shown, in the structure of the first protection structure 71 including the first signal connection line L1, along the direction Y from the display area AA to the first frame area B1, the first signal connection line L1 in the first protection structure 71 is located on the side of the bending area 12 close to the display area AA, and the two ends of the first signal connection line L1 in the first protection structure 71 are located on both sides of the first boundary BL1. The first signal connection line L1 in the first protection structure 71 and the orthographic projection of the first boundary BL1 on the substrate 100 at least partially overlap, so that the first signal connection line L1 in the first protection structure 71 can cover at least part of the first boundary BL1, thereby relieving the stress of the first boundary BL1 and reducing the risk of film peeling or cracking near the first boundary BL1.

[0152] In an exemplary implementation, such as Figures 6d to 6e , Figures 6h to 6i As shown, in the structure of the second protection structure 72 including the first signal connection line L1, along the direction Y from the display area AA to the first frame area B1: the first signal connection line L1 in the second protection structure 72 is located on the side of the bending area 12 away from the display area AA, and the two ends of the first signal connection line L1 in the second protection structure 72 are located on both sides of the second boundary BL2. The first signal connection line L1 in the second protection structure 72 and the orthographic projection of the second boundary BL2 on the substrate 100 at least partially overlap, so that the first signal connection line L1 in the second protection structure 72 can cover at least part of the second boundary BL2, thereby relieving the stress of the second boundary BL2 and reducing the risk of film peeling or cracking near the second boundary BL2.

[0153] In an exemplary implementation, such as Figures 6a to 6i As shown, the circuit structure layer 200 may further include at least one second signal connection line L2, at least a portion of the structure of the second signal connection line L2 is located in the bending region 12; the same second signal connection line L2 corresponds to two first signal connection lines L1. In the direction from the display area AA to the first border area B1, of the two first signal connection lines L1 corresponding to the same second signal connection line L2, one of the first signal connection lines L1 is located on the side of the bending region 12 closer to the display area AA, and the other first signal connection line L1 is located on the side of the bending region 12 away from the display area AA;

[0154] In the first border region B1, the touch inorganic insulating layer 50 may include a first opening K1 that exposes at least a portion of the structure of the second signal connection line L2, through which the first signal connection line L1 can be electrically connected to the corresponding second signal connection line L2.

[0155] In an exemplary implementation, such as Figures 6a to 6iAs shown, along the direction Y from the display area AA to the first border area B1, the first signal connection line L1 can be located at the center of the corresponding second signal connection line L2 on the side away from the bending area 12.

[0156] In an exemplary implementation, such as Figure 6c , Figure 6d , Figure 6g and Figure 6i As shown, along the direction Y from the display area AA to the first border area B1, on the side of the bending area 12 near the display area AA, the first opening K1 can be located on the side of the bending area 12 near the display area AA. In the structure of the first protective structure 71 including the touch inorganic insulating layer 50, the first protective structure 71 includes the touch inorganic insulating layer 50 located between the first opening K1 and the bending area 12. The orthographic projection of the touch inorganic insulating layer 50 in the first protective structure 71 on the substrate 100 covers the orthographic projection of the first boundary BL1 on the substrate 100, so that the touch inorganic insulating layer 50 in the first protective structure 71 can cover at least part of the first boundary BL1, thereby relieving the stress of the first boundary BL1 and reducing the risk of film peeling or cracking near the first boundary BL1.

[0157] In an exemplary implementation, such as Figure 6c , Figure 6d , Figure 6g and Figure 6i As shown, along the direction Y from the display area AA to the first border area B1, on the side of the bending area 12 away from the display area AA, the first opening K1 can be located on the side of the bending area 12 away from the display area AA. In the structure of the second protective structure 72 including the touch inorganic insulating layer 50, the second protective structure 72 can include the touch inorganic insulating layer 50 located between the first opening K1 and the bending area 12. The orthographic projection of the touch inorganic insulating layer 50 in the second protective structure 72 on the substrate 100 covers the orthographic projection of the second boundary BL2 on the substrate 100, so that the touch inorganic insulating layer 50 in the second protective structure 72 can cover at least part of the second boundary BL2, thereby relieving the stress of the second boundary BL2 and reducing the risk of film peeling or cracking near the second boundary BL2.

[0158] In an exemplary implementation, such as Figures 6a to 6iAs shown, in the bending area 12, the touch inorganic insulating layer 50 in the touch structure layer 500 is removed to form a second bending opening V2. The second bending opening V2 includes a third boundary BL3 and a fourth boundary BL4. In the structure of the protective structure 07 including the touch inorganic insulating layer 50, along the direction Y from the display area AA to the first frame area B1: the third boundary BL3 is located between the first boundary BL1 and the bending area 12, and the fourth boundary BL4 is located between the second boundary BL2 and the bending area 12, so that the touch inorganic insulating layer 50 in the protective structure 07 can cover the first boundary BL1 and the second boundary BL2, thereby relieving the stress of the first boundary BL1 and the second boundary BL2 and reducing the risk of film peeling or cracking near the first boundary BL1 and the second boundary BL2.

[0159] In an exemplary implementation, such as Figures 6a to 6i As shown, the circuit structure layer 200 may further include a first planarization layer 205 and a second planarization layer 206. In the direction Z perpendicular to the plane of the substrate 100, the first planarization layer 205 may be located between the inorganic insulating layer 20 and the at least one second signal connection line L2 in the circuit structure layer 200. The second planarization layer 206 may be located on the side of the at least one second signal connection line L2 away from the substrate 100. The first bending opening V1 can be filled by the first planarization layer 205. The orthographic projection of the first bending opening V1 onto the substrate 100 may be within the range of the orthographic projection of the second planarization layer 206 onto the substrate 100, i.e., the first bending opening V1 can be covered by the second planarization layer 206. The first planarization layer 205 and the second planarization layer 206 can disperse the stress of the first boundary BL1 and the second boundary BL2, reducing the risk of film peeling or cracking near the first boundary BL1 and the second boundary BL2.

[0160] In the first border region B1, the second flat layer 206 may include a second opening K2 that exposes at least a portion of the structure of the second signal connection line L2, through which the first signal connection line L1 can be electrically connected to the corresponding second signal connection line L2.

[0161] In an exemplary implementation, such as Figures 6a to 6i As shown, in the first opening K1 and the second opening K2 corresponding to the same second signal connection line L2, the orthographic projection of the first opening K1 on the substrate 100 can be located within the range of the orthographic projection of the second opening K2 on the substrate 100.

[0162] In an exemplary implementation, such as Figure 2a , Figure 3 , Figures 6a to 6i As shown, the display substrate may further include:

[0163] Multiple first signal lines L11 are located in display area AA;

[0164] Multiple pads PA are located in the first border area B1 and on the side of the bending area 12 away from the display area AA;

[0165] The end of the at least one second signal connection line L2 that is away from the display area AA is electrically connected to at least one pad through the corresponding first signal connection line L1, and the end that is close to the display area AA is electrically connected to at least one first signal line through the corresponding first signal connection line L1.

[0166] In an exemplary implementation, such as Figure 3 As shown, the multiple pads PA may include multiple driving pads PA1, multiple input pads PA2, and multiple bonding pads PA3 located in the bonding region 14. The multiple driving pads PA1 and multiple input pads PA2 may be located in the driving chip region 141, and the multiple bonding pads PA3 may be located in the bonding electrode region 142.

[0167] In an exemplary implementation, such as Figures 6a to 6i As shown, the first signal line L11 can be a touch signal line, and the second signal connection line L2 is electrically connected to at least one bonding pad at one end away from the display area AA through the corresponding first signal connection line L1, and the other end is electrically connected to at least one touch signal line through the corresponding first signal connection line L1.

[0168] In an exemplary implementation, such as Figures 6a to 6i As shown, in the direction Z from the circuit structure layer 200 to the protective structure layer 700, the touch structure layer 500 may include a touch buffer layer 501, a first touch conductive layer 511, a touch interlayer insulating layer 502, a second touch conductive layer 512, and a touch planarization layer 503 arranged sequentially; the first signal connection line L1 may be located in the second touch conductive layer 512; the touch inorganic insulating layer 50 may include the touch buffer layer 501 and the touch interlayer insulating layer 502; at least a portion of the protective structure 07 may be located in the touch planarization layer 503.

[0169] The first touch conductive layer 501 may include at least one third signal connection line L3, pointing in the direction Y from the display area AA to the first frame area B1. The at least one third signal connection line L3 corresponds one-to-one with at least one first signal connection line L1 located on the side of the bending area 12 near the display area AA. In the first frame area B1, the touch layer insulating layer 502 may include a third opening K3 that exposes at least a portion of the structure of the third signal connection line L3. The first signal connection line L1 can be electrically connected to the corresponding third signal connection line L3 through the third opening K3.

[0170] In an exemplary embodiment, the first signal line L11 may be located in the second touch conductive layer 512.

[0171] In an exemplary implementation, such as Figures 6a to 6i As shown, along the direction Y from the display area AA to the first border area B1, on the same side of the bending area 12, the third signal connection line L3 can be located on the side away from the bending area 12 at the center of the first signal connection line L1, and the first opening K1 can be located between the third opening K3 and the bending area 12.

[0172] The end of the second signal connection line L2 closest to the display area AA can be electrically connected to at least one first signal line through the corresponding first signal connection line L1 and the corresponding third signal connection line L3. The end of the second signal connection line L2 furthest from the display area AA can be electrically connected to at least one pad PA through the corresponding first signal connection line L1 and the corresponding third signal connection line L3.

[0173] In an exemplary implementation, such as Figure 6j As shown, Figure 2a A cross-sectional structural diagram along position a1-a1 is shown. The bending region 12 may contain a fourth signal connection line L4. The inorganic insulating layer 20 in the circuit structure layer 200 may contain a fifth signal connection line L5 and a sixth signal connection line L6. The fifth signal connection line L5 is located in the first fan-out region 11, and the sixth signal connection line L3 is located in the second fan-out region 13. In an exemplary embodiment, such as... Figure 6j As shown, a fourth via K4 and a fifth via K5 can be provided in the inorganic insulating layer 20 of the first planarization layer 205 and the circuit structure layer 200. The fourth signal connection line L4 can be electrically connected to the corresponding fifth signal connection line L5 through the fourth via K4, and the fourth signal connection line L4 can be electrically connected to the corresponding sixth signal connection line L6 through the fifth via K5. In an exemplary embodiment, such as... Figure 6j As shown, the fifth signal connection line L5 and the sixth signal connection line L6 can be located in at least one of the first gate metal layer and the second gate metal layer.

[0174] In an exemplary implementation, such as Figure 6j As shown, the fourth signal connection line L4 can be the second data connection line DL2, the fifth signal connection line L5 can be the first data connection line DL1, and the sixth signal connection line L6 can be the third data connection line DL3. The data lines DL, the first data connection line DL1, the second data connection line DL2, and the third data connection line DL3 can have a one-to-one correspondence. The end of the second data connection line DL2 away from the display area AA is electrically connected to at least one drive pad PA1 through the corresponding third data connection line DL3, and the end closer to the display area AA is electrically connected to the corresponding data line DL through the corresponding first data connection line DL1.

[0175] In an exemplary embodiment, Figure 6j In the structure shown, the fourth signal connection line L4 can be the second connection line of the first power line, the fifth signal connection line L5 can be the first connection line of the first power line, and the sixth signal connection line L6 can be the third connection line of the first power line. The display area AA can include multiple first power lines VDD. The end of the second connection line of the first power line away from the display area AA can be electrically connected to at least one bonding pad PA2 through the corresponding third connection line of the first power line, and the end closer to the display area AA can be electrically connected to the corresponding first power line VDD through the corresponding first connection line of the first power line.

[0176] In an exemplary embodiment, Figure 6j In the structure shown, the fourth signal connection line L4 can be the second connection line of the second power line, the fifth signal connection line L5 can be the first connection line of the first power line of the second power line, and the sixth signal connection line L6 can be the third connection line of the second power line. The third frame area B3 and the fourth frame area B4 can include at least one second power line VSS. The end of the second connection line of the second power line away from the display area AA can be electrically connected to at least one bonding pad PA2 through the corresponding third connection line of the second power line, and the end closer to the display area AA can be electrically connected to the corresponding second power line VSS through the corresponding first connection line of the second power line.

[0177] In an exemplary implementation, such as Figures 6a to 6j As shown, the first protective structure 71 can disperse the stress of the first boundary BL1, reducing the risk of film layer detachment or cracking near the first boundary BL1. For example, the first protective structure 71 can reduce the risk of detachment or cracking of the first signal connection line L1, the second signal connection line L2, the third signal connection line L3, the fourth signal connection line L4, and the fifth signal connection line L5 near the first boundary BL1. The second protective structure 72 can disperse the stress of the second boundary BL2, reducing the risk of film layer detachment or cracking near the second boundary BL2. For example, the second protective structure 72 can reduce the risk of detachment or cracking of the first signal connection line L1, the second signal connection line L2, the third signal connection line L3, the fourth signal connection line L4, and the sixth signal connection line L6 near the second boundary BL2.

[0178] In an exemplary implementation, such as Figure 2aAs shown, the display area AA may include multiple sub-pixels Pxij, and at least one sub-pixel Pxij includes a pixel driving circuit and a light-emitting element. The pixel driving circuit may be located in the circuit structure layer 200. At least one pixel driving circuit includes a transfer electrode, multiple transistors and at least one capacitor. In the same sub-pixel Pxij, the pixel driving circuit is electrically connected to the light-emitting element through the transfer electrode.

[0179] like Figure 5a and Figure 5b As shown, in the direction Z perpendicular to the plane of the substrate 100, the light-emitting element is located between the circuit structure layer 200 and the protective structure layer 700 (for example, the light-emitting element can be located in the light-emitting structure layer 300). The capacitor may include a first electrode plate and a second electrode plate sequentially disposed on one side of the substrate 100. The transistor may include an active layer, a control electrode, a first electrode, and a second electrode. The active layer is located on the side of the first electrode plate closer to the substrate 100. The control electrode may be disposed in the same layer as the first electrode plate. The first electrode and the second electrode are located on the side of the second electrode plate away from the substrate 100. The transfer electrode may be located on the side of the first electrode and the second electrode away from the substrate 100. The second signal connection line L2 may be disposed in the same layer as the transfer electrode. In an exemplary embodiment, the transfer electrode may be... Figure 5b The first transfer point 231 in the middle, or the transfer electrode may include, for example, Figure 5a At least one of the first transfer electrode 231 and the second transfer electrode 232 shown.

[0180] In an exemplary implementation, such as Figure 5a As shown, the first plate of the capacitor can be located in the first gate metal layer, the second plate of the capacitor can be located in the second gate metal layer, the active layer of the transistor can be located in the first semiconductor layer, the control electrode of the transistor can be located in the first gate metal layer, the first electrode and the second electrode of the transistor can be located in the first source-drain metal layer, and the transfer electrode can be located in the second source-drain metal layer and the third source-drain metal layer.

[0181] In an exemplary implementation, such as Figure 5b As shown, the first plate of the capacitor can be located in the first gate metal layer, the second plate of the capacitor can be located in the second gate metal layer, the active layer of the first transistor 21 can be located in the first semiconductor layer, the control electrode of the first transistor 21 can be located in the first gate metal layer, the first electrode and the second electrode of the first transistor 21 can be located in the first source-drain metal layer, the active layer of the second transistor 23 can be located in the second semiconductor layer, the control electrode of the second transistor 23 can include a bottom gate and a top gate, the bottom gate of the second transistor 23 can be located in the second gate metal layer, the top gate of the second transistor 23 can be located in the third gate metal layer, the first electrode and the second electrode of the second transistor 22 can be located in the first source-drain metal layer, and the transition electrode can be located in the second source-drain metal layer.

[0182] In an exemplary implementation, such as Figure 5a , Figures 6a to 6i As shown, in the direction Z perpendicular to the plane where the substrate 100 is located, the inorganic insulating layer 20 in the circuit structure layer 200 includes at least: a first gate insulating layer 201 located between the active layer and the control electrode, a second gate insulating layer 202 located between the control electrode and the second electrode plate, an interlayer insulating layer 203 located between the first electrode and the second electrode and the second electrode plate, and a passivation layer 204 located between the first electrode and the second electrode and the transition electrode.

[0183] In an exemplary implementation, such as Figure 5b , Figures 6a to 6i As shown, in the direction Z perpendicular to the plane where the substrate 100 is located, the inorganic insulating layer 20 in the circuit structure layer 200 includes at least: a first gate insulating layer 201 located between the active layer and the control electrode, a second gate insulating layer 202 located between the control electrode and the second electrode plate, a first interlayer insulating (ILD) layer 103 and a first buffer layer 104 located between the second gate metal layer and the second semiconductor layer (the first buffer layer 104 may be located on the side of the first interlayer insulating layer 103 away from the substrate 100), a third gate insulating layer 105 located between the second semiconductor layer and the third gate metal layer, a second interlayer insulating layer 106 located between the third gate metal layer and the first source / drain metal layer, an interlayer insulating layer 203 located between the first electrode and the second electrode and the second electrode plate, and a passivation layer 204 located between the first electrode and the second electrode and the transition electrode.

[0184] In an exemplary implementation, such as Figure 5a , Figure 5b , Figures 6a to 6j As shown, the display substrate may also include a light-emitting structure layer 300. In the direction Z perpendicular to the plane of the substrate 100, the light-emitting structure layer 300 is located between the circuit structure layer 200 and the protective structure layer 700. The light-emitting structure layer includes a pixel definition layer 304.

[0185] The pixel definition layer 304 may include a first structural portion PDL1, at least a portion of which is located in the bending region 12. The orthographic projection of the first structural portion PDL1 on the substrate 100 covers the orthographic projection of the first bending opening V1 on the substrate 100, so that the first structural portion PDL1 of the pixel definition layer 304 can cover the first boundary BL1 and the second boundary, thereby relieving the stress on the first boundary BL1 and the second boundary BL2 and reducing the risk of film peeling or cracking near the first boundary BL1 and the second boundary BL2.

[0186] In an exemplary implementation, such as Figure 5a , Figure 5b , Figures 6a to 6jAs shown, in the first border region B1, along the direction Y from the display region AA to the first border region B1: on the side of the bending region 12 near the display region AA, the first structural portion PDL1 of the pixel definition layer 304 is located on the side of the first opening K1 away from the display region AA, and the orthographic projection of the first structural portion PDL1 of the pixel definition layer 304 on the substrate at least partially overlaps with the orthographic projections of the first protective structure 71 and the first boundary BL1 on the substrate; on the side of the bending region 12 away from the display region AA, the first structural portion PDL1 of the pixel definition layer 304 may be located on the side of the first opening K1 near the display region AA, and the orthographic projection of the first structural portion PDL1 of the pixel definition layer 304 on the substrate at least partially overlaps with the orthographic projections of the second protective structure 71 and the second boundary BL2 on the substrate, that is, the first structural portion PDL1 of the pixel definition layer 304 covers the first boundary BL1 and the second boundary, thereby relieving the stress of the first boundary BL1 and the second boundary BL2, and reducing the risk of film peeling or cracking near the first boundary BL1 and the second boundary BL2.

[0187] In an exemplary embodiment Figures 6a to 6j As shown, along the direction from the display area AA to the first border area B1: a first buffer zone HC1 is provided between the first boundary BL1 and the bending area 12. The orthographic projection of the boundary of the first protective structure 71 near the bending area 12 on the substrate is within the range of the orthographic projection of the first buffer zone HC1 on the substrate, so that the first protective structure 71 can disperse the stress at the location of the first boundary BL1 and reduce the risk of film peeling or cracking near the first boundary BL1; a second buffer zone HC2 is provided between the second boundary 72 and the bending area 12. The orthographic projection of the boundary of the second protective structure 72 near the bending area 72 on the substrate is within the range of the orthographic projection of the second buffer zone HC2 on the substrate, so that the second protective structure 72 can disperse the stress at the location of the second boundary BL2 and reduce the risk of film peeling or cracking near the second boundary BL2.

[0188] In an exemplary embodiment Figures 6a to 6j As shown, along the direction from the display area AA to the first border area B1: the distance between the boundary of the first protective structure 71 near the bending area 12 and the first boundary BL1 is smaller than the size of the first buffer HC1, which can prevent the bending area 12 from affecting the film layer on the side of the bending area near the display area AA during the bending process; the distance between the boundary of the second protective structure 72 near the bending area 12 and the second boundary BL2 is smaller than the size of the second buffer CH2, which can prevent the bending area 12 from affecting the film layer on the side of the bending area away from the display area AA during the bending process.

[0189] In an exemplary embodiment, along the direction from the display area AA to the first border area B1, the size of the first buffer HC1 is 20 micrometers to 100 micrometers, and the size of the second buffer HC2 is 20 micrometers to 100 micrometers.

[0190] In an exemplary embodiment, the inorganic insulating layer 20 in the circuit structure layer 200 and the touch inorganic insulating layer 50 in the touch structure layer 500 are mainly fabricated by CVD (Chemical Vapor Deposition). The thin film material layer (deposition), which is generated by chemical vapor deposition, has significant stress. Therefore, in the bending region 12, the inorganic insulating layer 20 in the circuit structure layer 200 and the touch inorganic insulating layer 50 in the touch structure layer 500 need to be removed. However, the boundary of the inorganic insulating layer 20 in the circuit structure layer 200 still exists near the bending region 12. During the bending process, the boundary (i.e., the first boundary BL1 and the second boundary BL2) of the inorganic insulating layer 20 in the circuit structure layer 200 will still be affected. Simulation results show that different film layers have stress concentrations near the first boundary BL1 and the second boundary BL2 of the inorganic insulating layer 20 in the circuit structure layer 200. The inorganic insulating layer 20 in the circuit structure layer 200 is prone to peeling under stress, causing the first signal located on the side of the inorganic insulating layer 20 in the circuit structure layer 200 away from the substrate 100 to peel off. The connecting lines L1, L2, L3, and L4 are prone to detachment or cracking. This also causes the fifth and sixth signal connecting lines L5 and L6, located on the side of the inorganic insulating layer 20 near the substrate 100 in the circuit structure layer 200, to detach or crack. The detachment and cracking are mainly concentrated near the first boundary BL1 and the second boundary BL2. As the detachment or cracking extends, the first to sixth signal connecting lines L1 are affected, causing signals to fail to transmit normally. In severe cases, the metal layer in the display substrate is damaged, leading to the failure of the encapsulation structure layer 400. Moisture will enter the organic film layer along the damaged metal layer and extend to the display area AA, causing the display area AA to fail to display normally. The reliability (reliability margin) of the metal signal lines near the bending area is low.

[0191] like Figure 7 As shown, Figure 2a Another cross-sectional structural diagram along the u1-u1 position. Figure 7The structure shown does not have a first protective structure 71 and a second protective structure 72. During the bending process of the bending area 12, the stress at the boundary (first boundary BL1 and second boundary BL2) of the inorganic insulating layer 20 in the circuit structure layer 200 near the bending area 12 is relatively large. This can easily cause the first signal connection line L1, the second signal connection line L2, and the third signal connection line L3 near the first boundary BL1 and the second boundary BL2 to peel off or crack, resulting in abnormal display of the display substrate.

[0192] like Figure 8 As shown, Figure 2a A schematic diagram of a cross-sectional structure along the a1-a1 position. Figure 8 The structure shown does not have a first protective structure 71 and a second protective structure 72. During the bending process of the bending area 12, the stress at the boundary (first boundary BL1 and second boundary BL2) of the inorganic insulating layer 20 in the circuit structure layer 200 near the bending area 12 is relatively large. This can easily cause the fourth signal connection line L4, the fifth signal connection line L5, and the sixth signal connection line L6 near the first boundary BL1 and the second boundary BL2 to peel off or crack, resulting in abnormal display of the display substrate.

[0193] like Figures 6a to 6j As shown, Figures 6a to 6i for Figure 2a Schematic diagrams of several cross-sectional structures along the u1-u1 position. Figure 6j for Figure 2a A cross-sectional structural diagram along the a1-a1 position shows a first protective structure 71 and a second protective structure 72 near the bending area 12. During the bending process of the bending area 12, the stress at the boundaries (first boundary BL1 and second boundary BL2) of the inorganic insulating layer 20 in the circuit structure layer 200 near the bending area 12 is dispersed by the first protective structure 71 and the second protective structure 72. This can reduce the risk of the first signal connection line L1 to the sixth signal connection line L6 peeling or cracking near the first boundary BL1 and the second boundary BL2, thereby improving the product yield of the display substrate and increasing the reliability (reliability margin) of the metal signal lines near the bending area.

[0194] In an exemplary implementation, such as Figures 6a to 6jAs shown, the touch planarization layer 503 of the bending region 12 is removed to prevent the film thickness of the bending region 12 from being too large and difficult to bend. The bending region 12, the first buffer zone HC1, and the second buffer zone HC2 are provided with a first planarization layer PLN1, a second planarization layer PLN2, and a first structural part PDL1 of the pixel definition layer 304. The first planarization layer PLN1, the second planarization layer PLN2, and the first structural part PDL1 of the pixel definition layer 304, which are made of organic materials, can also play a role in dispersing the stress of the first boundary BL1 and the second boundary BL2, but the stress dispersion ability is limited and needs to be set up. The first protective structure 71 and the second protective structure 72 further disperse the stress at the first boundary BL1 and the second boundary BL2 to reduce the risk of film peeling or cracking near the stress at the first boundary BL1 and the second boundary BL2. The bending region 12 and the second planarization layer PLN2 at the positions of the first buffer zone HC1 and the second buffer zone HC2, and the first structural part PDL1 of the pixel definition layer 304 can protect the second signal connection line L2 and the fourth signal connection line L4, preventing them from being corroded in subsequent fabrication processes. Figure 6a and Figure 6f As shown, along the direction Y from the display area AA to the first border area B1, the first structural part PDL1 of the pixel definition layer 304 extends to the second fan-out area 13, which can increase the height of the first border area B1, reduce the height difference between the first border area B1 and the display area AA, and improve the flatness of the display substrate.

[0195] In an exemplary implementation, such as Figures 6a to 6j As shown, the bending area 12 and bonding area 14 of the display substrate are not covered by the touch planarization layer 503 in the touch structure layer 500, while other areas are covered by the touch planarization layer 503 in the touch structure layer 500. The touch planarization layer 503 in the touch structure layer 500 can protect the display substrate.

[0196] In an exemplary embodiment, the structures of the first protective structure 71 and the second protective structure 72 described above can be applied to the boundaries of other locations of the inorganic insulating layer 20 in the circuit structure layer 200, and are not limited to the boundary near the bending region 12.

[0197] This disclosure also provides a display device, such as... Figure 9 As shown, the display device may include a display substrate. The display substrate may be the display substrate provided in any of the foregoing embodiments.

[0198] In one exemplary embodiment, the display device can be a liquid crystal display (LCD), an organic light-emitting diode (OLED), or a light-emitting diode (LED) display device. The display device can be any product or component with display functionality, such as a liquid crystal panel, electronic paper, an OLED panel, an active-matrix organic light-emitting diode (AMOLED) panel, a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, or a navigator.

[0199] The display substrate and display device provided in this embodiment include a display area and a first border area located on at least one side. A circuit structure layer and a protective structure layer are sequentially provided on one side of the substrate. The protective structure layer contains a protective structure. The first border area includes a bending area. In the bending area, an inorganic insulating layer in the circuit structure layer is removed to form a first bending opening. The orthographic projection of at least one boundary of the first bending opening on the substrate is covered by the orthographic projection of the protective structure on the substrate. Along the direction from the display area to the first border area, the protective structure and at least one boundary of the first bending opening are located on at least one side of the bending area. In the technical solution provided in this embodiment, the removal of the inorganic insulating layer in the circuit structure layer to form the first bending opening, and the orthographic projection of at least one boundary of the first bending opening on the substrate being covered by the orthographic projection of the protective structure on the substrate, can disperse the stress of the inorganic insulating layer in the circuit structure layer, and can solve the technical problem of film peeling or cracking near the bending area to a certain extent.

[0200] Where there is no conflict, the features of the embodiments disclosed herein can be combined with each other to obtain new embodiments.

[0201] While the embodiments disclosed herein are as described above, the content is merely for the purpose of facilitating understanding of these embodiments and is not intended to limit them. Any person skilled in the art to which these embodiments pertain may make any modifications and changes to the form and details of the implementation without departing from the spirit and scope disclosed herein; however, the patent protection scope of these embodiments shall still be determined by the scope defined in the appended claims.

Claims

1. A display substrate, characterized in that, include: A substrate, the substrate including a display area and a first border area located on at least one side of the display area; A circuit structure layer is located on one side of the substrate. A protective structure layer is located on the side of the circuit structure layer away from the substrate, and the protective structure layer is provided with a protective structure; A bending area is located in the first frame area, in which the inorganic insulating layer in the circuit structure layer is removed to form a first bending opening; Wherein, at least one boundary of the first bending opening is orthographically projected onto the substrate by the orthographically projected onto the substrate by the protective structure, and along the direction from the display area to the first border area, the protective structure and at least one boundary of the first bending opening are located on at least one side of the bending area.

2. The display substrate according to claim 1, characterized in that, The protective structure includes a first protective structure and a second protective structure, and at least one boundary of the first bent opening includes a first boundary and a second boundary. Along the direction from the display area to the first border area, the first protective structure and the first boundary are located on the side of the bending area closer to the display area, and the second protective structure and the second boundary are located on the side of the bending area away from the display area. The orthographic projection of the first boundary onto the substrate is covered by the orthographic projection of the first protective structure onto the substrate. The orthographic projection of the second boundary onto the substrate is covered by the orthographic projection of the second protective structure onto the substrate.

3. The display substrate according to claim 2, characterized in that, The protective structure layer includes at least a touch structure layer, which includes a touch planarization layer. In a direction perpendicular to the plane of the substrate, the touch planarization layer is the film layer in the touch structure layer that is farthest from the circuit structure layer. At least a portion of the protective structure is located in the touch planarization layer.

4. The display substrate according to claim 3, characterized in that, The protective structure layer further includes a first protective layer, which is located on the side of the touch planarization layer away from the substrate in a direction perpendicular to the plane of the substrate. The touch planarization layer includes a first region, a second region, and at least one blocking structure. The blocking structure is located in the first border region. The first region of the touch planarization layer and the first protective layer form a cover layer. The cover layer is located in the display region and extends to the first border region in a direction from the display region to the first border region. The cover layer is located on the side of the at least one blocking structure away from the bending area. The second region of the touch planarization layer is located on the side of the bending area away from the display region. The second protective structure includes at least the second region of the touch planarization layer.

5. The display substrate according to claim 4, characterized in that, The at least one blocking structure includes a first blocking structure and a second blocking structure, which are located along the direction from the display area to the first border area, with the first blocking structure located on the side of the second blocking structure away from the display area. The orthogonal projection of the first barrier structure on the substrate covers the orthogonal projection of the first boundary on the substrate, and the first protective structure includes the first barrier structure; Alternatively, the orthogonal projection of the second barrier structure onto the substrate covers the orthogonal projection of the first boundary onto the substrate, and the first protective structure includes the second barrier structure.

6. The display substrate according to claim 5, characterized in that, Along the direction from the display area to the first border area: in a structure in which the orthogonal projection of the first blocking structure on the substrate covers the orthogonal projection of the first boundary on the substrate, the size of the first blocking structure is larger than the size of the second blocking structure; In a structure in which the orthographic projection of the second blocking structure on the substrate covers the orthographic projection of the first boundary on the substrate, the size of the first blocking structure is smaller than the size of the second blocking structure.

7. The display substrate according to claim 4, characterized in that, The at least one blocking structure includes a first blocking structure in the direction from the display area to the first border area, the edge of the cover layer near the bending area is located between the first boundary and the first blocking structure, the orthographic projection of the first boundary on the substrate is within the range of the orthographic projection of the cover layer on the substrate, and the first protective structure includes the cover layer.

8. The display substrate according to any one of claims 4 to 7, characterized in that, In the first border area, along the direction from the display area to the first border area, the boundary of the first protective layer on the side away from the display area is located between the boundary of the first area of ​​the touch planar layer on the side away from the display area and the at least one blocking structure.

9. The display substrate according to any one of claims 4 to 7, characterized in that, Along the direction from the display area to the first border area, the second boundary is located between the second region of the touch planarization layer and the bending area, and the orthographic projection of the second boundary on the substrate is within the range of the orthographic projection of the second region of the touch planarization layer on the substrate.

10. The display substrate according to any one of claims 2 to 7, characterized in that, The protective structure layer includes at least a touch structure layer, which includes at least one first signal connection line and a touch inorganic insulating layer. In a direction perpendicular to the plane of the substrate, the touch inorganic insulating layer is located on the side of the first signal connection line closer to the substrate. The protective structure includes at least one of the first signal connection line and the touch inorganic insulating layer.

11. The display substrate according to claim 10, characterized in that, The touch structure layer further includes a touch planarization layer. In a direction perpendicular to the plane of the substrate, the touch planarization layer is located on the side of the first signal connection line away from the substrate, and at least a portion of the protective structure is located in the touch planarization layer. Along the direction from the display area to the first frame area, in the protective structure on the same side of the bending area: the structure located on the touch planarization layer has its orthogonal projection on the substrate, which covers the orthogonal projection of the structure located on the touch inorganic insulating layer on the substrate; The orthographic projection of the structure located on the touch planarization layer onto the substrate covers the orthographic projection of the first signal connection line onto the substrate.

12. The display substrate according to claim 10, characterized in that, In the structure of the first protective structure including the first signal connection line, along the direction from the display area to the first border area: the first signal connection line in the first protective structure is located on the side of the bending area close to the display area, and both ends are located on both sides of the first boundary, and the first signal connection line in the first protective structure at least partially overlaps with the orthographic projection of the first boundary on the substrate.

13. The display substrate according to claim 10, characterized in that, In the second protection structure including the first signal connection line, along the direction from the display area to the first border area: the first signal connection line in the second protection structure is located on the side of the bending area away from the display area, and both ends are located on both sides of the second boundary, and the first signal connection line in the second protection structure at least partially overlaps with the orthographic projection of the second boundary on the substrate.

14. The display substrate according to claim 10, characterized in that, The circuit structure layer further includes at least one second signal connection line, at least a portion of the structure of the second signal connection line is located in the bending area, the same second signal connection line corresponds to two first signal connection lines, along the direction from the display area to the first border area, of the two first signal connection lines corresponding to the same second signal connection line, one first signal connection line is located on the side of the bending area closer to the display area, and the other first signal connection line is located on the side of the bending area away from the display area; In the first border area, the touch-sensitive inorganic insulating layer includes a first opening that exposes at least a portion of the structure of the second signal connection line, through which the first signal connection line is electrically connected to a corresponding second signal connection line.

15. The display substrate according to claim 14, characterized in that, Along the direction from the display area to the first border area, on the side of the bending area near the display area, the first opening is located on the side of the first boundary near the display area. In the structure of the first protective structure including the touch inorganic insulating layer, the first protective structure includes a touch inorganic insulating layer located between the first opening and the bending area. The orthographic projection of the touch inorganic insulating layer in the first protective structure on the substrate covers the orthographic projection of the first boundary on the substrate.

16. The display substrate according to claim 14, characterized in that, Along the direction from the display area to the first border area, on the side of the bending area away from the display area, the first opening is located on the side of the second boundary away from the display area. In the structure of the second protective structure including the touch inorganic insulating layer, the second protective structure includes a touch inorganic insulating layer located between the first opening and the bending area. The orthographic projection of the touch inorganic insulating layer in the second protective structure on the substrate covers the orthographic projection of the second boundary on the substrate.

17. The display substrate according to claim 14, characterized in that, In the bending area, the touch inorganic insulating layer in the touch structure layer is removed to form a second bending opening. The second bending opening includes a third boundary and a fourth boundary. In the structure of the protective structure including the touch inorganic insulating layer, along the direction from the display area to the first frame area: the third boundary is located between the first boundary and the bending area, and the fourth boundary is located between the second boundary and the bending area.

18. The display substrate according to claim 14, characterized in that, The circuit structure layer further includes a first planarization layer and a second planarization layer. In a direction perpendicular to the plane of the substrate, the first planarization layer is located between the inorganic insulating layer and the at least one second signal connection line in the circuit structure layer. The second planarization layer is located on the side of the at least one second signal connection line away from the substrate. The first bending opening is filled by the first planarization layer. The orthographic projection of the first bending opening on the substrate is within the range of the orthographic projection of the second planarization layer on the substrate. In the first border region, the second planarization layer includes a second opening that exposes at least a portion of the structure of the second signal connection line, through which the first signal connection line is electrically connected to a corresponding second signal connection line.

19. The display substrate according to claim 18, characterized in that, In the first opening and the second opening corresponding to the same second signal connection line, the orthographic projection of the first opening on the substrate is within the range of the orthographic projection of the second opening on the substrate.

20. The display substrate according to claim 14, characterized in that, Also includes: Multiple first signal lines are located in the display area; Multiple pads are located in the first frame area and on the side of the bending area away from the display area; The end of the at least one second signal connection line away from the display area is electrically connected to at least one pad via a corresponding first signal connection line, and the end closer to the display area is electrically connected to at least one first signal line via a corresponding first signal connection line.

21. The display substrate according to claim 20, characterized in that, In the direction from the circuit structure layer to the protective structure layer, the touch structure layer includes a touch buffer layer, a first touch conductive layer, an inter-layer insulating layer, a second touch conductive layer, and a touch planarization layer arranged sequentially; the first signal connection line is located in the second touch conductive layer; the touch inorganic insulating layer includes the touch buffer layer and the inter-layer insulating layer; and at least a portion of the protective structure is located in the touch planarization layer. The first touch conductive layer includes at least one third signal connection line in the direction from the display area to the first frame area. The at least one third signal connection line corresponds one-to-one with at least one first signal connection line located on the side of the bending area near the display area. In the first frame area, the touch layer insulating layer includes a third opening that exposes at least a portion of the structure of the third signal connection line. The first signal connection line is electrically connected to the corresponding third signal connection line through the third opening.

22. The display substrate according to claim 21, characterized in that, Along the direction from the display area to the first border area, on the same side of the bending area, the center of the third signal connection line is located on the side of the center of the first signal connection line away from the bending area, and the first opening is located between the third opening and the bending area; the end of the second signal connection line near the display area is electrically connected to at least one first signal line through the corresponding first signal connection line and the corresponding third signal connection line.

23. The display substrate according to claim 14, characterized in that, The display area includes multiple sub-pixels, and at least one sub-pixel includes a pixel driving circuit and a light-emitting element. The pixel driving circuit is located in the circuit structure layer and includes a transfer electrode, multiple transistors, and at least one capacitor. In the same sub-pixel, the pixel driving circuit is electrically connected to the light-emitting element through the transfer electrode. In a direction perpendicular to the plane of the substrate, the light-emitting element is located between the circuit structure layer and the protective structure layer. The capacitor includes a first electrode plate and a second electrode plate sequentially disposed on one side of the substrate. The transistor includes an active layer, a control electrode, a first electrode, and a second electrode. The active layer is located on the side of the first electrode plate closer to the substrate. The control electrode is disposed on the same layer as the first electrode plate. The first electrode and the second electrode are located on the side of the second electrode plate away from the substrate. The transition electrode is located on the side of the first electrode and the second electrode away from the substrate. The second signal connection line is disposed on the same layer as the transition electrode.

24. The display substrate according to claim 23, characterized in that, In a direction perpendicular to the plane of the substrate, the inorganic insulating layer in the circuit structure layer includes at least: a first gate insulating layer between the active layer and the control electrode, a second gate insulating layer between the control electrode and the second electrode plate, an interlayer insulating layer between the first electrode and the second electrode and the second electrode plate, and a passivation layer between the first electrode and the second electrode and the transition electrode.

25. The display substrate according to claim 14, characterized in that, It also includes a light-emitting structure layer, which is located between the circuit structure layer and the protective structure layer in a direction perpendicular to the plane of the substrate, and the light-emitting structure layer includes a pixel definition layer; The pixel definition layer includes a first structural portion, at least a portion of which is located in the bending region. The orthographic projection of the first structural portion of the pixel definition layer on the substrate covers the orthographic projection of the first bending opening on the substrate.

26. The display substrate according to claim 25, characterized in that, In the first border area, along the direction from the display area to the first border area: on the side of the bending area close to the display area, the first structural part is located on the side of the first opening away from the display area, and the orthogonal projection of the first structural part of the pixel definition layer on the substrate at least partially overlaps with the orthogonal projection of the first protective structure and the first boundary of the pixel definition layer on the substrate. On the side of the bending area away from the display area, the first structural portion of the pixel definition layer is located on the side of the first opening close to the display area, and the orthographic projection of the first structural portion of the pixel definition layer on the substrate at least partially overlaps with the orthographic projections of the second protective structure and the second boundary on the substrate.

27. The display substrate according to any one of claims 2 to 7, characterized in that, Along the direction from the display area to the first border area: a first buffer zone is provided between the first boundary and the bending area, and the orthographic projection of the boundary of the first protective structure on the side near the bending area on the substrate is within the range of the orthographic projection of the first buffer zone on the substrate; a second buffer zone is provided between the second boundary and the bending area, and the orthographic projection of the boundary of the second protective structure on the side near the bending area on the substrate is within the range of the orthographic projection of the second buffer zone on the substrate.

28. The display substrate according to claim 27, characterized in that, Along the direction from the display area to the first border area, the size of the first buffer is 20 micrometers to 100 micrometers, and the size of the second buffer is 20 micrometers to 100 micrometers.

29. A display device, characterized in that, Includes the display substrate as described in any one of claims 1 to 28.

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