Improved process stability light emitting diodes and methods of making the same

Abstract

The present disclosure provides a kind of improved process stability light-emitting diode and its preparation method, belong to the field of optoelectronic manufacturing technology.The preparation method includes: growing epitaxial layer on substrate;Transparent conductive layer and barrier layer are formed in turn on the surface of the epitaxial layer away from the substrate;Mask is formed on the surface of the barrier layer, and the barrier layer is etched through the mask to form the etching window exposing the transparent conductive layer;The transparent conductive layer is wet etched through the etching window to form the patterned transparent conductive layer.The embodiment of the present disclosure can reduce the difficulty of preparing transparent conductive layer on micro light-emitting diode, improve process stability.

Description

Technical Field

[0001] This disclosure relates to the field of optoelectronic manufacturing technology, and in particular to a light-emitting diode with improved process stability and a method for its fabrication. Background Technology

[0002] Micro LED (Micro Light Emitting Diode) is a display technology that miniaturizes LEDs to the micrometer level. In Micro LED, the p-type GaN layer is usually located on the side closest to the light-emitting surface. However, the p-type GaN layer itself has a very high resistivity. If the electrode is directly deposited onto the p-type GaN layer, the current will be confined to a very small area directly below the electrode, resulting in current congestion.

[0003] In related technologies, a transparent conductive layer (ITO) is typically deposited on a p-type GaN layer. The transparent conductive layer forms an ohmic contact with the p-type GaN layer, which reduces contact resistance and facilitates current injection. When fabricating the transparent conductive layer, the continuous transparent conductive layer needs to be patterned. First, the desired pattern is defined using photoresist through photolithography. Then, wet etching is used to remove the ITO in the unwanted areas, leaving the ITO in the target areas.

[0004] However, when the LED size shrinks to below 40μm, the adhesion of the photoresist decreases, making it easy to fall off during the etching process, resulting in pattern distortion. Wet etching is isotropic etching (simultaneous etching in the transverse and longitudinal directions). At small sizes, the relative proportion of transverse etching increases and is difficult to control, leading to unstable edge dimensions of the ITO pattern. At the corners of small transparent conductive layers, the chemical solution cannot completely penetrate and etch, leaving behind unremoved ITO, or irregular residues due to uneven etching rates, ultimately leading to failure of electrical isolation between pixels or short circuits. Summary of the Invention

[0005] This disclosure provides a light-emitting diode (LED) with improved process stability and its fabrication method, which can reduce the difficulty of fabricating a transparent conductive layer on a micro LED and improve process stability. The technical solution is as follows: On one hand, this disclosure provides a method for fabricating a light-emitting diode, the method comprising: growing an epitaxial layer on a substrate; sequentially forming a transparent conductive layer and a barrier layer on the surface of the epitaxial layer away from the substrate; forming a mask on the surface of the barrier layer and etching the barrier layer through the mask to form an etching window exposing the transparent conductive layer; and performing wet etching on the transparent conductive layer through the etching window to form a patterned transparent conductive layer.

[0006] In one implementation of this disclosure, forming the barrier layer on the transparent conductive layer includes forming a barrier layer with a thickness of 500 angstroms to 1000 angstroms on the transparent conductive layer.

[0007] In another implementation of this disclosure, the barrier layer includes at least one of a silicon oxide layer, a silicon nitride layer, and an aluminum oxide layer.

[0008] In another implementation of this disclosure, etching the barrier layer through the mask includes: adjusting the upper electrode power of the etching equipment to 400W to 600W and the lower electrode power to 100W to 180W to etch the barrier layer.

[0009] In another implementation of this disclosure, wet etching of the transparent conductive layer through the etching window includes etching the transparent conductive layer using a mixed solution of ferric chloride and hydrochloric acid.

[0010] In another implementation of this disclosure, wet etching of the transparent conductive layer further includes: determining the etching time based on the correspondence between the thickness of the transparent conductive layer and the etching time, wherein the correspondence is: T=h×N, where T is the etching time in seconds, h is the thickness of the transparent conductive layer in angstroms, and N is a proportionality coefficient, with N ranging from 0.2 to 0.6.

[0011] In another implementation of this disclosure, wet etching of the transparent conductive layer further includes etching the transparent conductive layer at a temperature of 40°C to 50°C.

[0012] In another implementation of this disclosure, after wet etching of the transparent conductive layer through the etching window, the method further includes: removing the mask using an alkaline solution; and removing the barrier layer using a buffered oxide etchant.

[0013] Secondly, embodiments of this disclosure provide a light-emitting diode (LED) fabricated using the fabrication method described above, comprising a substrate, an epitaxial layer, and a transparent conductive layer stacked sequentially.

[0014] In another implementation of this disclosure, the side length of the orthographic projection of the epitaxial layer onto the substrate is less than or equal to 40 μm.

[0015] The beneficial effects of the technical solutions provided in this disclosure include at least the following: The fabrication method provided in this disclosure increases the adhesion of the photoresist by adding a barrier layer to the surface of the transparent conductive layer, thus providing a more stable and highly adhesive substrate for the photoresist. The photoresist can be directly coated onto the surface of the barrier layer, and its adhesion changes from the "transparent conductive layer-photoresist" interface to the "barrier layer-photoresist" interface. This effectively solves the problem of photoresist detachment in small sizes, ensuring that the pattern defined by photolithography is accurately transferred to the barrier layer, thereby avoiding pattern distortion caused by photoresist detachment.

[0016] Meanwhile, the barrier layer acts as an intermediate mask layer. First, a pattern is defined on the barrier layer surface using photoresist, and then the barrier layer is etched to form a precise etching window. During subsequent wet etching, the transparent conductive layer is only etched within the etching window; the areas of the transparent conductive layer not covered by the window remain tightly protected by the barrier layer. In this case, the barrier layer acts as a physical boundary, limiting the lateral diffusion of wet etching, significantly reducing the relative proportion of lateral etching, and making the edge dimensions (such as linewidth and corner contours) of the transparent conductive layer pattern more stable, especially maintaining high-precision patterns at small sizes (≤40μm).

[0017] Furthermore, the size and shape of the etching window are precisely controlled by photolithography, so that the etching solution can only penetrate into the transparent conductive layer through the etching window. The non-etched area covered by the barrier layer is completely isolated from the solution, ensuring that the transparent conductive layer is thoroughly etched only within the etching window. The etching of difficult-to-process areas such as corners is more uniform, completely eliminating residual transparent conductive layer and irregular trailing, and avoiding the risk of short circuit. Attached Figure Description

[0018] To more clearly illustrate the technical solutions in the embodiments of this disclosure, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0019] Figure 1 This is a flowchart illustrating the fabrication process of a light-emitting diode according to an embodiment of this disclosure; Figure 2 This is a top view comparison diagram of a light-emitting diode provided in an embodiment of this disclosure; Figure 3 This is an electron microscope comparison image of a light-emitting diode provided in an embodiment of this disclosure; Figure 4 This is a fabrication state diagram of a light-emitting diode provided in an embodiment of this disclosure; Figure 5 This is a top view of a light-emitting diode provided in an embodiment of this disclosure; Figure 6 This is a schematic diagram of the structure of a light-emitting diode provided in an embodiment of this disclosure.

[0020] The markings in the diagram are explained as follows: 10. Substrate; 20. Epitaxial layer; 30. Transparent conductive layer; 40. Barrier layer; 50. Mask; 51. Etching window. Detailed Implementation

[0021] To make the objectives, technical solutions, and advantages of this disclosure clearer, the embodiments of this disclosure will be described in further detail below with reference to the accompanying drawings.

[0022] Unless otherwise defined, the technical or scientific terms used herein shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” “third,” and similar terms used in this patent application specification and claims do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Similarly, the terms “an” or “a” and similar terms do not indicate a quantity limitation, but rather indicate the presence of at least one. The terms “comprising” or “including” and similar terms mean that the elements or objects preceding “comprising” or “including” encompass the elements or objects listed following “comprising” or “including” and their equivalents, and do not exclude other elements or objects. The terms “connected” or “linked” and similar terms are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. The terms “upper,” “lower,” “left,” “right,” “top,” and “bottom,” etc., are used only to indicate relative positional relationships, and these relative positional relationships may change accordingly when the absolute position of the described objects changes.

[0023] Figure 1 This is a flowchart illustrating the fabrication process of a light-emitting diode (LED) according to an embodiment of this disclosure. Figure 1 As shown, the preparation method includes: Step S11: Grow an epitaxial layer on the substrate.

[0024] For example, the substrate is a sapphire substrate. Sapphire substrates have high light transmittance, meaning they are transparent. Furthermore, sapphire material is relatively hard and chemically stable, giving the light-emitting diode (LED) good luminous efficacy and stability.

[0025] For example, the epitaxial layer includes a first semiconductor layer, a multiple quantum well layer, and a second semiconductor layer stacked sequentially.

[0026] In this process, one of the first semiconductor layer and the second semiconductor layer is a p-type layer, and the other of the first semiconductor layer and the second semiconductor layer is an n-type layer.

[0027] Step S12: A transparent conductive layer and a barrier layer are sequentially formed on the surface of the epitaxial layer away from the substrate.

[0028] Step S13: A mask is formed on the surface of the barrier layer, and the barrier layer is etched through the mask to form an etch window that exposes the transparent conductive layer.

[0029] Step S14: Perform wet etching on the transparent conductive layer through the etching window to form a patterned transparent conductive layer.

[0030] The fabrication method provided in this disclosure increases the adhesion of the photoresist by adding a barrier layer to the surface of the transparent conductive layer, thus providing a more stable and highly adhesive substrate for the photoresist. The photoresist can be directly coated onto the surface of the barrier layer, and its adhesion changes from the "transparent conductive layer-photoresist" interface to the "barrier layer-photoresist" interface. This effectively solves the problem of photoresist detachment in small sizes, ensuring that the pattern defined by photolithography is accurately transferred to the barrier layer, thereby avoiding pattern distortion caused by photoresist detachment.

[0031] Meanwhile, the barrier layer acts as an intermediate mask layer. First, a pattern is defined on the barrier layer surface using photoresist, and then the barrier layer is etched to form a precise etching window. During subsequent wet etching, the transparent conductive layer is only etched within the etching window; the areas of the transparent conductive layer not covered by the window remain tightly protected by the barrier layer. In this case, the barrier layer acts as a physical boundary, limiting the lateral diffusion of wet etching, significantly reducing the relative proportion of lateral etching, and making the edge dimensions (such as linewidth and corner contours) of the transparent conductive layer pattern more stable, especially maintaining high-precision patterns at small sizes (≤40μm).

[0032] Figure 2 This is a top-view comparison diagram of a light-emitting diode provided in an embodiment of this disclosure. Figure 3 This is an electron microscope comparison image of a light-emitting diode provided in an embodiment of this disclosure. Figure 2 and Figure 3 The left and right sides of the image show light-emitting diodes with transparent conductive layers fabricated without the addition of a barrier layer. Figure 2 and Figure 3 The right side of the image shows light-emitting diodes with transparent conductive layers fabricated by adding a barrier layer.

[0033] like Figure 2 , 3 As shown, the size and shape of the etching window are precisely controlled by photolithography, so that the etching solution can only penetrate into the transparent conductive layer 30 through the etching window. The non-etched area covered by the barrier layer is completely isolated from the solution, ensuring that the transparent conductive layer 30 is thoroughly etched only within the etching window. The etching of difficult-to-process areas such as corners is more uniform, completely eliminating residual transparent conductive layer 30 and irregular trailing, and avoiding the risk of short circuit.

[0034] The epitaxial layer 20 formed in step S11 may include a first semiconductor layer, a multiple quantum well layer and a second semiconductor layer sequentially stacked on the substrate.

[0035] The first semiconductor layer has a first conductivity type, the second semiconductor layer has a second conductivity type different from the first conductivity type, and the multiple quantum well layer is used to generate light through electron-hole recombination.

[0036] In this process, one of the first semiconductor layer and the second semiconductor layer is a p-type layer, and the other of the first semiconductor layer and the second semiconductor layer is an n-type layer.

[0037] As an example, the first semiconductor layer is an n-type layer and the second semiconductor layer is a p-type layer.

[0038] Optionally, the first semiconductor layer is an n-type GaN layer. The thickness of the n-type GaN layer can be from 0.5 μm to 1 μm.

[0039] Optionally, the multiple quantum well layer includes alternating InGaN quantum well layers and GaN quantum barrier layers. Specifically, the multiple quantum well layer may include 3 to 8 alternating stacked InGaN quantum well layers and GaN quantum barrier layers.

[0040] As an example, in an embodiment of this disclosure, the multi-quantum-well layer includes five alternating stacked InGaN quantum-well layers and GaN quantum-barrier layers.

[0041] Optionally, the thickness of the multi-quantum well layer can be from 150 nm to 200 nm.

[0042] Optionally, the second semiconductor layer is a p-type GaN layer. The thickness of the p-type GaN layer can be from 0.5 μm to 1 μm.

[0043] Step S12 may include the following steps: First step, such as Figure 4 As shown, a transparent conductive layer 30 is uniformly deposited on the surface of the p-type layer using processes such as magnetron sputtering and electron beam evaporation.

[0044] For example, the transparent conductive layer 30 includes: an indium tin oxide layer, an aluminum-doped zinc oxide layer, and a fluorine-doped tin oxide layer.

[0045] For example, the thickness of the transparent conductive layer 30 is 200 angstroms to 3000 angstroms.

[0046] The second step involves placing the deposited epitaxial wafer in a rapid annealing furnace and performing high-temperature annealing in a nitrogen or nitrogen-oxygen mixed atmosphere. This promotes a chemical reaction between the transparent conductive layer 30 and the p-type layer interface, reduces the interface barrier, and ultimately forms an ohmic contact layer with low contact resistance, ensuring efficient current injection into the active region.

[0047] For example, the annealing conditions are: temperature 450°C to 600°C, time 30s to 120s.

[0048] The third step, as Figure 4 As shown, an insulating material with high etching selectivity, high surface flatness and strong adhesion to photoresist is selected for the transparent conductive layer 30. A barrier layer 40 is formed on the surface of the transparent conductive layer 30 by plasma-enhanced chemical vapor deposition, magnetron sputtering or atomic layer deposition.

[0049] For example, a barrier layer 40 with a thickness of 500 to 1000 angstroms is formed on the transparent conductive layer 30.

[0050] The thickness range of the aforementioned transparent conductive layer 30 falls within the thin film category, with a small total material volume. During subsequent etching removal, chemical reagents penetrate faster and the etching rate is higher, which can significantly shorten the process time and reduce reagent consumption. At the same time, the thin-layer structure makes it easier to achieve residue-free removal, avoiding the blocking material residue caused by incomplete etching of thick films, and preventing contamination of the transparent conductive layer 30 or affecting the electrical performance of the pixels.

[0051] Optionally, the barrier layer 40 includes at least one of a silicon oxide layer, a silicon nitride layer, and an aluminum oxide layer.

[0052] For example, the barrier layer 40 includes a silicon oxide layer. The silicon oxide layer has moderate surface energy, strong adhesion to photoresist, high selectivity for ITO during etching, and easily forms a clear mask.

[0053] For example, the barrier layer 40 includes a silicon nitride layer. The silicon nitride layer has a dense structure and high mechanical strength, which can effectively block the lateral diffusion of wet etching; it has a large difference in etching rate from ITO, high mask edge precision, and strong resistance to chemical penetration, making it suitable for small-size patterned confinement protection.

[0054] For example, the barrier layer 40 includes an aluminum oxide layer. The aluminum oxide layer has excellent chemical stability and is resistant to acid and alkali corrosion; its low surface roughness facilitates photoresist adhesion, and it has good selectivity for ITO etching. A thin layer can achieve reliable mask protection and reduce the risk of residue.

[0055] Step S13 may include the following steps: The first step is to spin-coat a layer of positive photoresist on the surface of the barrier layer 40 after the barrier layer 40 is deposited, with the spin speed controlled at 2000 rpm to 4000 rpm, to form a uniform photoresist film with a thickness of 0.5 μm to 1.5 μm.

[0056] The second step, as Figure 4As shown, exposure is performed using a photolithography machine, aligning a pre-designed patterned photomask 50 with the barrier layer 40, causing a photolysis reaction in the photosensitive area of ​​the photoresist. After exposure, development is performed with a developer for 30 to 60 seconds to remove the photoresist in the photosensitive area, leaving the photoresist in the non-photosensitive area, thereby forming the photomask 50 on the surface of the barrier layer 40.

[0057] The third step, as Figure 4 As shown, the exposed barrier layer 40 is etched using an inductively coupled plasma (ICP) etching device with the mask 50 as a reference.

[0058] For example, CF4 is used as the main etching gas (flow rate of 30 sccm to 50 sccm), and a small amount of Ar (5 sccm to 10 sccm) can be added as a carrier gas to enhance plasma stability.

[0059] For example, in a low-power mode, the power of the upper electrode (plasma excitation electrode) of the etching equipment is adjusted to 400W to 600W, the power of the lower electrode (sample carrier electrode) of the etching equipment is adjusted to 100W to 180W, and the radio frequency bias voltage is controlled at 50V to 100V.

[0060] In low-power mode, the plasma density is moderate, and the etching rate of F radicals on the barrier layer 40 is higher than that on ITO, avoiding accidental etching damage to the underlying transparent conductive layer 30 and maintaining its ohmic contact performance.

[0061] Among them, CF4 has high etching efficiency for the barrier layer 40 and can reduce etching residue; at the same time, weak ion bombardment at low power can avoid surface roughening of the barrier layer 40, ensuring that the ITO surface within the window is flat and providing a uniform entry point for subsequent wet etching of ITO.

[0062] In this embodiment, ICP etching exhibits strong anisotropy (vertical etching) under CF4 gas and low power, which can form a steep-edged etching window 51, avoiding the lateral diffusion of wet etching and ensuring that the window size is consistent with the design value, especially suitable for the patterning requirements of small-sized pixels below 40μm.

[0063] Step S14 may include the following steps: The first step is to weigh ferric chloride and concentrated hydrochloric acid in a volume ratio of 3:1 to 5:1, stir well, and let stand to defoam. Ferric chloride provides Cl-. - and Fe³ + ITO is dissolved through a redox reaction; HCl enhances the acidity of the solution and inhibits Fe³⁺. + Hydrolysis, and accelerates In³ + The formation of complexes improves corrosion efficiency.

[0064] The second step is to set the corrosion time and corrosion temperature.

[0065] The corrosion time is determined based on the relationship between the thickness of the transparent conductive layer 30 and the corrosion time.

[0066] The corresponding relationship is: T = h × N, where T is the corrosion time in seconds, h is the thickness of the transparent conductive layer in 30 angstroms, and N is the proportionality coefficient, with a value ranging from 0.2 to 0.6.

[0067] By establishing a linear relationship between thickness and etching time, we ensure that ITO is thoroughly etched in the thickness direction while avoiding over-etching and preventing excessive lateral dissolution of ITO at the window edges.

[0068] In this embodiment of the disclosure, when the thickness of the transparent conductive layer 30 is 600 angstroms to 1000 angstroms, the etching time can be 200 s to 360 s.

[0069] For example, if the ITO thickness is 800 angstroms (h=800), and N=0.3, then T=800×0.3=240s; if h=600 angstroms, N=0.33, T≈200s; if h=1000 angstroms, N=0.36, T=360s, ensuring that ITO of different thicknesses can be completely etched without exceeding the time limit.

[0070] Optionally, the corrosion temperature can be between 40°C and 50°C. Specific control procedures may include: placing the corrosion solution in a constant-temperature water bath and heating it to 40°C to 50°C, with real-time monitoring via a thermometer.

[0071] Below 40℃, the reaction rate is slow and residue is easily left behind; above 50℃, the rate is too fast, leading to a surge in lateral corrosion. 45℃ is the equilibrium point, balancing efficiency and precision.

[0072] The third step involves immersing the epitaxial wafer with the barrier layer 40 into the etching solution, and gently shaking the sample (amplitude ≤ 5 mm) during the etching process to promote solution convection.

[0073] The corrosion is confined to the corrosion window 51. The ITO exposed inside the corrosion window 51 reacts with the corrosion liquid and gradually dissolves, while the ITO outside the corrosion window 51, protected by the barrier layer 40, does not participate in the reaction.

[0074] The fourth step is to immediately remove the sample with tweezers after the set etching time has been reached, rinse it three times with deionized water (1 minute each time) to remove any residual etching solution on the surface, and then dry it with nitrogen.

[0075] Then, the ITO inside the window was observed using an optical microscope to see if it was completely removed (no residual bright spots) and whether there was regular lateral etching at the edge (the amount of lateral etching is ≤1μm).

[0076] Remove the product strictly according to the specified time to avoid excessive corrosion, and rinse with deionized water to remove residual Fe². + / In³ +Ions (to prevent subsequent oxidation contamination), nitrogen blowing to avoid water marks, ensuring the cleanliness of the patterned ITO surface, and providing a good interface for subsequent electrode fabrication.

[0077] Step S14 may be followed by the following steps: First step, such as Figure 4 As shown, an alkaline solution is used to remove mask 50.

[0078] Specifically, after wet etching of the transparent conductive layer 30 and subsequent cleaning and drying, the sample is immersed in an alkaline solution at a temperature controlled between 25°C and 35°C for 3 to 8 minutes. During this time, the sample is gently agitated (amplitude ≤ 3 mm) to promote solution penetration, allowing the photoresist (mask 50) to undergo a hydrolysis reaction and gradually dissolve under alkaline conditions. After removal, the sample is rinsed three times with deionized water (2 minutes each time), dried with nitrogen, and confirmed to be free of photoresist residue using an optical microscope.

[0079] For example, alkaline solutions include tetramethylammonium hydroxide solution and KOH solution.

[0080] The second step, as Figure 4 As shown, the barrier layer 40 is removed using a buffered oxide etching solution.

[0081] Specifically, after removing the mask 50, the sample is immersed in buffered oxide etching solution (BOE), which is prepared by volume ratio of ammonium fluoride:hydrofluoric acid = 6:1~10:1, and the temperature is controlled at 20℃ to 25℃.

[0082] Figure 5 This is a top view of a light-emitting diode provided in an embodiment of this disclosure. Figure 6 This is a schematic diagram of the structure of a light-emitting diode (LED) according to an embodiment of this disclosure. The LED is fabricated using the method described above. Figure 5 , 6 As shown, the light-emitting diode includes a substrate 10, an epitaxial layer 20, and a transparent conductive layer 30 stacked sequentially.

[0083] Optionally, the side length of the orthographic projection of the epitaxial layer 20 onto the substrate is less than or equal to 40 μm.

[0084] In the process of fabricating the transparent conductive layer 30, the light-emitting diode provided in this embodiment increases the adhesion of the photoresist by adding a barrier layer 40 to the surface of the transparent conductive layer 30, providing a more stable and highly adhesive substrate for the photoresist. The photoresist can be directly coated on the surface of the barrier layer 40, and its adhesion changes from the "transparent conductive layer 30-photoresist" interface to the "barrier layer 40-photoresist" interface, effectively solving the problem of photoresist detachment in small sizes, ensuring that the pattern defined by photolithography is accurately transferred to the barrier layer 40, thereby avoiding pattern distortion caused by photoresist detachment.

[0085] Meanwhile, the barrier layer 40 serves as an intermediate mask layer. First, a pattern is defined on the surface of the barrier layer 40 using photoresist, and then the barrier layer 40 is etched to form a precise etching window 51. During subsequent wet etching, the transparent conductive layer 30 is etched only within the etching window 51, while the areas of the transparent conductive layer 30 not covered by the window remain tightly protected by the barrier layer 40. In this case, the barrier layer 40 acts as a physical boundary, limiting the lateral diffusion of wet etching, significantly reducing the relative proportion of lateral etching, and making the edge dimensions (such as line width and corner contours) of the transparent conductive layer 30 pattern more stable, especially maintaining high-precision patterns even at small sizes (≤40μm).

[0086] Furthermore, the size and shape of the etching window 51 are precisely controlled by photolithography, so that the etching solution can only penetrate into the transparent conductive layer 30 through the etching window 51. The non-etched area covered by the barrier layer 40 completely isolates the solution, ensuring that the transparent conductive layer 30 is thoroughly etched only within the etching window 51. The etching of difficult-to-process areas such as corners is more uniform, completely eliminating residual transparent conductive layer 30 and irregular trailing, and avoiding the risk of short circuit.

[0087] For example, the substrate is a sapphire substrate. Sapphire substrates have high light transmittance, meaning they are transparent. Furthermore, sapphire material is relatively hard and chemically stable, giving the light-emitting diode (LED) good luminous efficacy and stability.

[0088] For example, the epitaxial layer 20 includes a first semiconductor layer, a multiple quantum well layer and a second semiconductor layer stacked sequentially.

[0089] In this process, one of the first semiconductor layer and the second semiconductor layer is a p-type layer, and the other of the first semiconductor layer and the second semiconductor layer is an n-type layer.

[0090] As an example, the first semiconductor layer is an n-type layer and the second semiconductor layer is a p-type layer.

[0091] Optionally, the first semiconductor layer is an n-type GaN layer. The thickness of the n-type GaN layer can be from 0.5 μm to 1 μm.

[0092] Optionally, the multiple quantum well layer includes alternating InGaN quantum well layers and GaN quantum barrier layers. Specifically, the multiple quantum well layer may include 3 to 8 alternating stacked InGaN quantum well layers and GaN quantum barrier layers.

[0093] As an example, in an embodiment of this disclosure, the multi-quantum-well layer includes five alternating stacked InGaN quantum-well layers and GaN quantum-barrier layers.

[0094] Optionally, the thickness of the multi-quantum well layer can be from 150 nm to 200 nm.

[0095] Optionally, the second semiconductor layer is a p-type GaN layer. The thickness of the p-type GaN layer can be from 0.5 μm to 1 μm.

[0096] For example, the transparent conductive layer 30 includes: an indium tin oxide layer, an aluminum-doped zinc oxide layer, and a fluorine-doped tin oxide layer.

[0097] For example, the thickness of the transparent conductive layer 30 is 200 angstroms to 3000 angstroms.

[0098] The above description is merely an optional embodiment of this disclosure and is not intended to limit this disclosure. The data therein represents only illustrative examples. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this disclosure should be included within the protection scope of this disclosure.

Claims

1. A method for fabricating a light-emitting diode, characterized in that, The preparation method includes: An epitaxial layer (20) is grown on a substrate (10); A transparent conductive layer (30) and a barrier layer (40) are sequentially formed on the surface of the epitaxial layer (20) away from the substrate (10). A mask (50) is formed on the surface of the barrier layer (40), and the barrier layer (40) is etched through the mask (50) to form an etch window (51) that exposes the transparent conductive layer (30). The transparent conductive layer (30) is wet-etched through the etching window (51) to form a patterned transparent conductive layer (30).

2. The preparation method according to claim 1, characterized in that, Forming the barrier layer (40) on the transparent conductive layer (30) includes: A barrier layer (40) with a thickness of 500 to 1000 angstroms is formed on the transparent conductive layer (30).

3. The preparation method according to claim 2, characterized in that, The barrier layer (40) includes at least one of a silicon oxide layer, a silicon nitride layer, and an aluminum oxide layer.

4. The preparation method according to any one of claims 1 to 3, characterized in that, Etching the barrier layer (40) through the mask (50) includes: The upper electrode power of the etching equipment is adjusted to 400W to 600W and the lower electrode power is adjusted to 100W to 180W to etch the barrier layer (40).

5. The preparation method according to any one of claims 1 to 3, characterized in that, Wet etching of the transparent conductive layer (30) through the etching window (51) includes: The transparent conductive layer (30) was etched using a mixed solution of ferric chloride and hydrochloric acid.

6. The preparation method according to claim 5, characterized in that, The wet etching of the transparent conductive layer (30) further includes: The corrosion time is determined based on the correspondence between the thickness of the transparent conductive layer (30) and the corrosion time. The correspondence is: T = h × N, where T is the corrosion time in seconds, h is the thickness of the transparent conductive layer (30) in angstroms, and N is a proportionality coefficient with a value range of 0.2 to 0.

6.

7. The preparation method according to claim 5, characterized in that, The wet etching of the transparent conductive layer (30) further includes etching the transparent conductive layer (30) at a temperature of 40°C to 50°C.

8. The preparation method according to any one of claims 1 to 3 and claims 6 to 7, characterized in that, After wet etching of the transparent conductive layer (30) through the etching window (51), the process further includes: The mask (50) was removed using an alkaline solution. The barrier layer (40) was removed using a buffered oxide etching solution.

9. A light-emitting diode, characterized in that, The light-emitting diode is fabricated using the fabrication method described in any one of claims 1 to 8, comprising a substrate (10), an epitaxial layer (20), and a transparent conductive layer (30) stacked sequentially.

10. The light-emitting diode according to claim 9, characterized in that, The side length of the orthographic projection of the epitaxial layer (20) onto the substrate (10) is less than or equal to 40 μm.

Images