A thick silicon backplane for MEMS differential pressure chips
By using wet etching and silicon-silicon bonding technology to form a thick silicon backplane in MEMS differential pressure chips, the problem of insufficient mechanical strength and thermal stability of thin silicon backplanes in low-stress packaging, high-temperature, and high-vibration environments is solved, and the controllability of thickness and pressure transmission effect are improved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- CHONG QING JIN XIN MAI SI CHUAN GAN QI JI SHU YOU XIAN GONG SI
- Filing Date
- 2025-06-24
- Publication Date
- 2026-06-30
AI Technical Summary
Existing MEMS differential pressure chips typically have thin silicon backplanes, resulting in insufficient mechanical strength and thermal stability in low-stress packaging, high-temperature, and high-vibration environments.
By using wet etching to form through-holes on single-sided and double-sided polished silicon wafers, and forming thick silicon backplanes through silicon-silicon bonding, the thickness of the silicon backplanes can be stacked, and the thickness can exceed 2mm.
It effectively improves the mechanical strength and thermal stability of silicon backplanes, making them suitable for low-stress packaging, high-temperature, and high-vibration environments, and ensuring the linearity and pressure conduction effect of chips under high-pressure environments.
Smart Images
Figure CN224430200U_ABST
Abstract
Description
Technical Field
[0001] This utility model relates to the field of pressure sensing technology for microelectromechanical systems (MEMS), and more particularly to a thick silicon backplate for MEMS differential pressure chips. Background Technology
[0002] In the field of microelectromechanical systems (MEMS), MEMS differential pressure chips, as core devices for achieving accurate pressure measurement and conversion, are widely used in industrial process control, environmental monitoring, medical diagnosis and other scenarios.
[0003] Currently, in traditional MEMS processes, the etching of through-holes in thick silicon backplanes faces thickness limitations, requiring mechanical drilling or laser drilling to achieve through-hole processing for ultra-thick backplanes. However, silicon is a brittle material at room temperature and is easily broken during mechanical drilling; in laser drilling, burrs at the through-hole edges and particles inside the hole are difficult to remove, and particles adhering to the backplane surface can affect subsequent bonding processes. Therefore, silicon backplanes used for MEMS differential pressure chips are typically thin. Thin silicon backplanes suffer from insufficient mechanical strength and thermal stability in applications such as low-stress packaging, high-temperature, and high-vibration environments. Summary of the Invention
[0004] This invention provides a thick silicon backplane for MEMS differential pressure chips, which solves the problem that the silicon backplane thickness of existing MEMS differential pressure chips is usually too thin. Thin silicon backplanes have insufficient mechanical strength and thermal stability when applied to low-stress packaging, high-temperature, and high-vibration environments.
[0005] This utility model provides a thick silicon backplane for MEMS differential pressure chips, comprising:
[0006] A single-sided polished silicon wafer, wherein the single-sided polished silicon wafer has a first through-hole along the thickness direction, the first through-hole being formed by wet etching;
[0007] A double-sided polished silicon wafer, wherein the double-sided polished silicon wafer has a second through hole along the thickness direction, the second through hole being opened corresponding to the first through hole, and the second through hole being formed by wet etching;
[0008] The single-sided polished silicon wafer and the double-sided polished silicon wafer are bonded to form a thick silicon backplate with a composite structure. The unpolished side of the single-sided polished silicon wafer constitutes the first surface of the thick silicon backplate, and the polished side of the double-sided polished silicon wafer constitutes the second surface of the thick silicon backplate.
[0009] In one embodiment of the present invention, a diaphragm layer is further included, wherein the diaphragm layer is bonded to the second surface of the thick silicon backplane to form a differential pressure chip with a composite structure.
[0010] In one embodiment of the present invention, a dielectric cavity is provided between the diaphragm layer and the thick silicon backplate, and the dielectric cavity is connected to the first through hole and the second through hole.
[0011] In one embodiment of this utility model, the single-sided polished silicon wafer is provided with marking points.
[0012] In one embodiment of this utility model, a window is provided on the double-sided polished silicon wafer corresponding to the marked point.
[0013] In one embodiment of this utility model, the marker point is a rectangular marker point, and the window is a rectangular hole.
[0014] In one embodiment of this utility model, the size of the window is larger than the size of the marker point.
[0015] In one embodiment of this utility model, both the single-sided polished silicon wafer and the double-sided polished silicon wafer are 6-inch positive silicon wafers.
[0016] In one embodiment of this utility model, the thickness of both the single-sided polished silicon wafer and the double-sided polished silicon wafer is 0.5 to 1 mm.
[0017] In one embodiment of the present invention, the first through hole and the second through hole form a channel penetrating the thick silicon backplate.
[0018] The beneficial effects of this invention are as follows: This invention proposes a thick silicon backplane for MEMS differential pressure chips. A first through-hole is etched on a single-sided polished silicon wafer using wet etching. A second through-hole is etched on a double-sided polished silicon wafer using wet etching, corresponding to the first through-hole on the single-sided polished silicon wafer. The polished surface of the single-sided polished silicon wafer is then bonded to one side of the double-sided polished silicon wafer via silicon-silicon bonding to form the thick silicon backplane. This effectively achieves the stacking of silicon backplane thickness, improving the controllability of the silicon backplane thickness (thickness can exceed 2mm). After bonding, the first and second through-holes are coaxial, forming a dielectric channel. The thick silicon backplane can be applied to low-stress packaging, high-temperature, and high-vibration environments, effectively solving the problems of insufficient mechanical strength and thermal stability of thin silicon backplanes in these applications. Attached Figure Description
[0019] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application. It is obvious that the drawings described below are merely some embodiments of this application, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.
[0020] In the attached diagram:
[0021] Figure 1 A schematic diagram of the process of bonding a single-sided polished silicon wafer and a double-sided polished silicon wafer to form a thick silicon backplate, according to an embodiment of the present invention.
[0022] Figure 2 for Figure 1 Enlarged schematic diagram of the structure of section A in the middle;
[0023] Figure 3 This is a schematic diagram of the structure of a single-sided polished silicon wafer provided in one embodiment of the present invention;
[0024] Figure 4 This is a schematic diagram of the structure of a double-sided polished silicon wafer provided in one embodiment of the present invention.
[0025] The attached figures are labeled as follows:
[0026] Single-sided polished silicon wafer 1, marker point 101, first through hole 102, double-sided polished silicon wafer 2, window 201, second through hole 202. Detailed Implementation
[0027] The following specific examples illustrate the implementation of this utility model. Those skilled in the art can easily understand other advantages and effects of this utility model from the content disclosed in this specification. This utility model can also be implemented or applied through other different specific embodiments. Various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of this utility model. In the absence of conflict, the following embodiments and features in the embodiments can be combined with each other.
[0028] It should be noted that the illustrations provided in the following embodiments are only schematic representations of the basic concept of the present invention. The drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components. In actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.
[0029] In the following description, numerous details are explored to provide a more thorough explanation of embodiments of the present invention. However, it will be apparent to those skilled in the art that embodiments of the present invention may be practiced without these specific details. In other embodiments, well-known structures and devices are shown in block diagram form rather than in detail to avoid obscuring embodiments of the present invention.
[0030] Please combine Figures 1 to 4 As shown, this utility model provides a thick silicon backplane for MEMS differential pressure chips.
[0031] In an exemplary embodiment of this application, the thick silicon backplane for the MEMS differential pressure chip includes:
[0032] A single-sided polished silicon wafer 1 has a first through hole 102 along the thickness direction, which is formed by wet etching.
[0033] A double-sided polished silicon wafer 2 has a second through hole 202 along the thickness direction. The second through hole 202 is opened corresponding to the first through hole 102. The second through hole 202 is formed by wet etching.
[0034] In this process, a single-sided polished silicon wafer 1 and a double-sided polished silicon wafer 2 are bonded together to form a thick silicon backplate with a composite structure. The unpolished side of the single-sided polished silicon wafer 1 constitutes the first surface of the thick silicon backplate, and the polished side of the double-sided polished silicon wafer 2 on the other side constitutes the second surface of the thick silicon backplate.
[0035] In this embodiment, a composite film of silicon oxide and silicon nitride is used as an etching mask on both sides of the single-sided polished silicon wafer 1 and the double-sided polished silicon wafer 2. KOH is used as the etching solution with a concentration range of 25% to 35% to etch through holes on the single-sided polished silicon wafer 1 and the double-sided polished silicon wafer 2. After etching, the unpolished side of the single-sided polished silicon wafer 1 is temporarily bonded to quartz glass, and any surface of the double-sided polished silicon wafer 2 is temporarily bonded to quartz glass. The temporarily bonded single-sided polished silicon wafer 1 and the double-sided polished silicon wafer 2 are immersed in HF (hydrofluoric acid) solution to remove the mask on the unbonded side. After the mask is removed, it is rinsed with deionized water. After rinsing, the surface of the removed mask is activated using a plasma device. After activation, the activated surfaces of the single-sided polished silicon wafer 1 and the double-sided polished silicon wafer 2 are aligned and bonded to form a thick silicon backplate. A first via 102 is etched on a single-sided polished silicon wafer 1 using wet etching. A second via 202 is etched on a double-sided polished silicon wafer 2 using the same wet etching method. The polished surface of the single-sided polished silicon wafer 1 is then bonded to one side of the double-sided polished silicon wafer 2 via silicon-to-silicon bonding to form a thick silicon backplane. This effectively achieves the stacking of silicon backplane thickness, improving the controllability of the silicon backplane thickness (thickness can exceed 2mm). After bonding, the first via 102 and the second via 202 are coaxial, forming a dielectric channel. The thick silicon backplane can be applied to low-stress packaging, high-temperature, and high-vibration environments, effectively solving the problems of insufficient mechanical strength and thermal stability of thin silicon backplanes in these applications.
[0036] In one exemplary embodiment of this application, a diaphragm layer is also included, which is bonded to the second surface of a thick silicon backplane to form a differential pressure chip with a composite structure.
[0037] In this embodiment, the thick silicon backplate serves as a support structure. When the measured pressure is applied to the diaphragm, the thick silicon backplate can uniformly disperse the stress, avoiding nonlinear deformation caused by stress concentration, and effectively improving the linearity of the chip under high pressure.
[0038] In an exemplary embodiment of this application, a dielectric cavity is provided between the diaphragm layer and the thick silicon backplate, and the dielectric cavity is connected to the first through hole 102 and the second through hole 202.
[0039] In this embodiment, the medium cavity allows the measured medium to act uniformly on the diaphragm layer through the first through hole 102 and the second through hole 202, forming an efficient pressure transmission channel.
[0040] In an exemplary embodiment of this application, a single-sided polished silicon wafer 1 is provided with marking points 101.
[0041] In this embodiment, when the double-sided polished silicon wafer 2 and the single-sided polished silicon wafer 1 are bonded, the marker point 101 serves as a reference for visual alignment, which can effectively ensure the coaxiality of the first through hole 102 and the second through hole 202.
[0042] In an exemplary embodiment of this application, a window 201 is provided on the double-sided polished silicon wafer 2 corresponding to the marker point 101.
[0043] In this embodiment, during the bonding process between the double-sided polished silicon wafer 2 and the single-sided polished silicon wafer 1, the window 201 and the marker point 101 can serve as positioning references to ensure the accurate superposition of the multilayer structure.
[0044] In an exemplary embodiment of this application, the marker point 101 is a rectangular marker point 101, and the window 201 is a rectangular hole.
[0045] In this embodiment, the marker point 101 and window 201 are designed as a rectangular structure, which has a clear edge direction compared to a circular structure, making it easier to identify and locate. The four vertices of the rectangle can serve as precise coordinate reference points, and the recognition accuracy of the rectangular structure is higher than that of the circular structure.
[0046] In one exemplary embodiment of this application, the size of window 201 is larger than the size of marker point 101.
[0047] In this embodiment, by designing the size of window 201 to be larger than the size of marker point 101, the positional deviation that may occur during the bonding process is effectively compensated.
[0048] In an exemplary embodiment of this application, both the single-sided polished silicon wafer 1 and the double-sided polished silicon wafer 2 are 6-inch positive silicon wafers.
[0049] In this embodiment, 6-inch silicon wafers are a mature and standardized size in the semiconductor industry, with a complete supporting industrial chain including production equipment, photomasks, and packaging molds. Using wafers of this size allows for the direct reuse of existing production line resources, avoiding the costs of customized development.
[0050] In an exemplary embodiment of this application, the thickness of both the single-sided polished silicon wafer 1 and the double-sided polished silicon wafer 2 is 0.5 to 1 mm.
[0051] In this embodiment, the thickness of a single silicon wafer is between 0.5 and 1 mm, which satisfies the etching requirements of the wet etching process for the vias; in the bonding process, the silicon wafer with a thickness of 0.5 to 1 mm exhibits good thermal stress uniformity.
[0052] In an exemplary embodiment of this application, the first through-hole 102 and the second through-hole 202 form a channel penetrating the thick silicon backplane.
[0053] In this embodiment, the first through hole 102 and the second through hole 202 form a through channel, so that the pressure to be measured can act directly and without obstruction on the diaphragm layer.
[0054] The working principle involves etching a first via 102 on a single-sided polished silicon wafer 1 using wet etching, and then etching a second via 202 on a double-sided polished silicon wafer 2 using the same wet etching method. The polished surface of the single-sided polished silicon wafer 1 is then bonded to one side of the double-sided polished silicon wafer 2 via silicon-to-silicon bonding to form a thick silicon backplane. This effectively achieves the stacking of silicon backplane thickness, improving the controllability of the silicon backplane thickness (thickness can exceed 2mm). After bonding, the first via 102 and the second via 202 are coaxial, forming a dielectric channel. The thick silicon backplane can be applied to low-stress packaging, high-temperature, and high-vibration environments, effectively solving the problems of insufficient mechanical strength and thermal stability of thin silicon backplanes in these applications.
[0055] The above embodiments are merely illustrative of the principles and effects of this utility model and are not intended to limit the scope of this utility model. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of this utility model. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in this utility model should still be covered by the claims of this utility model.
Claims
1. A thick silicon backplate for a MEMS differential pressure chip, characterized in that, include: A single-sided polished silicon wafer, wherein the single-sided polished silicon wafer has a first through-hole along the thickness direction, the first through-hole being formed by wet etching; A double-sided polished silicon wafer, wherein the double-sided polished silicon wafer has a second through-hole along the thickness direction, the second through-hole being formed corresponding to the first through-hole by wet etching; The single-sided polished silicon wafer and the double-sided polished silicon wafer are bonded to form a thick silicon backplate with a composite structure. The unpolished side of the single-sided polished silicon wafer constitutes the first surface of the thick silicon backplate, and the polished side of the double-sided polished silicon wafer constitutes the second surface of the thick silicon backplate.
2. The thick silicon backplate for a MEMS differential pressure chip of claim 1, wherein: It also includes a diaphragm layer, which is bonded to the second surface of the thick silicon backplane to form a differential pressure chip with a composite structure.
3. The thick silicon backplate for a MEMS differential pressure chip of claim 2, wherein: A dielectric cavity is provided between the diaphragm layer and the thick silicon backplate, and the dielectric cavity is connected to the first through hole and the second through hole.
4. The thick silicon backplate for a MEMS differential pressure chip of claim 1, wherein: The single-sided polished silicon wafer has marking points.
5. The thick silicon backplate for a MEMS differential pressure chip of claim 4, wherein: The double-sided polished silicon wafer has windows corresponding to the marked points.
6. The thick silicon backplate for a MEMS differential pressure chip of claim 5, wherein: The marker point is a rectangular marker point, and the window is a rectangular hole.
7. The thick silicon backplate for a MEMS differential pressure chip of claim 6, wherein: The size of the window is larger than the size of the marker point.
8. The thick backplane for a MEMS differential pressure chip of claim 1, wherein: Both the single-sided polished silicon wafer and the double-sided polished silicon wafer are 6-inch positive silicon wafers.
9. The thick silicon backplate for a MEMS differential pressure chip of claim 8, wherein: The thickness of both the single-sided polished silicon wafer and the double-sided polished silicon wafer is 0.5 to 1 mm.
10. The thick silicon backplate for a MEMS differential pressure chip of claim 1, wherein: The first through hole and the second through hole form a channel penetrating the thick silicon backplane.