A display panel

Abstract

This utility model discloses a display panel having a display area and a non-display area surrounding the display area. The display panel includes: a color filter substrate, the color filter substrate including a black matrix layer and a color resist layer; the black matrix layer having a first annular opening surrounding the display area in the non-display area, and the color resist layer having an annular color resist dam surrounding the display area in the non-display area, the orthographic projection of the first annular opening on the color resist layer being within the range of the annular color resist dam; and an array substrate disposed opposite to the color filter substrate; the array substrate including a first common electrode line located in the non-display area and surrounding the display area, the orthographic projection of the first annular opening on the array substrate being within the range of the first common electrode line.

Description

Technical Field

[0001] This utility model relates to the field of display technology, and in particular to a display panel. Background Technology

[0002] During use, display products may generate static electricity due to contact, friction, etc.

[0003] Static electricity entering the display product can easily burn out the circuitry, leading to display product failure. To prevent static electricity from entering the display panel, related technologies typically incorporate an annular opening around the display area within the black matrix of the display panel. However, because this annular opening is located between the sealing adhesive and the display area, light leakage is common at the opening location.

[0004] To prevent light leakage from the ring-shaped opening, a light-shielding structure is usually set on one side of the ring-shaped opening, which increases the width of the display panel's bezel, making it unsuitable for narrow bezel designs. Utility Model Content

[0005] This utility model provides a display panel to solve the above-mentioned technical problems existing in the prior art.

[0006] In a first aspect, to solve the above-mentioned technical problems, this utility model embodiment provides a display panel having a display area and a non-display area surrounding the display area, including:

[0007] A color filter substrate, the color filter substrate including a black matrix layer and a color resist layer; the black matrix layer has a first annular opening surrounding the display area in the non-display area, and the color resist layer has an annular color resist dam surrounding the display area in the non-display area, the orthographic projection of the first annular opening on the color resist layer being located within the range of the annular color resist dam.

[0008] An array substrate is disposed opposite to the color filter substrate; the array substrate includes a first common electrode line located in the non-display area and surrounding the display area, and the first annular opening is located within the range of the first common electrode line in the orthogonal projection of the array substrate.

[0009] In one possible implementation, the array substrate further includes:

[0010] First substrate;

[0011] Multiple gate lines are located on the side of the first substrate close to the color filter substrate; the gate lines and the first common electrode lines are disposed in the same layer and of the same material.

[0012] An insulating layer is located on the side of the plurality of gate lines away from the first substrate. The insulating layer has a plurality of first through-holes. The first through-holes adopt a semi-via-hole structure, in which a part of the semi-via-hole structure is a deep hole region and another part is a shallow hole region. The portion of the first substrate overlapping with the deep hole region of the first through-hole forms part of the bottom of the first through-hole, and the portion of the first common electrode line overlapping with the shallow hole region of the first through-hole forms the other part of the bottom of the first through-hole. The first through-holes and the first annular opening do not overlap.

[0013] A common electrode layer is located on the side of the insulating layer away from the first substrate; the common electrode layer covers the first common electrode line and is connected to the first common electrode line and the first substrate within the first through hole.

[0014] In one possible implementation, the array substrate further includes:

[0015] Multiple pixel electrodes are located in the display area;

[0016] Multiple auxiliary signal lines are disposed on the same layer and made of the same material as the gate lines; the auxiliary signal lines are located between the multiple gate lines and the first common electrode line, and do not overlap with the pixel electrode; the common electrode layer covers the multiple auxiliary signal lines;

[0017] In the second direction, the distance between the first auxiliary signal line and the last auxiliary signal line among the plurality of auxiliary signal lines is less than or equal to the length of the pixel electrode in the second direction.

[0018] In one possible implementation, the array substrate further includes:

[0019] Multiple data lines are arranged in a different layer from the multiple gate lines;

[0020] Multiple first-fan outgoing lines and multiple second-fan outgoing lines are configured in the same layer and with the same material as the data line;

[0021] The first connecting block is connected between the first fan-out line and the gate line;

[0022] The second connecting block is connected between the second fan-out line and the auxiliary signal line; wherein, the orthographic projection of the first connecting block and the second connecting block on the first substrate is located between the orthographic projection of the first common electrode line on the first substrate and the orthographic projection of the display area on the first substrate.

[0023] The first connecting block and the second connecting block are disposed in the same layer and material as the common electrode and do not overlap with each other.

[0024] In one possible implementation, the orthographic projection of the end of the gate line near the first fan-out line on the first substrate is parallel to the orthographic projection of the end of the first fan-out line near the gate line on the first substrate.

[0025] At least one second through hole is provided at the end of the gate line near the end of the first fan-out line. A portion of the second through hole in the orthographic projection of the first substrate is located within the orthographic projection of the end of the gate line on the first substrate. The second through hole also adopts the semi-via structure. The portion of the first substrate overlapping with the deep hole region of the second through hole serves as part of the bottom of the second through hole, and the portion of the gate line overlapping with the shallow hole region of the second through hole serves as the other part of the bottom of the second through hole. The first connecting block is connected to the gate line and the substrate within the second through hole.

[0026] At least one third through hole is provided at the end of the first fan-out line near the end of the gate line. A portion of the third through hole is located within the orthographic projection of the first substrate in the first substrate. The third through hole also adopts the semi-via structure. The portion of the first substrate overlapping with the deep hole region of the third through hole serves as part of the bottom of the third through hole. The portion of the first fan-out line overlapping with the shallow hole region of the third through hole serves as another part of the bottom of the third through hole. The first connecting block is connected to the first fan-out line and the first substrate in the third through hole.

[0027] In one possible implementation, the orthographic projection of the end of the second fan-out line near the auxiliary signal line onto the first substrate is located in a portion of the orthographic projection of the end of the auxiliary signal line near the second fan-out line onto the first substrate.

[0028] At least one fourth through hole is provided at the end of the auxiliary signal line away from the second fan-out line. A portion of the fourth through hole in the orthographic projection of the first substrate is located within the orthographic projection of the end of the auxiliary signal line on the first substrate. The fourth through hole also adopts the semi-via structure. The portion of the first substrate overlapping with the deep hole region of the fourth through hole serves as part of the bottom of the fourth through hole. The portion of the auxiliary signal line overlapping with the shallow hole region of the fourth through hole serves as another part of the bottom of the fourth through hole. The second connecting block is connected to part of the end of the auxiliary signal line and the first substrate within the fourth through hole.

[0029] At least one fifth through hole is provided in the area where the end of the auxiliary signal line overlaps with the second fan-out line; the fifth through hole penetrates the membrane layer between the second connecting block and the second fan-out line, and the second connecting block is connected to the second fan-out line in the fifth through hole.

[0030] In one possible implementation, the center line of the first common electrode line roughly coincides with the center line of the first annular opening.

[0031] In one possible implementation, the distance between the edge of the first annular opening in the orthographic projection of the array substrate and the corresponding edge of the first common electrode line is greater than or equal to the cell alignment error between the array substrate and the color filter substrate.

[0032] In one possible implementation, the color resist layer includes a blue color resist, and the annular color resist dam is disposed in the same layer and made of the same material as the blue color resist.

[0033] In one possible implementation, the orthogonal projection of the first common electrode line onto the color filter substrate is located within the annular color resist dam.

[0034] In one possible implementation, the distance between the edge of the first common electrode line in the orthographic projection of the color filter substrate and the edge of the annular color dam is greater than or equal to the cell alignment error between the array substrate and the color filter substrate.

[0035] In one possible implementation, the annular color barrier is spaced apart from the display area.

[0036] In one possible implementation, each column of color resist in the display area extends into the non-display area and connects to the annular color resist dam.

[0037] One possible implementation involves providing at least one column of auxiliary color resists in the area of ​​the non-display area near the display area.

[0038] In one possible implementation, the display panel further includes:

[0039] A sealing adhesive is used to bond the color filter substrate and the array substrate in the non-display area.

[0040] The black matrix layer also has a second annular opening surrounding the first annular opening in the non-display area, and the sealing adhesive covers the second annular opening and does not overlap with the first annular opening.

[0041] In one possible implementation, the distance between the edge of the second annular opening and the edge of the sealing adhesive is greater than or equal to the sum of the positional fluctuation tolerance and diffusion tolerance of the sealing adhesive. Attached Figure Description

[0042] Figure 1 A top view of a black matrix provided for an embodiment of this utility model;

[0043] Figure 2 A display panel provided for an embodiment of this utility model Figure 1 Cross-sectional view of position A'A in the middle;

[0044] Figure 3 A top view of a color filter substrate provided for an embodiment of this utility model;

[0045] Figure 4 A partial top view of a color filter substrate provided for an embodiment of this utility model;

[0046] Figure 5 A partial top view of another color filter substrate provided in an embodiment of this utility model;

[0047] Figure 6 A top view of a black matrix layer provided in an embodiment of this utility model;

[0048] Figure 7 Provided for the embodiments of this utility model Figure 6 Cross-sectional view of B'B;

[0049] Figure 8 A partial schematic diagram of an array substrate provided for an embodiment of this utility model;

[0050] Figure 9 Provided for the embodiments of this utility model Figure 8 Cross-sectional view of C'C;

[0051] Figure 10 This is a schematic diagram of a full via design;

[0052] Figure 11 A schematic diagram of the diffusion of the alignment film in a semi-perforated structure provided for an embodiment of this utility model;

[0053] Figure 12 and Figure 13 A partial schematic diagram of another array substrate provided in an embodiment of this utility model;

[0054] Figure 14 A partial schematic diagram of another array substrate provided in an embodiment of this utility model;

[0055] Figure 15 Provided for the embodiments of this utility model Figure 14 A top view of the end of the grid line and the end of the corresponding first fan-out line within the coverage area of ​​the first connecting block;

[0056] Figure 16Provided for the embodiments of this utility model Figure 14 A top view of the end of the auxiliary signal line and the end of the corresponding second fan-out line within the coverage area of ​​the second connecting block.

[0057] Figure label:

[0058] Display area AA, non-display area BB, color filter substrate 1, second substrate substrate 11, black matrix layer 12, color resist layer 13, first annular opening K1, annular color resist dam 131, array substrate 2, first substrate substrate 21, first common electrode line 22, sealing glue 3, auxiliary color resist 132, color resist 133, second annular opening K2, gate line 23, insulating layer 24, first through hole H1, common electrode layer 25, second direction Y, pixel electrode 26, auxiliary signal line 27, switch transistor T, data line 28, first fan-out line 231, first connecting block 232, second fan-out line 271, second connecting block 272, alignment film 29, second common electrode line 22'. Detailed Implementation

[0059] This utility model provides a display panel to solve the above-mentioned technical problems existing in the prior art.

[0060] It should be understood that the specific structural and functional details disclosed in the embodiments of this utility model are merely representative and are intended to describe exemplary embodiments of this application. However, this application can be implemented in many alternative or combined forms and should not be construed as being limited solely to the embodiments set forth herein.

[0061] In the description of this application, it should be understood that the terms "center," "lateral," "upper," "lower," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," and "outer," etc., indicating orientation or positional relationships based on the orientation or positional relationships shown in the accompanying drawings, are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, unless otherwise stated, "a plurality of" means two or more. Additionally, the term "comprising" and any variations thereof are intended to cover non-exclusive inclusion.

[0062] In this embodiment of the invention, the term "and / or" is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent three situations: A existing alone, A and B existing simultaneously, and B existing alone. Additionally, the character " / " in this document generally indicates that the preceding and following related objects have an "or" relationship.

[0063] To make the above-mentioned objects, features, and advantages of this utility model more apparent and understandable, the utility model will be further described below in conjunction with the accompanying drawings and embodiments. However, the exemplary embodiments can be implemented in many forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided to make the utility model more comprehensive and complete, and to fully convey the concept of the exemplary embodiments to those skilled in the art. The same reference numerals in the figures denote the same or similar structures, and therefore repeated descriptions of them will be omitted. Terms describing position and direction in this utility model are illustrative based on the accompanying drawings, but changes can be made as needed, and all such changes are included within the scope of protection of this utility model. The accompanying drawings of this utility model are for illustrating relative positional relationships only and do not represent actual proportions.

[0064] It should be noted that specific details are set forth in the following description to provide a full understanding of the present invention. However, the present invention can be implemented in many ways other than those described herein, and those skilled in the art can make similar extensions without departing from the spirit of the present invention. Therefore, the present invention is not limited to the specific embodiments disclosed below. The following description is a preferred embodiment for carrying out the present application; however, the description is for the purpose of illustrating the general principles of the present application and is not intended to limit the scope of the present application. The scope of protection of the present application shall be determined by the appended claims.

[0065] The following description, in conjunction with the accompanying drawings, details a display panel provided in an embodiment of the present invention.

[0066] Please refer to Figure 1 and Figure 2 , Figure 1 A top view of a black matrix provided in an embodiment of this utility model. Figure 2 A display panel provided for an embodiment of this utility model Figure 1 A cross-sectional view at position A'A shows a display panel with a display area AA and a non-display area BB surrounding the display area AA. The display panel includes:

[0067] like Figure 1 As shown, the color filter substrate 1 includes a black matrix layer 12 and a color resist layer 13; as Figure 2The black matrix layer 12 shown has a first annular opening K1 surrounding the display area AA in the non-display area BB, and the color resist layer 13 has an annular color resist dam 131 surrounding the display area AA in the non-display area BB. The orthographic projection of the first annular opening K1 in the color resist layer 13 is located within the range of the annular color resist dam 131. The color filter substrate 1 also includes a second substrate 11 located on the side of the black matrix layer 12 away from the color resist layer 13, and the color resist layer 13 is located on the side of the black matrix layer 12 closer to the array substrate 2.

[0068] An array substrate 2 is disposed opposite to a color filter substrate 1. The array substrate 2 includes a first common electrode line 22 located in the non-display area BB and surrounding the display area AA. The first annular opening K1 is located within the range of the first common electrode line 22 in the orthogonal projection of the array substrate 2. The array substrate 2 also includes a first substrate 21 located on the side of the first common electrode line 22 away from the color filter substrate 1. After the color filter substrate 1 and the array substrate 2 are assembled, a sealing adhesive 3 is disposed along the edges of the first substrate 21 and the second substrate 11 to bond the color filter substrate 1 and the array substrate 2 together.

[0069] The first common electrode line 22 is made of a metallic material, for example, it can be disposed in the same layer and material as the gate metal layer in the array substrate 2. Since the orthogonal projection of the first annular opening K1 on the array substrate 2 is within the range of the first common electrode line 22, and the first common electrode line 22 has the characteristic of blocking light, the light from the backlight can be blocked by the first common electrode line 22, thereby preventing the light from the backlight from leaking out from the first annular opening K1.

[0070] However, within the liquid crystal cell formed by the array substrate 2 and the color filter substrate 1, light from the display area AA may be scattered and refracted into the non-display area BB and exit through the first annular opening K1, or ambient light may enter the liquid crystal cell through the first annular opening K1, be reflected and refracted, and then exit through the first annular opening K1. This results in some light leakage at the first annular opening K1. In this invention, an annular color barrier dam 131 is also provided in the color filter substrate 1 to block the first annular opening K1, thereby further improving the light leakage phenomenon of the first annular opening K1.

[0071] In some embodiments, the annular color-blocking dam 131 can be disposed in the same layer and with the same material as at least one color color resist 133 in the color-blocking layer 13. For example, the annular color-blocking dam 131 can be disposed in the same layer and with the same material as the blue color resist. Since the blue color resist has low light transmittance, disposing the annular color-blocking dam 131 in the same layer and with the blue color resist can better block the light emitted from the first annular opening K1, thereby better improving the light leakage problem of the first annular opening K1. The annular color-blocking dam 131 can also be composed of multiple layers of color resist 133 stacked together. Different layers of color resist 133 are disposed in the same layer and with the same material as color resist 133 of different colors. For example, the annular color-blocking dam 131 can include 2 or 3 layers of color resist 133. Taking 3 layers of color resist 133 as an example, these 3 layers of color resist 133 can be disposed in the same layer with the red color resist, green color resist, and blue color resist, respectively. This can improve the light-blocking effect of the annular color-blocking dam 131.

[0072] In the embodiment provided by this utility model, by setting a first annular opening K1 around the display area AA in the non-display area BB of the black matrix layer 12, the black matrix layer 12 is divided into two unconnected parts (the part of the first annular opening K1 away from the display area AA can be called the outer part, and the part of the first annular opening K1 close to the display area AA can be called the inner part). When static electricity enters the outer part of the black matrix layer 12, it will be weakened by the outer part, and weakened again after reaching the first annular opening K1. This makes it difficult for static electricity to enter the display area AA through the black matrix layer 12, thereby preventing static electricity from entering the display area AA. Within area A; because a first common electrode line 22 and an annular color barrier dam 131 that can block light are respectively provided on both sides of the first annular opening K1, it is difficult for any kind of light to pass through the first annular opening K1, thereby effectively preventing light leakage from the first annular opening K1. The first common electrode line 22 that provides light blocking for the first annular opening K1 is already present in the array substrate 2, so it does not additionally increase the width of the non-display area BB of the array substrate 2, which facilitates the implementation of a narrow bezel design. Therefore, this utility model can prevent static electricity from entering the display area AA, prevent light leakage from the first annular opening K1, and facilitate the implementation of a narrow bezel design. In addition, since the entire design utilizes existing materials and processes, it does not increase material costs or processes.

[0073] like Figure 2 As shown, the width W1 of the first annular opening K1 ranges from 8 to 15 μm.

[0074] Please continue to refer to this. Figure 2 The distance d1 between the edge of the first annular opening K1 projected onto the array substrate 2 and the corresponding edge of the first common electrode line 22 is greater than or equal to the cell alignment error between the color filter substrate 1 and the array substrate 2. For example, if the cell alignment error between the color filter substrate 1 and the array substrate 2 is 4.5 μm, then d1 can be set to a minimum of 4.5 μm.

[0075] By setting the distance d1 between the edge of the first annular opening K1 projected onto the array substrate 2 and the corresponding edge of the first common electrode line 22 to be greater than or equal to the cell alignment error between the color filter substrate 1 and the array substrate 2, it can be ensured that the first common electrode line 22 can cover the first annular opening K1 after the array substrate 2 and the color filter substrate 1 are aligned, thus preventing backlight from emitting through the first annular opening K1 and causing light leakage.

[0076] In some embodiments, the center line of the first common electrode line 22 is approximately coincident with the center line of the first annular opening K1. Ideally, the center line of the first common electrode line 22 and the center line of the first annular opening K1 should coincide. However, in actual production, due to errors such as box alignment and process errors, the center line of the first common electrode line 22 and the center line of the first annular opening K1 cannot be perfectly coincident. Instead, there is a certain degree of misalignment. This should all be regarded as the center line of the first common electrode line 22 and the center line of the first annular opening K1 being approximately coincident.

[0077] By aligning the center line of the first common electrode line 22 with the center line of the first annular opening K1, it is possible to better ensure that the first common electrode line 22 covers the first annular opening K1, thereby improving the light leakage problem of the first annular opening K1.

[0078] Please continue to refer to this. Figure 2 The first common electrode line 22 is projected onto the color filter substrate 1 within the annular color barrier dam 131, which helps to reduce the bezel width of the display panel and achieve a narrow bezel design.

[0079] Please continue to refer to this. Figure 2 The distance d2 between the edge of the first common electrode line 22 in the orthographic projection of the color filter substrate 1 and the edge of the annular color dam 131 is greater than or equal to the cell alignment error between the array substrate 2 and the color filter substrate 1. This ensures that after the array substrate 2 and the color filter substrate 1 are aligned, the first common electrode line 22 and the annular color dam 131 can cover the first annular opening K1, thereby preventing light leakage from the first annular opening K1.

[0080] Please continue to refer to this. Figure 2 The annular color barrier 131 is spaced apart from the display area AA, which reduces the interference of the annular color barrier 131 on the normal display of the display area AA.

[0081] In some embodiments, the distance d3 between the annular color barrier 131 and the display area AA is ≥100μm, which ensures that the annular color barrier 131 does not interfere with the normal display of the display area AA.

[0082] In some embodiments, the area between the annular color blocking dam 131 and the display area AA can be covered by the black matrix layer 12.

[0083] Please refer to Figure 3 This is a top view of a color filter substrate provided in an embodiment of the present invention, wherein each column of color resist 133 in the display area AA extends into the non-display area BB and is connected to the annular color resist dam 131. Figure 3 The dashed box in the middle shows the orthographic projection area of ​​the pixel opening.

[0084] For example, an auxiliary color resistor 132 is made between the non-display area BB and the annular color resistor dam 131, and the auxiliary color resistor 132 in the column direction is connected to the annular color resistor dam 131.

[0085] It's important to understand that when manufacturing color resist 133, one column of color resist 133 on the same layer corresponds to one color resist 133 channel. Therefore, in Figure 3 It is shown in the form of a 133-channel color filter.

[0086] By extending each column of color resist 133 in the display area AA into the non-display area BB and connecting it with the annular color resist dam 131, the color resist 133 material in the non-display area BB can be used to block light in the area between the display area AA and the annular color resist dam 131, while also interfering with the normal display of the display area AA, which is beneficial to improving the display effect.

[0087] Please refer to Figure 4 This is a partial top view of a color filter substrate provided in an embodiment of the present invention. At least one column of auxiliary color resists 132 is provided in the area near the display area AA in the non-display area BB.

[0088] like Figure 4 As shown, three columns of auxiliary color resistors 132 can be set on one side of the display area AA in the non-display area BB. The color arrangement of the auxiliary color resistors 132 is the same as that of the color resistors 133 in the display area AA. Figure 3 The image only shows the three columns of auxiliary color resistors 132 on the left side of the display area. In reality, three columns of auxiliary color resistors 132 can also be set on the right side of the display area AA. Of course, one column of auxiliary color resistors 132 can also be set on each side of the display area AA. The specific number of columns of auxiliary color resistors 132 is not limited here.

[0089] At least one column of auxiliary color resist 132 is provided in the area near the display area AA in the non-display area BB, which can improve the color effect at the edge of the display area AA while preventing light leakage.

[0090] Please refer to the following for further information. Figure 4 The auxiliary color resist 132 column furthest from the display area AA is set in the same layer and with the same material as the blue color resist 133. Of course, the auxiliary color resist 132 column furthest from the display area AA can also be set in the same layer and with the same material as the color resist 133 of other colors.

[0091] Please refer to Figure 5 This is a partial top view of another color filter substrate provided in an embodiment of the present utility model. If there is a gap between the multiple rows of auxiliary color resists 132 and the annular color resist dam 131, color resist 133 material can be filled between the multiple rows of auxiliary color resists 132 and the annular color resist dam 131. The color resist 133 material can be any color resist 133 material, for example, it can be the same color resist 133 material as the blue color resist 133.

[0092] By filling the space between the multi-column auxiliary color resist 132 and the annular color resist dam 131 with color resist 133 material, the light-blocking performance can be improved by using the filled color resist 133 material. When using blue color resist 133 material, the light-blocking performance is better than that of color resist 133 material of other colors.

[0093] Please refer to Figure 6 and Figure 7 , Figure 6 A top view of a black matrix layer provided in an embodiment of this utility model. Figure 7 Provided for the embodiments of this utility model Figure 7 The cross-sectional view of B'B in the middle, the display panel also includes:

[0094] The sealing adhesive 3 is bonded between the color filter substrate 1 and the array substrate 2 in the non-display area BB.

[0095] The black matrix layer 12 also has a second annular opening K2 surrounding the first annular opening K1 in the non-display area BB. The sealing adhesive 3 covers the second annular opening K2 and does not overlap with the first annular opening K1.

[0096] By having a second annular opening K2 surrounding the first annular opening K1 in the non-display area BB of the black matrix layer 12, and the sealing adhesive 3 covering the second annular opening K2 without overlapping with the first annular opening K1, the black matrix layer 12 can be divided into three unconnected parts using the first annular opening K1 and the second annular opening K2. This prevents static electricity from entering the display area AA by using the two outermost parts of the black matrix layer 12 and the first and second annular openings K1 and K2. Furthermore, since the second annular opening K2 is located in the area covered by the sealing adhesive 3, the bezel width of the display panel will not be increased due to the setting of the second annular opening K2, which facilitates the implementation of a narrow bezel design. At the same time, the sealing adhesive 3 can also be used to shield the second annular opening K2 from light to prevent light leakage.

[0097] The centerline of the second annular opening K2 roughly coincides with the centerline of the sealing adhesive 3, which ensures that the sealing adhesive 3 completely covers the second annular opening K2.

[0098] Please continue to refer to this. Figure 7 The width W2 of the second annular opening K2 ranges from 8 to 15 μm.

[0099] The distance d4 between the edge of the second annular opening K2 and the edge of the sealing adhesive 3 is greater than or equal to the sum of the positional fluctuation tolerance and diffusion tolerance of the sealing adhesive 3. For example, if the sum of the positional fluctuation tolerance and diffusion tolerance of the sealing adhesive 3 is 180μm, then d4≥180μm.

[0100] When the sealant 3 is applied, there is usually positional fluctuation, and the sealant 3 also has a certain fluidity before curing, which causes the sealant 3 to spread near the application position. By setting the distance d4 between the edge of the sealant 3 and the edge of the second annular opening K2 to be greater than or equal to the sum of the positional fluctuation tolerance and the diffusion tolerance of the sealant 3, it can be ensured that the sealant 3 can always cover the second annular opening K2.

[0101] Please refer to Figure 8 and Figure 9 , Figure 8 This is a partial schematic diagram of an array substrate provided in an embodiment of the present invention. Figure 9 Provided for the embodiments of this utility model Figure 8 The cross-sectional view of C'C shows that the array substrate 2 also includes:

[0102] First substrate 21;

[0103] Multiple gate lines 23 are located on the side of the first substrate 21 close to the color filter substrate 1; the gate lines 23 and the first common electrode line 22 are disposed in the same layer and with the same material;

[0104] An insulating layer 24 is located on the side of the multiple gate lines 23 away from the first substrate 21. The insulating layer 24 has multiple first vias H1. The first vias H1 adopt a semi-via structure, with a part of the semi-via structure being a deep via region and another part being a shallow via region. The part of the first substrate 21 overlapping with the deep via region of the first via H1 serves as part of the bottom of the first via H1, and the part of the first common electrode line 22 overlapping with the shallow via region of the first via H1 serves as the other part of the bottom of the first via H1. The first via H1 and the first annular opening K1 do not overlap. The insulating layer 24 is usually composed of multiple sub-insulating layers. For details, refer to the film structure of the conventional array substrate 2. The first via H1 overlaps with the first common electrode line 22 in the orthographic projection of the first substrate 21, and the other part is located on the side of the first common electrode line away from the display area AA. This facilitates the formation of a stepped structure composed of the first substrate 21 and the first common electrode line 22 at the bottom of the first via H1.

[0105] The common electrode layer 25 is located on the side of the insulating layer 24 away from the first substrate 21; the common electrode layer 25 covers the first common electrode line 22 and is connected to the first common electrode line 22 and the first substrate 21 in the first through hole H1.

[0106] The common electrode layer 25 forms a semi-overlap structure with the portion of the first common electrode line 22 located in the shallow hole region within the first through hole H1. That is, a portion of the common electrode layer 25 overlaps with the portion of the first common electrode line 22 located in the shallow hole region within the first through hole H1, while the other portion is located on the surface of the first substrate 21 and has no contact with the first common electrode line 22.

[0107] Please refer to Figure 10 This is a schematic diagram of a full via design. If the first through hole H1 is adopted... Figure 10 In the full via design, after coating the alignment film 29 on the side of the common electrode layer 25 away from the first substrate 21, the alignment film 29 has fluidity during coating, resulting in more alignment film 29 accumulating at the bottom of deeper vias (e.g., ...). Figure 10 (As shown in the two through-holes of different depths), resulting in uneven diffusion of the alignment film 29.

[0108] Please refer to Figure 11 This is a schematic diagram of the diffusion of the alignment film in a semi-perforated structure provided by an embodiment of the present invention. Since the semi-perforated structure has a deep pore region and a shallow pore region, the alignment film 29 can be gradient transitioned between the deep pore region and the shallow pore region of the semi-perforated structure when it is coated, thereby improving the diffusion uniformity of the alignment film 29.

[0109] The area of ​​the portion of the first common electrode line 22 projected onto the first substrate 21 and located in the first through hole H1 can be 1 / 2 or 3 / 4 of the projected area of ​​the first through hole H1 onto the first substrate 21, or other proportions, without any specific limitation.

[0110] Since the common electrode layer 25 is connected to the first common electrode line 22 and the first substrate 21 within the first through hole H1, and there is a height difference between the first common electrode line 22 and the first substrate 21, the bottom of the first through hole H1 has a gradient change. This facilitates the uniform diffusion of the alignment film 29 when it is fabricated on the side of the common electrode layer 25 away from the first substrate 21, thereby effectively improving the display effect of the display panel. At the same time, it also allows the common electrode layer 25 to be connected to the first common electrode line 22 within the first through hole H1, which facilitates the first common electrode line 22 to provide a common voltage to the common electrode layer 25.

[0111] Please continue to refer to this. Figure 9The edge width W3 of the first via H1 is greater than or equal to 1.9 μm, which ensures that the common electrode layer 25 completely covers the first substrate 21 within the first via H1. As shown in Figure 10, if the surface of the first substrate 21 is not covered by the common electrode layer 25, the alignment film 29 will diffuse between the first substrate 21 and the insulating layer 24 when the alignment film 29 is coated. However, this invention sets the edge width W3 of the first via H1 to be greater than or equal to 1.9 μm to ensure that the common electrode layer 25 completely covers the first substrate 21 within the first via H1, thereby effectively preventing the alignment film 29 from diffusing between the first substrate 21 and the insulating layer 24.

[0112] The width W4 of the portion of the first through hole H1 that does not overlap with the first common electrode line 22 on the orthographic projection of the first through hole H1 is greater than or equal to 1.9 μm. This ensures that a stepped structure is formed at the bottom of the first through hole H1, so that the common electrode layer 25 is connected to the first substrate 21 and the first common electrode line 22 at the bottom of the first through hole H1, respectively.

[0113] The width W5 of the portion where the first through hole H1 overlaps with the first common electrode line 22 is greater than or equal to 2.1 μm, which ensures that the common electrode layer 25 and the first common electrode line 22 are effectively connected.

[0114] Please refer to Figure 12 and Figure 13 This is a partial schematic diagram of another array substrate provided in an embodiment of the present invention, wherein... Figure 12 The common electrode layer 25 is not shown in the diagram. Figure 13 exist Figure 12 In addition to the common electrode layer 25, the array substrate 2 also includes:

[0115] Multiple pixel electrodes 26 are located in the display area AA; the pixel electrodes 26 can be disposed in the same layer and material as the gate line 23.

[0116] like Figure 12 As shown, multiple auxiliary signal lines 27 are disposed on the same layer and made of the same material as the gate lines 23; the auxiliary signal lines 27 are located between the multiple gate lines 23 and the first common electrode line 22, and do not overlap with the pixel electrode 26; as Figure 13 As shown, the common electrode layer 25 covers multiple auxiliary signal lines 27;

[0117] In the second direction Y, the distance d4 between the first auxiliary signal line 27 and the last auxiliary signal line 27 among the multiple auxiliary signal lines 27 is less than or equal to the length L of the pixel electrode 26 in the second direction Y.

[0118] Unlike the gate line 23 in the display area AA, the auxiliary signal line 27 does not need to be connected to the pixel electrode 26 through the switching transistor T. The switching transistor T connected to the gate line 23 includes the gate Tg, the first electrode Ta, and the second electrode Tb. A part of the data line 28 is multiplexed as the first electrode Ta, and the second electrode Tb is connected to the pixel electrode 26. However, the switching transistor T connected to the auxiliary signal only has the gate and the first electrode. In the second direction Y, the distance d4 between the first auxiliary signal line 27 and the last auxiliary signal line 27 is less than or equal to the length L of the pixel electrode 26 in the second direction Y. This can reduce the length occupied by the multiple auxiliary signal lines 27. In this way, the multiple auxiliary signal lines 27 can be used to reset the display panel after the display panel completes the display of a frame to balance the load of the display panel, and the length occupied by the auxiliary signals can be reduced, which is convenient for the narrow bezel design.

[0119] Please continue to refer to 13. The display surface also includes a second common electrode line 22'. The second common electrode line 22' extends in the same direction as the data line 28 and is made of the same material and layer as the data line 28. The second common electrode line 22' extends to the first common electrode line 22 and is connected to the first common electrode line 22 through a connecting hole. The via connecting the first common electrode line 22 and the second common electrode line 22' can be a full via design. The second common electrode line 22' provides a common voltage for the common electrode.

[0120] It should be noted that, in Figure 8 , Figure 12 A column of auxiliary pixels is also set on the left side of the central display area AA. Since the auxiliary pixels do not participate in the display, the data line 28 corresponding to the auxiliary pixels extends to the first common electrode line 22 and is connected to the first common electrode line 22, so that it does not float and does not receive data signals.

[0121] Please refer to Figure 14 This is a partial schematic diagram of another array substrate provided in an embodiment of the present invention. The array substrate 2 further includes:

[0122] Multiple data lines 28 are arranged in a different layer from multiple gate lines 23;

[0123] Multiple first-side cables 231 and multiple second-side cables 271 are designed with the same layer and material as the data cable 28;

[0124] The first connecting block 232 is connected between the first fan-out line 231 and the grid line 23;

[0125] The second connecting block 272 is connected between the second fan-out line 271 and the auxiliary signal line 27; wherein, the first connecting block 232 and the second connecting block 272 are located between the orthographic projection of the first common electrode line 22 on the first substrate 21 and the orthographic projection of the display area AA on the first substrate 21.

[0126] The first connecting block 232 and the second connecting block 272 are disposed in the same layer and with the same material as the common electrode, and do not overlap with each other.

[0127] Because the first connecting block 232 connecting the first fan-out line 231 and the gate line 23, and the second connecting block 272 connecting the second fan-out line 271 and the data line 28 are disposed between the first common electrode line 22 and the display area AA, and the first fan-out line 231 and the second fan-out line 271 are disposed on the same layer and made of the same material as the data line 28, the first fan-out line 231 and the second fan-out line 271 are disposed on different layers from the first common electrode line 22. This ensures that the first fan-out line 231 and the second fan-out line 271 will not intersect with the first common electrode line 22 when passing through the orthographic projection area of ​​the first common electrode line 22 on the first substrate 21. This facilitates the placement of driving circuits or bonding pins corresponding to the first fan-out line 231 and the second fan-out line 271 outside the orthographic projection area of ​​the first common electrode line 22 on the first substrate 21.

[0128] Please refer to Figure 15 Provided for the embodiments of this utility model Figure 14 A top view of the ends of the grid lines and the corresponding ends of the first fan-out lines within the coverage area of ​​the first connecting block.

[0129] The end of the gate line 23 near the first fan-out line 231 is arranged parallel to the orthographic projection of the first substrate 21 and the end of the first fan-out line 23 near the gate line 23 in the orthographic projection of the first substrate 21.

[0130] At least one second through hole H2 is provided at the end of the gate line 23 near the end of the first fan-out line 231. A portion of the second through hole H2 in the orthographic projection of the first substrate 21 is located within the orthographic projection of the end of the gate line 23 in the first substrate 21. The second through hole H2 also adopts a semi-through hole structure. The portion of the first substrate 21 overlapping with the deep hole region of the second through hole H2 serves as part of the bottom of the second through hole, and the portion of the gate line 23 overlapping with the shallow hole region of the second through hole H2 serves as the other part of the bottom of the second through hole H2. The first connecting block 232 is connected to the gate line 23 and the substrate in the second through hole H2. That is, the first connecting block 232 in the second through hole H2 forms a semi-overlapping structure with the portion of the first connecting block 232 located in the shallow hole region. That is, a portion of the first connecting block 232 in the second through hole H2 overlaps with the portion of the first connecting block 232 located in the shallow hole region, and the other portion is located on the surface of the first substrate 21 and does not contact the first connecting block 232.

[0131] At least one third through-hole H3 is provided at the end of the first fan-out line 231 near the end of the gate line 23. A portion of the third through-hole H3 in the orthographic projection of the first substrate 21 is located within the orthographic projection of the end of the first fan-out line 231 on the first substrate 21. The third through-hole H3 also adopts a semi-through-hole structure. The portion of the first substrate 21 overlapping with the deep hole region of the third through-hole H3 forms part of the bottom of the third through-hole H3, and the portion of the first fan-out line 231 overlapping with the shallow hole region of the third through-hole H3 forms the other part of the bottom of the third through-hole H3. The first connecting block 232 is connected to the first fan-out line 231 and the first substrate 21 within the third through-hole. That is, the first connecting block 232 in the third through-hole H3 forms a semi-overlapping structure with the portion of the first connecting block 232 located in the shallow hole region. That is, a portion of the first connecting block 232 in the third through-hole H3 overlaps with the portion of the first connecting block 232 located in the shallow hole region, while the other portion is located on the surface of the first substrate 21 and does not contact the first connecting block 232.

[0132] Cross-sectional views of the semi-through-hole structures of the second and third through holes can be referenced. Figure 9 I will not go into details here.

[0133] Of course, since the distance between the first fan-out line 231 and the first substrate 21 is greater than that between the gate line 23 and the first substrate 21, even if the third via adopts a full via design, it will not have a significant impact on the diffusion of the alignment film 29. Therefore, the third via can also adopt a full via design.

[0134] The end of the gate line 23 near the end of the first fan-out line 231 is parallel to the orthographic projection of the first fan-out line 231 near the end of the gate line 23 on the first substrate 21. At least one second through hole is provided at the end of the first fan-out line 231 near the end of the gate line 23. A portion of the second through hole in the orthographic projection of the first fan-out line 231 is located within the orthographic projection of the first substrate 21, which facilitates setting the second through hole H2 as a semi-through hole structure. Since the second through hole H2 adopts a semi-through hole structure, the alignment film 29 is uniformly diffused in the region where the second through hole H2 is located. Similarly, at least one third through hole H3 is provided at the end of the first fan-out line 231 near the end of the gate line 23. A portion of the third through hole H3 in the orthographic projection of the first fan-out line 231 is located within the orthographic projection of the first substrate 21, which facilitates setting the third through hole H3 as a semi-through hole structure, which allows the alignment film 29 to diffuse uniformly in the region where the third through hole H3 is located.

[0135] Please refer to Figure 16 Provided for the embodiments of this utility model Figure 14 A top view of the end of the auxiliary signal line and the end of the corresponding second fan-out line within the coverage area of ​​the second connecting block.

[0136] The end of the second fan-out line 271 near the auxiliary signal line 27 is located in a portion of the orthographic projection of the auxiliary signal line 27 near the second fan-out line 271 onto the first substrate 21.

[0137] At least one fourth through hole H4 is provided at the end of the auxiliary signal line 27 away from the second fan-out line 271. A portion of the fourth through hole H4 in the orthographic projection of the first substrate 21 is located within the orthographic projection of the end of the auxiliary signal line 27 in the first substrate 21. The fourth through hole H4 also adopts a semi-through hole structure. The portion of the first substrate 21 overlapping with the deep hole region of the fourth through hole H4 serves as part of the bottom of the fourth through hole H4, and the portion of the auxiliary signal line 27 overlapping with the shallow hole region of the fourth through hole H4 serves as the other part of the bottom of the fourth through hole H4. The second connecting block 272 is connected to part of the end of the auxiliary signal line 27 and the first substrate 21 in the fourth through hole H4. That is, the second connecting block 272 forms a semi-overlapping structure with the portion of the second connecting block 272 located in the shallow hole region in the fourth through hole H4. That is, a portion of the second connecting block 272 in the first through hole H4 overlaps with the portion of the second connecting block 272 located in the shallow hole region, and the other portion is located on the surface of the first substrate 21 and does not contact the second connecting block 272.

[0138] At least one fifth through hole H5 is provided in the area where the end of the auxiliary signal line 27 overlaps with the second fan-out line 271; the fifth through hole H5 penetrates the membrane layer between the second connecting block 272 and the second fan-out line 271, and the second connecting block 272 is connected to the second fan-out line 271 in the fifth through hole H5.

[0139] Figure 16 The fourth through hole H4 adopts a 1 / 4 half through hole structure, that is, the area of ​​the first substrate 21 in the deep hole area of ​​the fourth through hole H4 accounts for 1 / 4 of the area of ​​the fourth through hole H4. Of course, the above area ratio can be adjusted according to the wiring of the auxiliary signal line 27, such as adjusting it to 1 / 2, or it can be adjusted to other ratios, which are not limited here.

[0140] By positioning the end of the second fan-out line 271 within the orthographic projection of the auxiliary signal line 27 onto the first substrate 21, and by providing at least one fourth through-hole H4 at the end of the auxiliary signal line 27 away from the second fan-out line 271, with a portion of the fourth through-hole H4 located within the orthographic projection of the auxiliary signal line 27 onto the first substrate 21, it is easier to configure the fourth through-hole H4 as a semi-via structure, thereby allowing the alignment film 29 to diffuse uniformly in the area where the fourth through-hole H4 is located. At least one fifth through-hole H5 is provided in the area where the end of the auxiliary signal line 27 overlaps with the second fan-out line 271. The fifth through-hole H5 penetrates the film layer between the second connecting block 272 and the second fan-out line 271. Since the depth of the fifth through-hole H5 is small, it has little impact on the diffusion of the alignment film 29.

[0141] The display panel can be a liquid crystal display (LCD), an organic light-emitting diode (OLED) display panel, a quantum dot light-emitting diode (QLED) display panel, a micro light-emitting diode (Micro LED) display panel, etc., and this utility model does not specifically limit it.

[0142] Although preferred embodiments of the present invention have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of the present invention.

[0143] Obviously, those skilled in the art can make various modifications and variations to this utility model without departing from its spirit and scope. Therefore, if these modifications and variations fall within the scope of the claims of this utility model and their equivalents, this utility model also intends to include these modifications and variations.

Claims

1. A display panel having a display area and a non-display area surrounding the display area, characterized in that, include: A color filter substrate, the color filter substrate including a black matrix layer and a color resist layer; the black matrix layer has a first annular opening surrounding the display area in the non-display area, and the color resist layer has an annular color resist dam surrounding the display area in the non-display area, the orthographic projection of the first annular opening on the color resist layer being located within the range of the annular color resist dam. An array substrate is disposed opposite to the color filter substrate; the array substrate includes a first common electrode line located in the non-display area and surrounding the display area, and the first annular opening is located within the range of the first common electrode line in the orthogonal projection of the array substrate.

2. The display panel as described in claim 1, characterized in that, The array substrate further includes: First substrate; Multiple gate lines are located on the side of the first substrate close to the color filter substrate; the gate lines and the first common electrode lines are disposed in the same layer and of the same material. An insulating layer is located on the side of the plurality of gate lines away from the first substrate. The insulating layer has a plurality of first through-holes. The first through-holes adopt a semi-via-hole structure, in which a part of the semi-via-hole structure is a deep hole region and another part is a shallow hole region. The portion of the first substrate overlapping with the deep hole region of the first through-hole forms part of the bottom of the first through-hole, and the portion of the first common electrode line overlapping with the shallow hole region of the first through-hole forms the other part of the bottom of the first through-hole. The first through-holes and the first annular opening do not overlap. A common electrode layer is located on the side of the insulating layer away from the first substrate; the common electrode layer covers the first common electrode line and is connected to the first common electrode line and the first substrate within the first through hole.

3. The display panel as described in claim 2, characterized in that, The array substrate further includes: Multiple pixel electrodes are located in the display area; Multiple auxiliary signal lines are disposed on the same layer and made of the same material as the gate lines; the auxiliary signal lines are located between the multiple gate lines and the first common electrode line, and do not overlap with the pixel electrode; the common electrode layer covers the multiple auxiliary signal lines; In the second direction, the distance between the first auxiliary signal line and the last auxiliary signal line among the plurality of auxiliary signal lines is less than or equal to the length of the pixel electrode in the second direction.

4. The display panel as described in claim 3, characterized in that, The array substrate further includes: Multiple data lines are arranged in a different layer from the multiple gate lines; Multiple first-fan outgoing lines and multiple second-fan outgoing lines are configured in the same layer and with the same material as the data line; The first connecting block is connected between the first fan-out line and the gate line; The second connecting block is connected between the second fan-out line and the auxiliary signal line; wherein, the orthographic projection of the first connecting block and the second connecting block on the first substrate is located between the orthographic projection of the first common electrode line on the first substrate and the orthographic projection of the display area on the first substrate. The first connecting block and the second connecting block are disposed in the same layer and material as the common electrode and do not overlap with each other.

5. The display panel as described in claim 4, characterized in that, The orthographic projection of the end of the gate line near the first fan-out line on the first substrate is parallel to the orthographic projection of the end of the first fan-out line near the gate line on the first substrate. At least one second through hole is provided at the end of the gate line near the end of the first fan-out line. A portion of the second through hole in the orthographic projection of the first substrate is located within the orthographic projection of the end of the gate line on the first substrate. The second through hole also adopts the semi-via structure. The portion of the first substrate overlapping with the deep hole region of the second through hole serves as part of the bottom of the second through hole, and the portion of the gate line overlapping with the shallow hole region of the second through hole serves as the other part of the bottom of the second through hole. The first connecting block is connected to the gate line and the substrate within the second through hole. At least one third through hole is provided at the end of the first fan-out line near the end of the gate line. A portion of the third through hole is located within the orthographic projection of the first substrate in the first substrate. The third through hole also adopts the semi-via structure. The portion of the first substrate overlapping with the deep hole region of the third through hole serves as part of the bottom of the third through hole. The portion of the first fan-out line overlapping with the shallow hole region of the third through hole serves as another part of the bottom of the third through hole. The first connecting block is connected to the first fan-out line and the first substrate in the third through hole.

6. The display panel as described in claim 4, characterized in that, The orthographic projection of the end of the second fan-out line near the auxiliary signal line onto the first substrate is located in a portion of the orthographic projection of the end of the auxiliary signal line near the second fan-out line onto the first substrate. At least one fourth through hole is provided at the end of the auxiliary signal line away from the second fan-out line. A portion of the fourth through hole in the orthographic projection of the first substrate is located within the orthographic projection of the end of the auxiliary signal line on the first substrate. The fourth through hole also adopts the semi-via structure. The portion of the first substrate overlapping with the deep hole region of the fourth through hole serves as part of the bottom of the fourth through hole. The portion of the auxiliary signal line overlapping with the shallow hole region of the fourth through hole serves as another part of the bottom of the fourth through hole. The second connecting block is connected to part of the end of the auxiliary signal line and the first substrate within the fourth through hole. At least one fifth through hole is provided in the area where the end of the auxiliary signal line overlaps with the second fan-out line; the fifth through hole penetrates the membrane layer between the second connecting block and the second fan-out line, and the second connecting block is connected to the second fan-out line in the fifth through hole.

7. The display panel as described in any one of claims 1-6, characterized in that, The center line of the first common electrode line roughly coincides with the center line of the first annular opening.

8. The display panel as described in any one of claims 1-6, characterized in that, The distance between the edge of the first annular opening in the orthographic projection of the array substrate and the corresponding edge of the first common electrode line is greater than or equal to the cell alignment error between the array substrate and the color filter substrate.

9. The display panel as described in any one of claims 1-6, characterized in that, The color resist layer includes a blue color resist, and the annular color resist dam is made of the same material and layer as the blue color resist.

10. The display panel as described in any one of claims 1-6, characterized in that, The first common electrode line is projected onto the color filter substrate within the annular color dam.

11. The display panel as claimed in claim 10, characterized in that, The distance between the edge of the first common electrode line in the orthographic projection of the color filter substrate and the edge of the annular color dam is greater than or equal to the cell alignment error between the array substrate and the color filter substrate.

12. The display panel as described in any one of claims 1-6, characterized in that, The annular color barrier is spaced apart from the display area.

13. The display panel as claimed in claim 12, characterized in that, Each column of color resist in the display area extends into the non-display area and connects to the annular color resist dam.

14. The display panel as claimed in claim 13, characterized in that, At least one column of auxiliary color resist is provided in the area of ​​the non-display area near the display area.

15. The display panel as described in any one of claims 1-6, characterized in that, The display panel also includes: A sealing adhesive is used to bond the color filter substrate and the array substrate in the non-display area. The black matrix layer also has a second annular opening surrounding the first annular opening in the non-display area, and the sealing adhesive covers the second annular opening and does not overlap with the first annular opening.

16. The display panel as claimed in claim 15, characterized in that, The distance between the edge of the second annular opening and the edge of the sealing adhesive is greater than or equal to the sum of the positional fluctuation tolerance and diffusion tolerance of the sealing adhesive.

Images